TW200818453A - Semiconductor package on which a semiconductor device is stacked and production method thereof - Google Patents

Semiconductor package on which a semiconductor device is stacked and production method thereof Download PDF

Info

Publication number
TW200818453A
TW200818453A TW095137477A TW95137477A TW200818453A TW 200818453 A TW200818453 A TW 200818453A TW 095137477 A TW095137477 A TW 095137477A TW 95137477 A TW95137477 A TW 95137477A TW 200818453 A TW200818453 A TW 200818453A
Authority
TW
Taiwan
Prior art keywords
circuit board
electrical connection
substrate
semiconductor package
connection structure
Prior art date
Application number
TW095137477A
Other languages
English (en)
Other versions
TWI312569B (en
Inventor
Han-Ping Pu
Chien-Ping Huang
Chih-Ming Huang
Yu-Po Wang
Cheng-Hsu Hsiao
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW095137477A priority Critical patent/TWI312569B/zh
Priority to US11/974,441 priority patent/US7679178B2/en
Publication of TW200818453A publication Critical patent/TW200818453A/zh
Application granted granted Critical
Publication of TWI312569B publication Critical patent/TWI312569B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16151—Cap comprising an aperture, e.g. for pressure control, encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Description

200818453 •九、發明說明： 【發明所屬之技術領域】 種球柵陣列 本發明係關於一種半導體封裝件，尤指 (BGA, Ball Grid Away)式半導體封裝件。 【先前技術】 電子產品在小型化之餘’仍要求性能與處理速度之提 升。提升性能與處理速度之較佳方法，不外乎是增加半導 參體封裝件中之晶片數量或尺寸’惟供晶片接置之基板上所 能使用之面積往往無法供複數個晶片水平設置或較大尺寸 之^的置放。故而，目前之發展乃著眼於複數個晶片上 下堆，之堆疊式多晶片模組（Stakable multi_chip则加⑹。 是種堆疊式多晶片模組之結構，係如第5,222,〇14號 •吳國專制*者’乃將—上層半導體縣件料塊（s〇lder Joims)或銲球（solder Balls)疊接並電性連接至下層半導體 封t件，以在基板之尺寸不變之情況下，藉由堆疊之方式 ⑩增加晶片之數量而達成提升模組之性能與處理速度之要 求。然而，如第7圖所示，堆疊式多晶片模組7令之鲜球 72乃分別銲接至上層半導體封裝件7()之基板的下表 面700a上所佈設之銲墊7〇〇1)及下層半導體封裝件？！之基 板710的上表面71〇a上所佈設之銲墊71补，使上層半導 體封裝件70與下層半導體封裝件71間之電性連接關係合 受到銲墊7_及710b之數量的影響。亦即，欲使上^ 導體封裝件70中之晶片701具較多之I/O連接點⑽曰 connections)，則須增加基板7〇〇之下表面7〇如上所佈設 19305 6 200818453 •之銲墊700b的數量，然而，增加了銲墊7〇〇b的數量，則 會使下層半導體封裝件71之封裝膠體712之尺寸縮小，進 而使封I膠體712所包覆之晶片7 Π亦須縮小，而限制住 下層半導體封裝件71之晶片711所能適用的型式；反之， ★若所欲之下層半導體封裝件71之晶片711之尺寸較大，則 、會影響至基板700之下表面70〇&上所能佈設之銲墊7〇讣 的數里，§知墊700b之數量減少，代表提供予上層半導體 _封裝件7〇0< 1/0連接點會減少，故會限制住封裝件7⑽ 適用型式。簡言之，是種堆疊式多晶片模組7中之晶片的 選用會受到銲墊數目及封裝件型式之影響，導致其運用受 到限制，而無法允符不同之需求。 件二銲 =3封層半㈣封裝 1 逐接下層基板710之銲墊710b 能太大’否則會限制形成之輝球高Μ;亦即， 、干東回度H有其特定限制走 裝體712之古声導體封裝件71之封 裝膠體719々^ & 力又係肩在以下，然而封 ^ 回度限制會影響到用以電性連接日71 1 $ 基板71〇之鋥綠71,从》曰A 电旺遷接日日片711至 71之_賴性不# 線品f ’導致下層半導體封裝件 若干ip著門韻土。故而’是種堆疊式多晶片模組7仍存在 丁礦者問題而亟待改良。 廿仕 為解決上述問題，遂有第 利權人同於本荦之申咬人、植，，665唬吳國專利案（專 板結合於封裝勝體中出一種將具外露銲墊之電路 封裳件能藉銲球堆疊並電= 少另-半導體 連接至该具外露銲墊電路板之 19305 7 200818453 ° 8 ^ -τιφ 800 …' 板80係藉多數顆銲球81銲接至一接置有曰 U之基板83上，而使該電路板8〇經由 接=曰曰片 4^球81電性連 缺後Γ於兮其f使該晶片82位於電路板80與基板83間， ; 該基板83上形成-包覆該晶片82、銲球8… 知墊8(Π外露出該封裝膠體84;因而，所形成之 丨="㈣面上植設有銲球85ι之另一半導體封裝件 ^宜於5亥電路板8〇之外露頂面_上，且因銲球85,係銲 接至该電路板80上之頂面銲塾8〇1，使該另一半導壯 件8’能電性連接至位於其下方之半導體封|件8。、衣 是種半導體封袭件8中之晶片82與用以供另 體封I件8'堆疊其上之電路板8〇係同時包覆於封裝膠體 队故電路板80底面謝上可供設置底面鲜塾，之 不會受到封裝膠體84之干涉，使晶片82之尺寸或型式選貝 #用與底面銲墊803之佈設（layout)具有較前述之第 5,222,014號美國專利所揭示之構造為大之自由度，而能有 效解決該第5,222,014號美國專利所存在之問題。然而' 該半導體封裝件8之晶片82於電路板8〇藉銲球81辉接至 基板83上時未為封裝膠體84所包覆，故在進行銲球“ 回鮮(Reflow)至基板83時’其兩溫會影響電性連接晶片η 至基板8 3之銲線8 6的品質，而其助銲劑（f丨u χ)會造成晶片 82與基板83之污染，導致完成封裝之半導體封裝件^存 在有品質及信賴性問題。 19305 8 200818453 為解決前述使用銲球電性連接供堆疊另一封裝件之 電路板至基板上所產生之問題，第6,861，288號美國專利 乃提出-種毋須使用銲球以電性連接基板與供堆疊另一封 裝件之電路板的半導體封裝件。如第9圖所示，該苐 、6,861，288號美國專利所揭示之半導體封裝件9係使用一具 支撐腳9〇1之金屬承載件9〇架設於一基板…上，以承載 一供堆疊另一封裝件用之電路板92，使該電路板％支撐 •於接置在該基板91上之日日日片93的上方，且該金屬承载件 係藉如導熱膠（Thermally Conductive Glue)或膠片 (Film Adhesive)之分隔件（Spacer)94結合至晶片，一封 裝膠體95並形成於該基板91上，以包覆該金屬承载件 0電路板92、晶片93、分隔件94，但使該電路板92之 部分頂S 920夕卜露出封裝缪體95，而令形成於外露之部分 =面920上之銲墊921能與另一半導體封裝件9,之銲球％， 在干接，俾使另一半導體封裝件9’能藉由該銲球96,盥該半 •導體封裝件9電性祕。此外，該半導體封裝件^晶片 93乃藉多數第—銲線97電性連接至基板91，而該電路板 ^則藉多數第二銲線98電性連接至基板9卜且為包覆該 第二銲線98,該封裝膠體95之頂面㈣即須高於電路板 92之外露頂面920，而在該外露頂面92〇上形成一凹a 951。 八 、該半導體封裝件9之電路板92雖毋須藉由銲球電性 連接至基板91，然而，該電路板92須使用金屬承载件卯 架設於晶片9 3之上方，不惟增加龍製程之複雜性，且亦 9 19305 200818453 導致成本之增加；同時，該電路板92係與金屬承載件90 面與面（Surface-to-Surface)結合，金屬承載件90與分隔件 94係面與面之結合，以及分隔件94係與晶片93面與面結 合，使該半導體封裝件9存在多個面與面接觸之介面 (Interface)，導致該半導體封裝件9在製程之溫度循環 (Temperature Cycle)及製成後之工作狀態中，易於介面處產 生脫層現象（Delamination)，而造成產品之信賴性與品質問 題；再而，為包覆線弧高度（Height of Wire Loop)高出電路 ®板92之外露頂面920的第二銲線98，並使該電路板92上 之銲墊921能外露出封裝膠體95，如第10圖所示，用以 形成封裝膠體95之模具Μ須使用具突出部（Insertion)之上 模M!，俾具有形成能完整包覆第二銲線98而高出電路板 92之外露頂面920之部分的封裝膠體95,是種規格特殊之 上模的使用，遂會增加製成該半導體封裝件9之成本。 因而，如何提供一種得有效解決前揭問題之可供堆疊 ❿半導體裝置之半導體封裝件，乃成一亟待完成之課題。 【發明内容】 本發明之主要目的即在於提供一種堆疊用之半導體 裝置之型式與I/O連接點數量不會受限的可供堆疊半導體 裝置之半導體封裝件及其製法。 本發明之另一目的在提供一種封裝膠體之大小不會 影響所包覆之晶片型式及對應供堆疊用之半導體裝置所需 之I/O連接點數量的可供堆疊半導體裝置之半導體封裝件 及其製法。 10 19305 200818453 種封^體之高度不合 又限於八所包後之晶片的可供堆疊 曰 裝件及其製法。 置之半導體封 本發明之再-目的在提供一種供堆 ，：:性連接結構毋須藉鲜球焊接至承載該電性連；二:之 基板’而無因回銲作業導致晶片及基板受到污毕之=之 疊半導體裝置之半導體封裝件及其製法。、了 i、堆 ❿本發明之又-目的在提供一種毋須使用金屬承 :口供堆疊半導體裝置用之電性連接結構於晶 牛 堆璺半導體裝置之半導體封裝件及其製法。 Ti、 本發明之再-目的在提供一種毋須使用特殊模 不致增加製造成本之可供堆疊半導封 及其製法。 千令體封i件 為達成前揭及其它目的，本發明乃提供 ，裝置之半導趙封裝件，係包括-基板，具有ί、數; 多η:!二銲墊;至少一接置於該基板上之晶片’· 勒外一 ^接70件，用以電性連接該晶片至基板之多 數弟-銲墊；接置於該基板上之電性連接結構，其係由上 2電路板與電性連接至該上層電路板之下層電路板所構 下展ΐ上層電路板亚具多數銲塾，且該上層電路板係藉該 :層電路板之支撐而懸空於該晶片之上方；多數第二電性 連接凡件，用以電性連接該下層電路板至該基板之多數第 :銲塾’以使該電性連接結構電性連接至該基板；以及形 成於該基板上之封裝膠體’用以包覆該晶片、多數第一電 19305 11 200818453 性連接元件、多數第二電性連接元 使該電性連接結構之上層電路板上 構，但 裝膠體，以供至少一半導體裝置堆疊外露出該封 上層電路板上，並藉該多數銲墊 .連接結構之 連接。 堅而兵該+導體封裝件電性 該電性連接結狀上層電路㈣藉銲_接並電性 接板:使該銲料之回銲處理係於該電性連 接、、，。構接置至基板上前即完成，亦即該回銲作 ： 電性連接結構時實施，且電性連接該 /、’、夕成 用之第二電性連接元件料料^ 肖構至基板 性連接I接置並電性連接該電 1·生連接、、'。構至基板之作業均毋需回鲜處理，遂 與基板及影響第二電性連接元件之品質的問題曰曰片 該下層電路板之尺寸小於上層電路板，且係以兩片下 層電路板接置於上層電路板底面相對之兩侧上、或以四片 下層電路板接置於上層電路板底面之四側上，俾在上層電 路板之底面下方形成一由該上層電路板與下層電路板所定 義出之收納空間，以由該收納空間收納接置於基板上之晶 片及用以電性連接該晶片與基板之第—電性連接元件。 该電性連接結構亦得為成對之上層電路板錯位疊接 於下層電路板上之單元所構成者，以進一步降低材料成本。 "弟龟丨生連接元件仔為焊線或鲜塊（solder bumps 〇 ) 田第一電性連接元件為銲塊時，該晶片即係以覆晶方式 (Flip Chip)方式與基板形成電性連接關係。 本發明所提供之可供堆疊半導體裝置之半導體封裝 12 19305 200818453 件的製法，係包括下列步驟·制 性連接钍槿係由卜爲千 衣一電性連接結構，該電 電路板與電性連接至該上層電路板之 執运包路板所構成’該下層電路板並形成有多數第三鮮 μ該上層電路板亦並形成有多數第四鲜塾，且位於該上 :電路板之下方復由該上層電路板及下層電路板定義出— 收:空間；將該電性連接結構黏置於一接置有至少一晶片 ^ 土板上’並使該晶諸納於該電性連接結構之收 二’其中’該基板上係形成有多數第—銲塾及多數第二在 由第-電性連接元件電性連接該晶片至基板:之 、二數第二電性連接元件電性連接該電性 社構弟二鲜塾至基板之第二婷塾，而使該電性連接 基板形成電性連接關係；以及，於該基板上形成— 缺衣t體’以包覆該晶片’多數第一電性連接元件、多數 2一电性連接元件、及電性連接結構，但使該電性連接結 •少上之第四銲塾外露出該封裝勝體，俾供至 疊於該電性連接結構之上層電路板上， ”精遠多數第四銲墊而與該半導體封裝件電性連接。 本發明所提供之可供堆疊半導體震置之半導體 2之製法的另—實施態樣，係在前述之電性連接結構形成 =於該j電路板形成有多數第四銲墊之表面上黏貼一 夕…以覆盍住該多數第四銲墊，俾防止該多數第 =績步驟中受到污染，而影響至該第四銲塾與半導體裝 封°且在㈣_體形成後’該夥片係未為 、”-所覆盍’將該膠片自電性連接結構之上層電路板 19305 13 200818453 上撕除，即能將該上層 露出封穿豚妒 斤形成之多數第四銲墊外 之體，而毋須對上層電路板之外露頂面進行清洗 二===裝膠體之形成毋須特殊模具之 之虞。再而，該電性連接：；構製造上無增加成本 n 4 "稱係以鋅線電性連接於其扼μ 以銲球電性連接基板，故無回銲處理之需要二’ 發明之半導體封裝件之信賴性與品質。 此 【實施方式】 ' 式二特定的具體實施例說明本發明之實施方 式Α自此技蟄之人士可由本說明書 =一及功效。本發明亦可藉由其 施方，加以施行或應用，本說明書中的各項細節亦可基於 不同親點與應用，在不脖離本發明所揭示之精神下賦予不. 同之修倚與變更。 不 下述之實施例與配合之圖式，為使本發明之特徵及結 構更為清晰易懂，僅說明並顯示出與本發明直接關聯者，。 其餘部分則予以略除。 羞一實施例
^切麥閱第1A及1B圖，其係顯示本發明第一實施例之 半導體封裝件i之下視圖及第1A圖沿1B_1B線剖開之剖 視圖。該半導體封裝件i主要係由基板1〇、黏置於基板 上之晶片11、接置於該基板10上之電性連接結構12及形 成於該基板10上並用以包覆該晶片u與電性連接結構U 19305 14 200818453 之封裝膠體13所構成。 如圖所不，該基板10為一球栅陣列式（B all_Grid_Amy Type)基板，亦即，該基板10之底面1〇2上係形成有多數 成陣列方式設置之銲球塾⑽lpads)102a，以供鲜球14植 接於該銲球塾黯上，以作為該半導體封裝件i與如印刷 電路板(Printed Circuit Board)之外界裝置形成電性連接關 係之介質。該銲球墊102a之形成及銲球墊1〇2a與銲球14 修之銲接均同於習知技藝，故在此不予詳述。該基板1〇之頂 面104上位於供該晶片u黏置之晶片接置區（Die_M〇unt Area’其所在位置由圖式能清楚得知，故不另予圖號標示） 外之區域上，係分別形成有多數之第一銲墊1〇4a及多數之 第一銲墊104b，使其位置關係為第一銲墊1〇4&位於較接 近晶片11處而第二銲墊104b則位於較遠離晶片u處；更 具體言之，該多數第一銲墊104a位於基板1〇之頂面1〇4 上為該電性連接結構12所覆蓋之區域内，而該多數第二銲 _墊104b則位於基板1 〇之頂面！ 〇4上為該電性連接結構^ 2 所覆蓋之區域外。 該曰曰片11係藉習知之銀膠（Silver paste)或聚醯亞胺膠 片（PolyimideFilm)黏固於基板1〇之頂面1〇4上。該晶片 11上並形成有多數之電性連接墊（C〇n£juctive pa(js)〗i〇，使 多數第一金線15(Au wire)各能以其一端銲接至晶片〗]上 之對應電性連接墊110,而另一端銲接至基板1〇上對應之 第一銲墊104a，以電性連接該晶片u至基板1〇。 該電性連接結構12則係由四片下層電路板120及接 15 19305 200818453 置於該下層電路板120上之上層電路板121所構成。該下 層书路板120之面積係小於該上層電路板121，且該下層 電路板120分別環接於上層電路板121之底面上/使各^ 層電路板120均突伸出上層電路板121之側邊ΐ2ι〇以在 .^電性連接結構12中形成出一收納空間122，供該晶片j j 與弟一金線15收納於該收納空間122内；亦即，該收納空 間122之大小須足以充分收納該晶片丨丨與第一金線Μ， _令該第一金線15不致碰觸至該電性連接結構12。各該下 層電路板120係具有一下表面12〇a及一相對之上表面 u〇b，該上表面120b上並形成有多數第三銲墊12〇\及多 數與該第三銲墊120c電性連接之第四 鲜一位於該下層電路板12〇之上表㈣二 電路板121所覆蓋之處，而第四銲墊12〇d則位於該下層電 路板120之上表面12〇]3未為上層電路板121覆蓋之處上。 同％’该電性連接結構12乃藉一般之膠黏劑以下層電路板 _ 12〇之下表面120a黏結至該基板10之頂面104上。 該上層電路板121亦具有下表面121a及相對之上表 面121b，該下表面121a對應該下層電路板之第三銲 墊120c處並形成有多數之銲墊121χ，該上表面i2ib則形 成有多數成陣列方式佈設且與該銲墊121c電性連接之銲 墊121d，使該銲墊12〇c與下層電路板12〇之對應第三銲 墊12〇C間~結有多數之銲錫（solder Paste)或銲塊（Solder Bum|>)16，俾令該上層電路板121藉該銲錫或銲塊而電 f生連接至下層電路板12〇。該銲錫或銲塊丨6之銲接得使用 19305 16 200818453 習知之如表面黏著技術（SMT)等j式為 <，且該下層電路 板120及上層電路板121俱為習見之電路板，其製造方法 ^使用材料亦與習知者無異，故在此不另為文贅述。同時， 夕數之第一金線17係分別端接至該下層電路板】之第四 銲墊120d及基板10之頂面1〇4上之第二銲墊i〇4b，以使 該電性連接結構12藉該多數第二金線17而電性連接至基 板 10。 土 _一、該封裝膠體13乃以習見之環氧樹脂⑺㈧巧以以㈨等 回刀子材料形成，其形成亦係以一般之模具（Mold)及模壓 製程（Molding Process)為之。該封裝膠體〗3形成於基板工〇 上後，係將該上層電路板121之上表面121b外露出且使該 f層電路板121之上表面121b與封裝膠體13之頂面13〇 背平，以令本發明之半導體封裝件i能藉該上表面12比 上之銲墊121d與另一半導體封裝（未圖示）電性連接，而使 另一半導體封裝件疊接至本發明之半導體封裝件〗之上。 _由於該外露之上層電路板121的上表面121b乃與封裝膠體 13之頂面13〇齊平，故在模壓製程中使用一般之模具（即 模具之模穴（Mold Cavity)為平頂（Fiat Top)者）即可，而毋須 如前述之第6,861，288號美國專利所揭示之裝置須使用特、 殊模具（Insert Mold)來形成封裝膠體，因此，本發明之^ 裝膠體13之形成無增加成本之虞。 ' 並且，該用以與如另一半導體封裝件之外界裝置電性 連接之電性連接結構12乃藉第二金線17電性連接至基板 10，且之上層電路板121與下層電路板120之銲接乃在哕 19305 17 200818453 電性連接結構12藉黏著劑黏結至基牙反w 故無前述第6,828,665號美國專利 則 凡成， 猎銲球電性連接至基板上時，、板 質受影響及W與基板受㈣;㈣造成銲線品 並係直㈣m 木專問續。該電性連接結構12 係直接h於基板1G上而未與晶片 會有前述之第Μ61，288號美國專利所揭示之^而不 金屬承载件支撐與疊接用之另:湏使用 路板，㈣絲結介面衫W產生性連接之電 •成本增加以㈣純脫層（D—)、 再而，該晶片11及第一厶始7 c 1 結構U中所形成之收納=乃收納於該電性連接 予以包覆，故不合有/^ 2毋須先以封裝膠體 -々丁成丄有述之第5,222,014號美國專利所揭 不之下層半導體封裝件會受限下層半導專利所揭 膠體尺寸而影響到基板 之封裝 連接用之銲墊數目的問題導體封裝件電性 I半導體封壯杜！ Μ ’’，因本發明第-實施例之 奋/ 、衣牛之與另一半導體封裝疊接用之銲墊數目不 影響’所以，該晶片11之型式與尺二 性-内用上幸謂述習知技藝為大的彈性、變化 …且W生。此外，本發明之 體13之上層電路板121的上表面= 其上半導體封裝件雷 ，、为宜接 美國專利所Mu s 而非如前述第5,222,㈣號 下層=二:半導體封裝件乃藉銲球電性連接至 _、衣，使銲球之高度會限制下層半導體封裝 19305 18 200818453 件之封裝膠翻高度，而訂層半導體封料之高 限’即會限制住下層半導體封裝件所能選用之晶片的 與尺寸，亚亦會影響至銲線之品f。亦即，本發明所提 之結構確能解決該第5,222,〇14號美國專利所存在之題 μ本發明第-實施例之半導體封裝们之製法，則配合 第2Α至2F圖詳述如后。 … 如第2A圖所示，分別製備下層電路板12〇及上層帝 路板12!，使該下層電路板m之上表面·上形成= 列相對應之多數第二銲塾12()。及第四銲墊1·，且該第 三銲墊120c係藉電路i施電性連接至對應之第四鲜塾 12〇d’而該上層電路板121則在其下表面Η。之預設位置 上形成有多數之銲墊121c，及在其上表面1211)上形成有 多數成陣列方式佈設之銲墊121d，並使該上表面^化上 之銲墊121d藉電路121f電性連接至位於下表面i2u上之 銲墊121c。該下層電路板12〇之尺寸宜小於上層電路板 _ 121 ’且该上層電路板121及下層電路板12〇得個別形成， 或以陣列方式一體形成為一塊電路板片，端視尺寸之需求 而疋，並無特定限制。惟在此說明書中為求簡易明瞭及圖 式簡潔，故未顯示電路板片之型態。 如第2B圖所示，以表面黏著技術將多數銲錫16銲接 於複數片上層電路板12ι之下表面121a上的銲墊121c及 下層電路板120之上表面HOb上的第三銲墊i2〇c間，並 予以回銲（Refl〇w)處理，以使該上層電路板121藉銲錫16 私性連接至下層電路板120，而形成一電性連接結構。 19 19305 200818453 該下層電路板no藉銲錫16連接至該上層電路板ΐ2ι方 式，係使下屬電路板！20之上表面㈣形成有第三焊塾 120C之部分為該上層電路板121所覆蓋，而形成有第四鲜 墊120d之料則外露出該上層電路板121，亦即該下層電 路板120之上表面n〇b形成有第四鲜塾n〇d的部分乃自 該上層電路才反121之側邊121e向外延伸出，而使兩相對之 下層電路板120間形成一預設之間隙，以於該電性連接結 構12中形成出一收納空間122。上述之複數片下層電路^ 120之*數得為二或四，當其為二片下層電路板⑶ /、上層％路板121之結合時，係示如第圖；而當i為 四片下層電路才反12〇與上層電路板之結合時，則示如第扣 圖。=即，該下層電路板12〇帛以與上層電路板ΐ2ι結合 j數！係視需要而定，但須知該下層電路板i2G之使用數 f亦不限於本實施例所揭轉，其它能產生相似效果之數 f變化亦適用。 •…如弟2E圖所示，將該電性連接結構u以習用之黏著 片J站…至基板10之頂面104上。該基板10之頂面1〇4 係預黏叹有一晶片u，且形成有位於該晶片“之黏設 區域外之多數第—銲塾1Q4a及第二銲墊⑽b ;而該晶片 ^上亦形成有多數電性連接墊11〇，俾藉多數分別端接至 該，眭連接墊110與基板10頂面104上之第一銲墊104a ί線15，以電性連接該晶片11與基板10。並且， 數第—金線17分別端接至下層電路板120上表面 12〇b上之第四銲墊12〇d與基板1〇頂面1〇4上之第二銲墊 20 19305 200818453 mb ’使該電性連接結構i2電性連接至該基板⑺。由於 X電[生連接結構12具有從納空間m，故能在與基板1〇 f結後，使該晶片11與第一金線15均收納於該收納空間 i中且忒收納空間122之大小係能充分至該第一金線 • 一 =曰jl觸至β亥電性連接結構12。因而，該晶片η及第 - $ 15由於毋須先以封裝膠體包覆，該電性連接結構 曰，基板ίο之黏結即不會受到封裝㈣之影響，而提供 I丄1之型式與尺寸在選用上的更大彈性，且因不用刻意 低弟一金線15之線弧高度（Height of Wireloop)，故復能 維持第一金線15之銲接品質。 此外’ δ亥電性連接結構12之下層電路板的下表 面120a與基板1〇黏結之位置係在該基板w之第一焊墊 丁4恳&與第二銲塾_間。由於該電性連接結構！2乃藉其 :層電路板m以黏接方式黏結於基板1()上，並藉第二金 1 17 $性連接至基板1()，因而，並無使用銲球作為支樓 兵另一半導體封裝件電性連接之堆疊用電路板的需要，故 “度限制住晶片之型式及尺寸與金線之線弧 7度的問通，且亦不會因須對銲球進行回銲處理而造成晶 片與基板受污染的缺點。 再參照第2F圖，將該第2Ε圖所示之結構置於模且a 之下模18a與上才莫18b間以進行㈣作業，俾於該基板μ 之頂面104上形成一包覆該電性連接結構ΐ2、晶片 及第二金線17之封襄膠體13，但使該電性連接 4 之上層電路板121的上表面咖外露出該封裝谬 19305 21 200818453 體13,並令該上表面121b與封裝膠體13之頂面130斑平， 121b上的_ 121d_生連接堆疊二上 另—轉體封裝件（未圖㈤。由於該上表面 士 /、封衣膠體U之頂面130為其平面，故用於模壓作 業之模^ 18於模穴中毋須採用突出設計（insert Design)， 而為一般之模具，故無增加成本之虞。 .取後’將模具18脫模後，進行植球作業（Solder Ball WO，將多數銲球14植接至該基板10之底面1〇2 上成陣列方式佈設之銲球墊1〇2a， 發明 例之半導體封裝件】，如第1B圖所示。纟月弟貝施 弟二實施例 如第3圖所示，所顯不者為本發明第二實施例之 體封裝件3之剖簡。該半導體封裝件3與前述之第一# 體封裝件1的結構大致相同，其不同處在於二 半二體，牛3，如圖所示，係將晶片31以覆晶方式(叫 ip)电性連接至基板30之頂面3〇4上；該晶片31乃多數 銲塊（Solder Bumps)35銲接於基板3〇頂面綱上所 ^對應之第—銲塾鳥，心銲塊35乃銲設於晶片= =板30間’故無以金線電性連接晶片至基板時，金線係 曰曰片向外幸田射伸出而會佔才康基板上之使用面積的情形， 故此覆晶形式之結構能進一步縮小整體封裝件之尺寸或增 加基板上供佈線（Lay0ut)或利用之面積。 曰
羞三f施I 如第4圖所示’所顯示者為本發明第三實施例之半導 22 19305 200818453 4㈣簡。料導體封料4之結構大致同於 刖处之弟—實施例之半導體封裝件1，i 、 導體封裴件4之電性連 ，、冋處在於該半 及42b，各一^ 構乃分為兩對稱之部分仏 所構成η由上層電路板421及下層電路板· 42ld之數旦特徵在上層電路板421戶斤提供之銲墊 付合需求下’可減少上層電路板42ι之用 科而仵降低整體之封裝成本。 盖四复 之示料本發明第四實施例之半導體封裝件 同於㈣貫施例之半導體封裝件5之結構係大致 該半二:：Γ例之半導體封裝件1 ’其不同處在於 封穿勝體之上層電路板521的上表面521b係低於 1 衣㈣53之頂® 530 ’亦即’兩者非共平面。該上声電 俜因反Γ1之上表面521b之低於封裝谬體53之頂面530， 覆製？Λ上表面521b於模壓作業完 ' 多此衣耘將詳述於后），以避免上表面521b上之 銲墊5叫於漏作業中遭受污染而影響其與另一堆疊其 ^之+導體封裝㈣雜連接或職續清 本的增加。 午双砥 第6A至6D圖所示者為本發明第四 封裝件5的製造流程，”，同…二?之“肢 /、丫 问於刖述弟一貫施例之丰導 體封们之製法之部分將予略除，以避免贅述。 、 如第6A圖所不，製備一由下層電路板520斑上層電 路板521構成之電性連接結構52，復在該上層電路板%21 19305 23 200818453 之上表面521b上貼覆一層膠片（Tape)59。 如第6B圖所示，將該電性連接結構52黏設於基板5〇 之頂面504上，使黏置於該基板5〇上之晶片51能收納於 5亥電性連接結構52之收納空間522中。 ^再參照第6C圖，進行模壓作業（未顯示出該模具，以 簡化說明與圖式）以在該基板5〇上形成—包覆該晶片”及 電性連接結構52之封裝膠體53,但使該膠片”外露出該 封裝膠體53之頂面530。 最後，如第6D圖所示，將該膠片59自該電性連接结 構52之上層電路板521的上表面521b上撕除，以使上表σ 面上之多數銲墊521d外露於大氣中，俾供堆疊於^ 上層電路板521之上表面上的另—半導體封裝件藉之與所 1成之半導體封裝件5電性連接。由於該膠片”係於封裝 膠體53形成後方予撕除，故膠片59撕除後而外露出朗 裝膠體53的上表面521b會低於該封裝膠體53的頂面：。 上述實施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明。任何熟習此項技藝之人士均可^不^ =本發明之㈣及範訂，對上述#_進行㈣與= 變。因此，本發明之權利保護範圍，應如 ^ 範圍所列。 T叫專利 【圖式簡單說明】 第1A圖係顯示本發明第一實施例之半導體 ΊΓ i目国· 4衣1干之 第 1B圖係顯示相對第1A圖沿 1B-1B線剖開之剖視 19305 24 200818453 圖； 第2 A至2 F圖係顯示本發明第一實施例之半 件之製法示意圖； 、封衣 視圖， 第3圖係顯示本發明第二實施例之半導體封裳件之剖 視圖； 第4圖係顯示本發明第三實施例《半導體封裝件 之剖 _ 第5圖係顯示本發明第四實施例之半導體封妒 立 視圖； 弟6A至6D圖係顯示本發明第四實施例之 件之製造示意圖； 干*體封裝 第7圖係顯示習知堆疊式多晶片模組剖視圖； 第8圖係顯示第6,828,665號美國專利案所揭示 導體封裝件剖視圖； 第9圖係顯示第6,861，288號美國專利案所揭厂、“ 鲁導體封裝件剖視圖；以及 、。不之半 第圖係顯示第6,861，288號美國專利案中形 膠體之剖視圖。 --成封裝 【主要元件符號說明】 1 半導體封裝件 10 基板 11 曰 LI 曰曰片 12 電性連接結構 13 封裝膠體 19305 25 200818453 102 底面 102a 銲球墊 104 頂面 104a 第一銲墊 104b 第二銲墊 110 電性連接墊 120 下層電路板 120a 下表面 120b 上表面 120c 第三銲墊 120d 第四銲墊 120e 電路 121 上層電路板 121a 下表面 121b 上表面 121c 焊塾 121d 銲墊 121e 侧邊 121f 電路 122 收納空間 130 頂面 14 鲜球 15 弟一金線 16 銲錫/銲塊 200818453 17 第二金線 18 模具 18a 下模 18b 上模 3 半導體封裝件 30 基板 304 頂面 304a 第一銲墊 ®31晶片 35 銲塊 4 半導體封裝件 42 電性連接結構 42a，42b電性連接結對稱之部分 420 下層電路板 421 上層電路板 421d 鲜塾 5 半導體封裝件 50 基板 504 頂面 51 晶片 52 電性連接結構 520 下層電路板 521 上層電路板 521b 上表面 27 19305 200818453 521d 銲墊 522 收納空間 53 封裝膠體 530 頂面 59 膠片

Claims (1)

  1. 200818453 十、申請專利範圍： 1· 一種可供堆疊半導體裝置之半導體封裝件，係包括·· 一基板，具有多數第一銲墊及第二銲墊； 至少一接置於該基板上之晶片； 多數第一電性連接元件，用以電性連接該晶片至 基板之第一焊塾； 接置於該基板上之電性連接結構，係由上層電路 板與下層電路板所構成，該上層電路板並與下層電路 板形成有電性連接關係，且形成有一收納空間Z將該 至少一晶片及多數之第一電性連接元件收納其中，並 使該基板之多數第-銲墊位於基板為該電性連接結構 所覆蓋之區域内，而該多數第二銲墊位於基板為該電 性連接結構所覆蓋之區域外； 多數第二電性連接元件，用以電性連接於該電性 '連接結構之下層電路板及基板上m，而將該 電性連接結構電性連接至基板；以及 形成於該基板上之封裝膠體，用以包覆該至少一 晶Γ多數第一電性連接元件、電性連接結構與多數 ^弟-電性連接元件，但使該電性連接結構之上層電 2. 路板的上表面外露出該封裝膠體。 如申請專利範圍第1項之半導體封裝件，置中，兮第 —及第二電性連接元件係為銲線。 〃 ^弟 如申請專利範圍第2項之半導體 線係為金線。 卞Τ，5亥鈐 19305 29 3. 200818453 4. ”請專利範圍第！項之半導體封裝件，其中 =電性連接元件係為銲塊而該第二電性連接元件為焊 5. ^申請專利範圍第1項之半導體封裝件，其中1上 θ電路板係藉由該下層電路板而支撐於基板上，使該 ϋ構晶片及第—電性連接元件不致碰觸至該電性連 6. $申凊專利範圍第丨項之半導體封I件，其中， 括2 =構係由二對稱之部分所構成，每一部分係包 =電路板及結合至該上層電路板下表面上之下層 ，申請專利範圍第丨項之半導體封裝件，其中， 性連接結構係由一片 〇Λ 構成者。 乃上層窀路板及二片下層電路板所 8· 如申請專利範圍第1項之半導 性連接結構係由一片上4m電 構成者。 々上層電路板及四片下層電路板所 9· 利範圍第1項之半導體封裝件，其中，該電 =構係藉其下層電路板之下表面以黏著劑黏接 王孩基板上。 10.:nt利範圍第1項之半導體叫其中，該電 結構係糾塊或銲錫電性連接該上層電路板與 下層電路板。 u.如申請專利範圍第1項之半導體封裝件，其中，該下 19305 30 200818453 層電路板之上表面係部分為該上層電路板 其餘部分則外露出該上層電路板。 是義，而 12. 如申請專利範圍第u項之半導體封裝件，其 層電路板之上表面為上層電路板所覆蓋之部分’：下 多數第三鮮墊以與銲塊或銲錫銲接，而該下層:有 之上表面未為上層電路板所覆蓋之部分則形‘：】 弟四銲墊，俾與該第二電性連接元件銲接。 13. 如申請專利範圍第i項之半導體封裝件，其中 層電路板之上表面上形成有多數呈陣列方式佈設:銲 Ϊ性=堆疊於上表面上之另一半導體裳置與該銲塾 14.如申請專利範圍第丨項之半導體封裝件，其中，該上 層電路板之上表面係與封裝膠體之頂面齊平。 15·如申請專利範圍第丨項之半導體封裝件，其中，該上 層電路板之上表面係低於封裝膠體之頂面。 Φ 16. ^中請專利範圍第1項之半導體封裝件叫复包括多數 銲狀銲植於該基板之底面上，俾供該半導體封裝件藉 該多數銲球與外界裝置電性連接。 17. —種可堆疊半導體裝置之半導體封裝件的製法，係包 括下列步驟： 製備一電性連接結構，該電性連接結構具有上層 電路板及與該上層電路板電性連接之下層電路板，且 位於該上層電路板之下方形成有一收納空間； 黏接該電性連接結構至一其上黏設有一至少一晶 31 19305 200818453 片之基板，該基板上形成有多數第一銲墊及多數第二 銲墊，使該多數第-銲塾位於基板上為該電性連接: 構所覆蓋之區域内而該多數第二銲墊則位於基板上為 該電性連接結構所覆蓋之區域外，俾供該晶片藉多數 第一電性連接元件電性連接至基板上之第一銲墊； 藉多數第二電性連接元件電性連接該電性連接結 構至該基板上之多數第二銲墊；以及 於該基板上形成用以包覆該至少一晶片、電性連 攀接結構與多數之第一及第二電性連接元件之封裝膠 體，但使該電性連接結構之上層電路板的上表面外露 出該封裝膠體。 18·如申請專利範圍第17項之製法，其中，該電性連接結 構係藉下層電路板之下表面黏接至該基板上。 19·如申印專利範圍第17項之製法，其中，該電性連接結 構之上層電路板係藉多數銲塊或銲錫電性連接該下層 _ 電路板。 S 20.如:請專利範圍第17項之製法，其中，該上層電路板 係藉由下層電路板之支撐而懸空於該至少一晶片及第 :電性連接元件上，使該至少一晶片及第一電性連接 元件不致碰觸至該電性連接結構。 申明專利範圍第17項之製法，其中，該電性連接結 構復包括一貼覆於該上層電路板之上表面上之貼片。 22.如申請專利範圍第21項之製法，於該封裝膠體形成 後，復包括一將該貼片自該上層電路板之上表面上撕 19305 32 200818453 驟’以使该上層電路板之上表面外露出該封裳 該上層電路板 該上層電路板 該第一及第二 該銲線為金線 3·如申凊專利範圍第22項之製法，其中 之上表面係低於該封裝膠體之頂面。 4·如申请專利範圍第17項之製法，其中 之上表面係與該封裝膠體之頂面齊平。 25.如申請專利範圍第17項之製法，其t 電性連接元件為銲線。 請專利範圍第25項之製法，其中，5f、線。 •申请專利範圍f 17項之製法，其中，㈣一電性連 接π件係銲塊而該第二電性連接元件為銲線。 8·:申請專利範圍第17項之製法，其中，該電性連接結 ♦件由一對稱之部分所構成，每一該部分則具有上層 包路板及與該上層電路板電性連接之下層電路板。 19305 33
TW095137477A 2006-10-12 2006-10-12 Semiconductor package on which a semiconductor device is stacked and production method thereof TWI312569B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW095137477A TWI312569B (en) 2006-10-12 2006-10-12 Semiconductor package on which a semiconductor device is stacked and production method thereof
US11/974,441 US7679178B2 (en) 2006-10-12 2007-10-12 Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095137477A TWI312569B (en) 2006-10-12 2006-10-12 Semiconductor package on which a semiconductor device is stacked and production method thereof

Publications (2)

Publication Number Publication Date
TW200818453A true TW200818453A (en) 2008-04-16
TWI312569B TWI312569B (en) 2009-07-21

Family

ID=39302387

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095137477A TWI312569B (en) 2006-10-12 2006-10-12 Semiconductor package on which a semiconductor device is stacked and production method thereof

Country Status (2)

Country Link
US (1) US7679178B2 (zh)
TW (1) TWI312569B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9167686B2 (en) 2012-10-17 2015-10-20 Universal Scientific Industrial (Shanghai) Co., Ltd. 3D stacked package structure and method of manufacturing the same

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI292617B (en) * 2006-02-03 2008-01-11 Siliconware Precision Industries Co Ltd Stacked semiconductor structure and fabrication method thereof
US20090152740A1 (en) * 2007-12-17 2009-06-18 Soo-San Park Integrated circuit package system with flip chip
JP5078808B2 (ja) * 2008-09-03 2012-11-21 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US9559046B2 (en) * 2008-09-12 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-in package-on-package structure using through silicon vias
TWI406373B (zh) * 2009-01-14 2013-08-21 Advanced Semiconductor Eng 可選擇線路之基板及覆晶接合結構
US7847382B2 (en) * 2009-03-26 2010-12-07 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US20110068478A1 (en) * 2009-03-26 2011-03-24 Reza Argenty Pagaila Integrated circuit packaging system with package stacking and method of manufacture thereof
US8844123B2 (en) * 2009-12-03 2014-09-30 Chin-Chi Yang Method of manufacturing a hollow surface mount type electronic component
US8653654B2 (en) * 2009-12-16 2014-02-18 Stats Chippac Ltd. Integrated circuit packaging system with a stackable package and method of manufacture thereof
US8530277B2 (en) * 2011-06-16 2013-09-10 Stats Chippac Ltd. Integrated circuit packaging system with package on package support and method of manufacture thereof
TWI491017B (zh) * 2013-04-25 2015-07-01 矽品精密工業股份有限公司 半導體封裝件及其製法
US10797035B1 (en) * 2019-04-02 2020-10-06 Sandisk Technologies Llc Bonded assembly containing side bonding structures and methods of manufacturing the same
TWI711131B (zh) * 2019-12-31 2020-11-21 力成科技股份有限公司 晶片封裝結構
KR20220007192A (ko) * 2020-07-10 2022-01-18 삼성전자주식회사 언더필이 구비된 반도체 패키지 및 이의 제조 방법
CN114942493B (zh) * 2022-05-05 2024-01-30 武汉光迅科技股份有限公司 一种芯片组件、光器件及组装方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US7122904B2 (en) * 2002-04-25 2006-10-17 Macronix International Co., Ltd. Semiconductor packaging device and manufacture thereof
US7049691B2 (en) * 2002-10-08 2006-05-23 Chippac, Inc. Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package
TW567601B (en) 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
US6861288B2 (en) * 2003-01-23 2005-03-01 St Assembly Test Services, Ltd. Stacked semiconductor packages and method for the fabrication thereof
US6815254B2 (en) * 2003-03-10 2004-11-09 Freescale Semiconductor, Inc. Semiconductor package with multiple sides having package contacts
US7279783B1 (en) * 2003-10-29 2007-10-09 Silicon Pipe, Inc. Partitioned integrated circuit package with central clock driver
DE10360708B4 (de) * 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
US7445962B2 (en) * 2005-02-10 2008-11-04 Stats Chippac Ltd. Stacked integrated circuits package system with dense routability and high thermal conductivity
US7354800B2 (en) * 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
SG130055A1 (en) * 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US7312519B2 (en) * 2006-01-12 2007-12-25 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7435619B2 (en) * 2006-02-14 2008-10-14 Stats Chippac Ltd. Method of fabricating a 3-D package stacking system
US7298037B2 (en) * 2006-02-17 2007-11-20 Stats Chippac Ltd. Stacked integrated circuit package-in-package system with recessed spacer
US7368319B2 (en) * 2006-03-17 2008-05-06 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7390700B2 (en) * 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
TWI309079B (en) * 2006-04-21 2009-04-21 Advanced Semiconductor Eng Stackable semiconductor package
TWI298198B (en) * 2006-05-30 2008-06-21 Advanced Semiconductor Eng Stackable semiconductor package
US20080042265A1 (en) * 2006-08-15 2008-02-21 Merilo Leo A Chip scale module package in bga semiconductor package
TWI317993B (en) * 2006-08-18 2009-12-01 Advanced Semiconductor Eng Stackable semiconductor package
US7537962B2 (en) * 2006-12-22 2009-05-26 Stats Chippac Ltd. Method of fabricating a shielded stacked integrated circuit package system
US7566966B2 (en) * 2007-09-05 2009-07-28 Stats Chippac Ltd. Integrated circuit package-on-package system with anti-mold flash feature

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9167686B2 (en) 2012-10-17 2015-10-20 Universal Scientific Industrial (Shanghai) Co., Ltd. 3D stacked package structure and method of manufacturing the same

Also Published As

Publication number Publication date
TWI312569B (en) 2009-07-21
US20080088011A1 (en) 2008-04-17
US7679178B2 (en) 2010-03-16

Similar Documents

Publication Publication Date Title
TW200818453A (en) Semiconductor package on which a semiconductor device is stacked and production method thereof
US6462412B2 (en) Foldable, flexible laminate type semiconductor apparatus with reinforcing and heat-radiating plates
TW567601B (en) Module device of stacked semiconductor package and method for fabricating the same
TW563233B (en) Process and structure for semiconductor package
TW533507B (en) An electronic device an electronic device sealing method and an electronic device connecting method
US7719104B2 (en) Circuit board structure with embedded semiconductor chip and method for fabricating the same
TWI411073B (zh) 嵌埋被動元件之封裝基板及其製法
TWI353046B (en) Land grid array semiconductor device packages, ass
TWI496258B (zh) 封裝基板之製法
TW579560B (en) Semiconductor device and its manufacturing method
JP2001077294A (ja) 半導体装置
US8098496B2 (en) Wiring board for semiconductor device
TWI419278B (zh) 封裝基板及其製法
TW200926316A (en) Semiconductor package and method thereof
JP4035949B2 (ja) 配線基板及びそれを用いた半導体装置、ならびにその製造方法
TWI357653B (zh)
US8410598B2 (en) Semiconductor package and method of manufacturing the same
JP4038021B2 (ja) 半導体装置の製造方法
TW200845354A (en) Multi-chip semiconductor device having leads and method for fabricating the same
TW200828458A (en) Semiconductor package and fabrication method thereof and stack structure
JP4174008B2 (ja) 半導体装置
JPH11340352A (ja) 実装構造体
TWI720728B (zh) 薄膜覆晶封裝結構和其製作方法
TW201446086A (zh) 封裝結構及其製作方法
TWI819440B (zh) 電子封裝件及其製法