TW200816323A - High-voltage semiconductor device structure - Google Patents

High-voltage semiconductor device structure Download PDF

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Publication number
TW200816323A
TW200816323A TW095136376A TW95136376A TW200816323A TW 200816323 A TW200816323 A TW 200816323A TW 095136376 A TW095136376 A TW 095136376A TW 95136376 A TW95136376 A TW 95136376A TW 200816323 A TW200816323 A TW 200816323A
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Taiwan
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region
substrate
doped
type
adjacent
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TW095136376A
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English (en)
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TWI309068B (zh
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Chi-Hsiang Lee
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Leadtrend Tech Corp
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Priority to TW095136376A priority Critical patent/TW200816323A/zh
Priority to US11/639,558 priority patent/US7495286B2/en
Publication of TW200816323A publication Critical patent/TW200816323A/zh
Application granted granted Critical
Publication of TWI309068B publication Critical patent/TWI309068B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Description

200816323 九、發明說明: 【發明所屬之技術領域】 本發明係關於-種高料導體元件結構,特別係有關於 橫向擴散金魏化辨導體(LDMQS)之元件結構。 種 【先前技術】 橫向紐金魏化解雜LDMQS)元件f翻於 作環境下,例如高功率與高頻段的功率放大器,或是基 功率元件。L_的特徵是編崎雜,可抗 ^百伏特,主要原因是_S在汲極延伸結構中具有低 的4延伸區,可用以緩和汲極端與源極端之間的崩潰作用1 而⑽愤有較高的崩潰電壓(breakd〇wn讀勢為使_仍 獲仔更南的崩潰電M,因此必須針對元件的結構進行改良。 ,參閱「第U圖」及「第1Β圖」,分別為先前技術橫向擴 政孟屬乳化物半導體(LDM〇s)元件結構之配置圖及剖面圖。如「第 1A圖」所不’傳統的橫向擴散金屬氧化物半導體⑴結構包含— 原極、。構η、—汲極結構12、—祕延伸結構η及—閘極 14。 源極結構11具有由其下側部位朝中央部位延伸的突出部 =’,,而如部η,則被源極結構η之上側、左侧及右側部位所圍 &且刀顺上側、左侧及右側部位分隔—般距離。汲極結構 12配置於上述預設距離所形成之區域,形成圍繞在突出部11,左 200816323 側、上側及右側之馬蹄形區域,且其外圍則被突出部u,以外之 極結構11賴繞。汲極延伸結構η圍繞於汲極結構^外圍,爽 與源極結構η她-蚊轉。同時,祕轉u與祕延= 結構u間具有-閘極結構M,賴極結構M下方即為場效通道 區。在此高壓元件低導通電阻(Rdson)的要求下,此突出部n,的佈 局特徵不容易避免。 如「第1B圖」所示,係為沿「第1A圖」Η線之剖面圖。源 極結構U包含形成於基板如ρ型基板15表面上之源極電極Μ ; 形成於Ρ型基板15中並位於源極電極16底下之ρ型井區17,其 中按π隹有Ρ型導電離子,形成於ρ型井區17中之η+型摻雜區Μ, 係為具有高摻雜濃度Ν型導電離子之一 _ ;形成於ρ型井區17 中並與η型摻雜區18相鄰之ρ+型摻雜區19,係為具有高摻雜濃 度Ρ型導電離子之一區域。其中,奸型摻雜區18與垆型摻雜區 19皆與源極電極16相連接。 汲極結構12包含形成於ρ型基板15表面上之汲極電極20 ; 位於没極電極20下方且形成於Ρ型基板15中之η型井區21 ;形 成於η型井區中之η+型摻雜區22,係為具有高摻雜濃度Ν型導電 離子之一區域,並與汲極電極2〇相連接。 汲極延伸結構13中包含具有低摻雜濃度ν塑導電離子之η 型漂移延伸區23,及形成於η型漂移延伸區23中之Ρ型摻雜區 24。其中,汲極延伸結構13之η型漂移延伸區23與源極結構u 200816323 之n+型摻雜區18間具有-預設距離,用以形成場效通道區27。 閑極結構14 &含形成於基板表面上之閘極絕緣^ 25與形成 於閘極絕緣層25上之_電極26。閘極結構14配設於n奶票移 延伸區23與p型井區17之上方,透過控制閘極電壓的大小以開 關場效通道區27。 上述之LDMOS結構巾,祕突出部n,具有—個小曲率半徑 φ 的111 ’易產生包荷積聚的現象使得通過此部位的電場強度較 為強烈’造錢效通道關電場分佈不均,#_於高壓條件下 時,將因電場局部積聚的效應而形成崩潰作用,降低ldm〇s之 崩潰電壓。如欲不使此突出部U,影響其元件崩潰電壓,則必須將 此曲率半徑變大,然而此舉卻使整體树面積變大,相對的使得 導通電阻(Rdson)變高,並降低晶片上元件的積集度。 【發明内容】 • 自於先前技射具有小鱗半㈣電鱗端㈣成電荷積 承,造成場效通道’場強度分布不均,_導致崩潰電壓降低 的情形產生。因此’本發明提供一種具有高崩潰電壓之高壓半導 體結構’孩具有低導通雜並可同時提高⑼上半導體元件的 積集度,以滿足微型化電子元件之要求。 本發明之高壓轉赌構包含—基板、-祕結構、-汲極 延伸結構、一源極結構及一閘極結構。 及極結構職於基板±且具有彼此絕緣性地緊鄰交錯相嵌之 200816323
兩開口形結構,此兩個開口形結構於相嵌處間定義出三種不同的 區域,以配設不同功能之結構,其分別有兩第一區域、兩第二區 域及-第三區域,其中第-區域與開口形結構相鄰,第二區域則 緊鄰第-區域,而第三區域則介於上述兩第二區域之間。此外, 各開口形結構皆包含-第-井區、—第—摻雜區及—汲極電極。 汲極電極形成於基板表面上;第—摻雜_形成於汲極電極下方 的基板中,係為自基板表面向下延伸之—摻雜有導電離子之區 域,並與汲極電姉連形成於基板巾並醜第一 接雜區’且帛-井區舶雜導f軒之區域卿成。 汲極延伸結構形成於基板中且位於第一區域,其包含一具有 導電離子之漂移延輕,轉移延伸區係與第—井區相鄰/、 源極結構形成於基板中且位於第三區域。雜結構包含一第 上 至v L顧及—源極電極。源極電極形成於基板 ,並與形成於其下方基板中之第二摻祕 則圍繞於第二摻雜區之外圍。第 ^一井£ 、曾 开&及弟一抬雜區中皆摻雜有 導電離子。 效、形成於基板上且位於第二_,且其下方形成一場 極社構:人過閑極結構可用以控制場效通道區之開關狀態。閘 ==_陶及一閘極電極,其中,閘極絕緣層形成 層上。Κ上方之基板表面上,而難電極職蓋於閘極絕緣 200816323 猎由本㈣之减轉體結構,可避免雜結構歧極结 間產生尖端電場積聚的現象,有效提高抖體元件之崩潰電壓, 並透過具有彼此相嵌開口形結構之祕結構配置,以降低導通恭 阻’尚且充分展現空間细效率,提昇“上半導體元件之積^ 度,以付合微型化電子元件之要求。 、 【實施方式】 。月參閱# 2A圖」’係為本發明之高壓半導體元件結構之配 置圖。高壓半導體30元件結構包含一及極結構%、—汲極延伸結 構33、一源極結構31及一閘極結構34。 汲極結構32係練互分離之開口形結構(如馬蹄戦口形結 構但非用以限定本發明之應用範旬彼此絕緣性地緊鄰交錯嵌合 而形成配置,且關口形結構於緊鄰交錯後合處之間定義出三種 不同之區域:兩第-區域、兩第二區域及一第三區域,其相關排 ^位置’自開口形結構向外延伸依序為第—區域,與第一區域相 ,的第二區域’緊鄰第二區域之第三區域,而第三區域係位於兩 第二區域之間。 卜請參閱「第2Β圖」,係為沿「第2Α圖」腿線之剖面圖。如 ^第2B圖」所示,各開口形結構包含一沒極電極%、一 n+型摻 雜區37及一 n型井區38。汲極電極36形成於一基板上如P型基 板35’η型摻雜區37係由汲極電極允與?型基板%接觸表面向 下延伸-預舰離卿成之區域,射摻财高濃度的Ν型導電 200816323 =子;η型井區38則是形成於p型基板%中朗繞在γ型推雜 區37之外圍。此外,雖然兩開口形結構係為相互分離之獨立結構, 但其汲極電極36 f柯躺外抑線㈣e bQnding)設計喊此相 連。 没極延伸結構33位於第-區域巾,其包含—n型漂移延伸區 39及一 P型摻雜區40。η型漂移延伸區39係與n型井區%相鄰 φ 之一區域,其中摻雜有低濃度的N型導電離子;p型摻雜區4〇則 形成於n型漂移延伸區39所圍繞之區域中且係自p型基板35表 面向下延伸之一區域,此外,Ρ型摻雜區40中摻雜有Ρ型導電離 子。 ' 源極結構31形成於ρ型基板35中且位於第三區域。此外, 源極結構31包含一源極電極42、一 ρ型井區43、兩η+型摻雜區 44及一 Ρ+型摻雜區45。源極電極42形成於Ρ型基板35上;ρ型 馨 井區43形成於源極電極42下方之Ρ型基板35中,其摻雜有ρ型 導電離子;兩η+型摻雜區44及ρ+型摻雜區45形成於Ρ型基板35 中並被ρ型井區43所圍繞,其中Ρ+型摻雜區45位於兩η+型摻雜 區44之間’且η+型摻雜區44與ρ+型掺雜區45皆與源極電極42 相連接。此外,η+型摻雜區44中摻雜有高濃度的Ν型導電離子, 而Ρ+型摻雜區45中則摻雜高濃度的Ρ型導電離子。 閘極結構34形成於Ρ型基板35表面上且位於前述之第二區 域,此外,閘極結構34下方,即η型漂移延伸區39與n+型摻雜 200816323 區44之間’碱—場效娜41 1極結構34包含-閘極電極 47及- _絕緣層46。_絕緣層46形成於場效通道㈣上方 之P型基板35表面上,而閘極電極π則覆蓋於閑極絕緣層杯上。 透過閘極結構34可進行場效通道區41之開關控制。 此外,麵構32、祕結構31及_輯%彼此間形成 ^緣層48如氧化終用以確保電性絕緣效果,以免各結構間 產生短路現象。 ^「第3目」柄,她嶋概件之延伸結構 不思圖.結構52係由s形之開口形結構形成彼此相嵌之配置 型悲,且此歧極結構52巾尚包含圍繞在祕結構Μ周圍之沒 極延伸結構,㈣聽構5_成於減處的輯 S形配置型態。閘極結構(圄去_Λ Bt 兄 構(圖未不)則配置於汲極結構52與源極 培構51間。 如「第4圖」.所示,係為本發明高壓半導體元件之另一延伸 ^丁』疏、’。構62係由兩扁梳狀之開口形結構彼此相歲而 ^且纖構62尚包含圍繞在汲極結構62周圍之汲極延伸 遠* ς ^雜61 1 杨成於相嵌處的區域間,呈現首尾相接之 ^形配置動、。閘極結構(圖未示)則配置於沒極結構以與 源極結構61間。 ㈣tr緒半導體結觀置,在_口_嵌之汲極 有源極結構’使得源極電極不再具有小曲率半徑之邊 200816323 緣’進而排除產生先前技術中由於雜突出部之尖端電場局部積 聚的現象,因此,源、極結構與汲極延伸賴所形成的場效通道區 具有均勻的電場分佈,有效提辭導體之崩潰電[同時,透過 没極結構特殊的開口形械配置,可使元件具有較低導通電阻, 更可達成”有效運用的效果,提升晶片上半導體元件之積集 度,以因應高儲存容量之電子元件製作技術。 雖然本發明赠述之較佳實酬揭露如上,然其並非用以限 定本發明,任够有财知識者,在不雌本㈣之精神和範圍 ^,當可作些狀更__,耻本發日狀專娜職圍須視 本_書_之㈣翻細所界定者解。 【圖式簡單說明】 j U圖係為先前技術LDM〇S元件結構之配置圖; 弟iB圖係為先前技術LDM0S元件結構之剖面圖; f圖第M圖係為本發明高壓半導體元件結構之較佳實施例之配 第沈圖係為本發明高壓半導體元件結構之較佳實施例之剖 係為本發明綠半導體元件之延伸結構示意圖:似 【主要元^Γ_體元件之另,結構示意圖。 10 … 南壓橫向擴散金屬氧化物半導體 12 200816323 η、31、51、61 源極結構 11, 突出部 12、32、52、62 >及極結構 13、33 >及極延伸結構 14、34 閘極結構 15、35 P型基板 16、42 源極電極 17、43 P型井區 18、22、37、44 n+型摻雜區 19、45 P+型摻雜區 20、36 汲極電極 21 ^ 38 η型井區 23、39 η型漂移延伸區 24、40 ρ型掺雜區 25、47 閘極絕緣層 26、46 閘極電極 30 高壓半導體 41、27 場效通道區 48 絕緣層 111 尖端 13

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  1. 200816323 十、申請專利範圍: 1· 一種高壓半導體元件結構,其包含有: 一基板; 一汲極結構,係由彼此絕緣性地緊鄰交錯相嵌之兩開口形 結構形成於絲板上,且減處之該關口形結構财義出兩 第-區域、兩第二區域及一第三區域,其中該第一區域緊鄰該 開口形結構,該第二區域緊鄰該第—區域,該第三區域介於該 兩第二區域間,各該開口形結構包含一第一井區、一第一摻雜 區及一汲極電極,該汲極電極形成於該基板上,該第一摻雜區 形成於該汲極電極下方之縣板巾且與舰極電極相連接,該 第一井區形成於該基板中並圍繞該第一摻雜區,· 一汲極延伸結構,係形成於該基板中且位於該第一區域, 該汲極延伸結構具有一漂移延伸區,該漂移延伸區係與該第一 井區相鄰; 一源極結構,係形成於該基板中且位於該第三區域,該源 極、、Ό構包含—第二井區、至少―第二摻雜區及—源極電極,其 中該源極電極形成於該基板上,該至少―第二摻雜區形成於該 源極電極下方之該基板中且與該源極電極相連接,該第二井區 形成於該基板中且圍繞該至少一第二摻雜區;以及 一閘極結構,形成於該基板上且位於該第二區域,其包含 -閘極絕緣層及—雛雜,該閘極結構下方形成—場效通道 14 200816323 區。 2·如申請專利範圍第i項所述之高壓半導體元件呈 極結構與相鄰之魏極結構與該源極結二緣中該間 -3‘T梅购親之 -井晴雜打型導電離子,且該第—摻 雜= 度N型導電離子。 有尚浪 4. _料機項所狀縫轉妓件結構,兑 移延伸區中摻雜有低濃度Ν型導電離子。 該沐 5. 如申4專利_第1項所述之縫半導體元件結 移延伸區更包含至少—第三摻龍 ^中該七 雜有!>型導電離子。 ㈣雜區中摻 6. 如中請專利翻第〗項所述之高壓半導體元件結構,立中 一井區中摻雜有ρ型導電離子。 人 齡7,如申請專利範圍第!項所述之高壓半導體元件結構,立中輕 娜區中可摻雜Ν型或ρ型導電離子,且彼此相鄰之 “至少罘一掺雜區係摻雜不同導電離子型能。 8. 如申請細項所述之高料導體树結構,其中該兩 開口形結構之該汲極電極可藉由外部打線(wireb〇 結。 9. 如申請專繼圍第i韻数緒半㈣树結構,其中該開 口形結構可為一馬蹄形或U形結構。 200816323 10. 如申請專利範圍第1項所述之高壓半導體元件結構,其中該開 口形結構可為一S形或扁梳狀結構。 11. 如申請專利範圍第10項所述之高壓半導體元件結構,其中該 源極結構可為一 S形或連續相接之S形結構。 16
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TWI548095B (zh) * 2014-01-28 2016-09-01 旺宏電子股份有限公司 半導體元件及其製造方法

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