TW200735373A - Substrate manufacturing method and substrate processing device - Google Patents

Substrate manufacturing method and substrate processing device

Info

Publication number
TW200735373A
TW200735373A TW096102450A TW96102450A TW200735373A TW 200735373 A TW200735373 A TW 200735373A TW 096102450 A TW096102450 A TW 096102450A TW 96102450 A TW96102450 A TW 96102450A TW 200735373 A TW200735373 A TW 200735373A
Authority
TW
Taiwan
Prior art keywords
substrate
manufacturing
oxide
processing device
substrate processing
Prior art date
Application number
TW096102450A
Other languages
English (en)
Chinese (zh)
Other versions
TWI342071B (enExample
Inventor
Koji Yabushita
Masami Hayashi
Takahito Yamabe
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of TW200735373A publication Critical patent/TW200735373A/zh
Application granted granted Critical
Publication of TWI342071B publication Critical patent/TWI342071B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
TW096102450A 2006-03-08 2007-01-23 Substrate manufacturing method and substrate processing device TW200735373A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006062495A JP2007242848A (ja) 2006-03-08 2006-03-08 基板の製造方法及び基板処理装置

Publications (2)

Publication Number Publication Date
TW200735373A true TW200735373A (en) 2007-09-16
TWI342071B TWI342071B (enExample) 2011-05-11

Family

ID=38588105

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096102450A TW200735373A (en) 2006-03-08 2007-01-23 Substrate manufacturing method and substrate processing device

Country Status (4)

Country Link
JP (1) JP2007242848A (enExample)
KR (1) KR100879038B1 (enExample)
CN (1) CN101034659A (enExample)
TW (1) TW200735373A (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5794194B2 (ja) * 2012-04-19 2015-10-14 東京エレクトロン株式会社 基板処理装置
KR102436641B1 (ko) 2015-10-23 2022-08-26 삼성디스플레이 주식회사 표시 장치 및 그 제조방법
CN106711231A (zh) * 2017-01-13 2017-05-24 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、显示基板及其制备方法
WO2018181296A1 (ja) * 2017-03-29 2018-10-04 シャープ株式会社 チャネルエッチ型薄膜トランジスタの製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3081954B2 (ja) * 1995-06-13 2000-08-28 日本プレシジョン・サーキッツ株式会社 Ｍｏｓ型トランジスタの製造方法
US5935648A (en) 1997-03-28 1999-08-10 The United States Of America As Represented By The Secretary Of The Air Force High surface area molybdenum nitride electrodes
US6291282B1 (en) * 1999-02-26 2001-09-18 Texas Instruments Incorporated Method of forming dual metal gate structures or CMOS devices
KR100604804B1 (ko) * 2000-04-17 2006-07-28 삼성전자주식회사 몰리브데늄 박막 및 실리콘 박막을 포함하는 다층막 제조방법

Also Published As

Publication number Publication date
KR100879038B1 (ko) 2009-01-15
CN101034659A (zh) 2007-09-12
JP2007242848A (ja) 2007-09-20
KR20070092121A (ko) 2007-09-12
TWI342071B (enExample) 2011-05-11

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees