TW200725756A - Method for forming a semiconductor structure and structure thereof - Google Patents

Method for forming a semiconductor structure and structure thereof

Info

Publication number
TW200725756A
TW200725756A TW095140122A TW95140122A TW200725756A TW 200725756 A TW200725756 A TW 200725756A TW 095140122 A TW095140122 A TW 095140122A TW 95140122 A TW95140122 A TW 95140122A TW 200725756 A TW200725756 A TW 200725756A
Authority
TW
Taiwan
Prior art keywords
forming
insulating layer
device region
region
overlying
Prior art date
Application number
TW095140122A
Other languages
English (en)
Chinese (zh)
Inventor
Voon-Yew Thean
Jian Chen
Bich-Yen Nguyen
Mariam G Sadaka
Da Zhang
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200725756A publication Critical patent/TW200725756A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/011—Manufacture or treatment comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Landscapes

  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW095140122A 2005-10-31 2006-10-31 Method for forming a semiconductor structure and structure thereof TW200725756A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/263,120 US7575975B2 (en) 2005-10-31 2005-10-31 Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer

Publications (1)

Publication Number Publication Date
TW200725756A true TW200725756A (en) 2007-07-01

Family

ID=37996936

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095140122A TW200725756A (en) 2005-10-31 2006-10-31 Method for forming a semiconductor structure and structure thereof

Country Status (6)

Country Link
US (1) US7575975B2 (enExample)
JP (1) JP5289968B2 (enExample)
KR (1) KR20080070642A (enExample)
CN (1) CN101341597A (enExample)
TW (1) TW200725756A (enExample)
WO (1) WO2007053339A2 (enExample)

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US9543323B2 (en) 2015-01-13 2017-01-10 International Business Machines Corporation Strain release in PFET regions

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US7465972B2 (en) 2005-01-21 2008-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. High performance CMOS device design
US7754560B2 (en) * 2006-01-10 2010-07-13 Freescale Semiconductor, Inc. Integrated circuit using FinFETs and having a static random access memory (SRAM)
US7723805B2 (en) * 2006-01-10 2010-05-25 Freescale Semiconductor, Inc. Electronic device including a fin-type transistor structure and a process for forming the electronic device
US7709303B2 (en) * 2006-01-10 2010-05-04 Freescale Semiconductor, Inc. Process for forming an electronic device including a fin-type structure
US7323392B2 (en) * 2006-03-28 2008-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. High performance transistor with a highly stressed channel
JP4991254B2 (ja) 2006-11-17 2012-08-01 株式会社東芝 二重リング・ネットワークの通信制御方法及び二重リング・ネットワークの伝送局
US7612405B2 (en) * 2007-03-06 2009-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication of FinFETs with multiple fin heights
US7560785B2 (en) 2007-04-27 2009-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having multiple fin heights
JP4459257B2 (ja) * 2007-06-27 2010-04-28 株式会社東芝 半導体装置
JP2010536170A (ja) * 2007-08-08 2010-11-25 エージェンシー フォー サイエンス，テクノロジー アンド リサーチ 半導体構造および製造方法
US8440517B2 (en) * 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8236634B1 (en) * 2011-03-17 2012-08-07 International Business Machines Corporation Integration of fin-based devices and ETSOI devices
US9287385B2 (en) 2011-09-01 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-fin device and method of making same
US8692291B2 (en) 2012-03-27 2014-04-08 International Business Machines Corporation Passive devices for FinFET integrated circuit technologies
JP5612035B2 (ja) * 2012-07-31 2014-10-22 株式会社東芝 半導体装置
US8946063B2 (en) * 2012-11-30 2015-02-03 International Business Machines Corporation Semiconductor device having SSOI substrate with relaxed tensile stress
WO2015099784A1 (en) * 2013-12-27 2015-07-02 Intel Corporation Bi-axial tensile strained ge channel for cmos
CN105336772B (zh) * 2014-05-26 2021-11-30 中芯国际集成电路制造(上海)有限公司 鳍式tfet及其制造方法
US9653602B1 (en) * 2016-03-21 2017-05-16 International Business Machines Corporation Tensile and compressive fins for vertical field effect transistors
CN107305865B (zh) * 2016-04-18 2020-07-07 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
US10229856B2 (en) * 2017-05-16 2019-03-12 International Business Machines Corporation Dual channel CMOS having common gate stacks
US10699967B2 (en) 2018-06-28 2020-06-30 International Business Machines Corporation Co-integration of high carrier mobility PFET and NFET devices on the same substrate using low temperature condensation

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US6551937B2 (en) 2001-08-23 2003-04-22 Institute Of Microelectronics Process for device using partial SOI
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US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
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US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9543323B2 (en) 2015-01-13 2017-01-10 International Business Machines Corporation Strain release in PFET regions
US9761610B2 (en) 2015-01-13 2017-09-12 International Business Machines Corporation Strain release in PFET regions
US9966387B2 (en) 2015-01-13 2018-05-08 International Business Machines Corporation Strain release in pFET regions

Also Published As

Publication number Publication date
KR20080070642A (ko) 2008-07-30
JP2009514247A (ja) 2009-04-02
US20070099353A1 (en) 2007-05-03
CN101341597A (zh) 2009-01-07
JP5289968B2 (ja) 2013-09-11
WO2007053339A2 (en) 2007-05-10
US7575975B2 (en) 2009-08-18
WO2007053339A3 (en) 2007-11-29

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