TW200721312A - Semiconductor on glass insulator with deposited barrier layer - Google Patents

Semiconductor on glass insulator with deposited barrier layer

Info

Publication number
TW200721312A
TW200721312A TW095130584A TW95130584A TW200721312A TW 200721312 A TW200721312 A TW 200721312A TW 095130584 A TW095130584 A TW 095130584A TW 95130584 A TW95130584 A TW 95130584A TW 200721312 A TW200721312 A TW 200721312A
Authority
TW
Taiwan
Prior art keywords
barrier layer
semiconductor
deposited barrier
glass insulator
glass substrate
Prior art date
Application number
TW095130584A
Other languages
English (en)
Other versions
TWI305014B (en
Inventor
James Gregory Couillard
Kishor Purushottam Gadkaree
Original Assignee
Corning Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Corning Inc filed Critical Corning Inc
Publication of TW200721312A publication Critical patent/TW200721312A/zh
Application granted granted Critical
Publication of TWI305014B publication Critical patent/TWI305014B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
TW095130584A 2005-08-26 2006-08-20 Semiconductor on glass insulator with deposited barrier layer TWI305014B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/213,130 US7268051B2 (en) 2005-08-26 2005-08-26 Semiconductor on glass insulator with deposited barrier layer

Publications (2)

Publication Number Publication Date
TW200721312A true TW200721312A (en) 2007-06-01
TWI305014B TWI305014B (en) 2009-01-01

Family

ID=37772148

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095130584A TWI305014B (en) 2005-08-26 2006-08-20 Semiconductor on glass insulator with deposited barrier layer

Country Status (7)

Country Link
US (1) US7268051B2 (zh)
EP (1) EP1929511B1 (zh)
JP (1) JP2009506540A (zh)
KR (1) KR101291956B1 (zh)
CN (1) CN101248515B (zh)
TW (1) TWI305014B (zh)
WO (1) WO2007024549A2 (zh)

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* Cited by examiner, † Cited by third party
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DE102005052358A1 (de) * 2005-09-01 2007-03-15 Osram Opto Semiconductors Gmbh Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement
DE102005052357A1 (de) * 2005-09-01 2007-03-15 Osram Opto Semiconductors Gmbh Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement
US7619283B2 (en) 2007-04-20 2009-11-17 Corning Incorporated Methods of fabricating glass-based substrates and apparatus employing same
EP1993128A3 (en) * 2007-05-17 2010-03-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
US7696058B2 (en) * 2007-10-31 2010-04-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5548395B2 (ja) * 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Soi基板の作製方法
JP5700617B2 (ja) * 2008-07-08 2015-04-15 株式会社半導体エネルギー研究所 Soi基板の作製方法
KR101058105B1 (ko) * 2009-04-06 2011-08-24 삼성모바일디스플레이주식회사 액티브 매트릭스 기판의 제조방법 및 유기 발광 표시장치의 제조방법
KR101127574B1 (ko) * 2009-04-06 2012-03-23 삼성모바일디스플레이주식회사 액티브 매트릭스 기판의 제조방법 및 유기 발광 표시장치의 제조방법
US8674468B2 (en) * 2009-05-29 2014-03-18 Carestream Health, Inc. Imaging array with dual height semiconductor and method of making same
US7948017B2 (en) * 2009-06-19 2011-05-24 Carestream Health, Inc. Digital radiography imager with buried interconnect layer in silicon-on-glass and method of fabricating same
US8129810B2 (en) * 2009-06-19 2012-03-06 Carestream Health, Inc. Continuous large area imaging and display arrays using readout arrays fabricated in silicon-on-glass substrates
US7968358B2 (en) * 2009-07-29 2011-06-28 Carestream Health, Inc. Digital radiographic flat-panel imaging array with dual height semiconductor and method of making same
DE102009042886A1 (de) 2009-09-24 2011-05-26 Schott Ag Verfahren zur Herstellung einer Solarzelle oder eines Transistors mit einer kristallinen Silizium-Dünnschicht
US8377825B2 (en) * 2009-10-30 2013-02-19 Corning Incorporated Semiconductor wafer re-use using chemical mechanical polishing
US8562849B2 (en) * 2009-11-30 2013-10-22 Corning Incorporated Methods and apparatus for edge chamfering of semiconductor wafers using chemical mechanical polishing
US9404160B2 (en) 2009-12-22 2016-08-02 Becton, Dickinson And Company Methods for the detection of microorganisms
JP5643509B2 (ja) * 2009-12-28 2014-12-17 信越化学工業株式会社 応力を低減したsos基板の製造方法
US8357974B2 (en) 2010-06-30 2013-01-22 Corning Incorporated Semiconductor on glass substrate with stiffening layer and process of making the same
US8405036B2 (en) 2010-08-24 2013-03-26 Carestream Health, Inc. Digital radiography imager with buried interconnect layer in silicon-on-glass and method of fabricating same
TWI555205B (zh) 2010-11-05 2016-10-21 半導體能源研究所股份有限公司 半導體裝置及半導體裝置的製造方法
JP5810718B2 (ja) * 2011-03-18 2015-11-11 富士ゼロックス株式会社 シリコン層転写用基板及び半導体基板の製造方法
CN103872189B (zh) * 2012-12-18 2016-09-07 比亚迪股份有限公司 垂直结构白光led芯片及其制备方法
EP3475975B1 (en) * 2016-06-24 2021-12-15 Qromis, Inc. Method of manufacture of a polycrystalline ceramic substrate
FR3079661A1 (fr) * 2018-03-29 2019-10-04 Soitec Procede de fabrication d'un substrat pour filtre radiofrequence

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FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3352340B2 (ja) * 1995-10-06 2002-12-03 キヤノン株式会社 半導体基体とその製造方法
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US6155909A (en) 1997-05-12 2000-12-05 Silicon Genesis Corporation Controlled cleavage system using pressurized fluid
JPH11307747A (ja) 1998-04-17 1999-11-05 Nec Corp Soi基板およびその製造方法
JP3697106B2 (ja) * 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
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JP4476390B2 (ja) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
TW452866B (en) * 2000-02-25 2001-09-01 Lee Tien Hsi Manufacturing method of thin film on a substrate
US6323408B1 (en) 2000-02-29 2001-11-27 Chi Fai Liu Music creation
US6610582B1 (en) 2002-03-26 2003-08-26 Northrop Grumman Corporation Field-assisted fusion bonding
US7176528B2 (en) 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
JP2004335642A (ja) * 2003-05-06 2004-11-25 Canon Inc 基板およびその製造方法
FR2856192B1 (fr) * 2003-06-11 2005-07-29 Soitec Silicon On Insulator Procede de realisation de structure heterogene et structure obtenue par un tel procede
JP4523299B2 (ja) * 2003-10-31 2010-08-11 学校法人早稲田大学 薄膜コンデンサの製造方法

Also Published As

Publication number Publication date
KR20080049068A (ko) 2008-06-03
EP1929511A2 (en) 2008-06-11
US20070048968A1 (en) 2007-03-01
WO2007024549A3 (en) 2007-09-07
CN101248515A (zh) 2008-08-20
WO2007024549A2 (en) 2007-03-01
EP1929511A4 (en) 2009-09-23
TWI305014B (en) 2009-01-01
JP2009506540A (ja) 2009-02-12
US7268051B2 (en) 2007-09-11
CN101248515B (zh) 2012-03-28
KR101291956B1 (ko) 2013-08-09
EP1929511B1 (en) 2016-04-13

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees