TW200713456A - Multiple low and high k gate oxides on single gate for lower miller capacitance and improved drive current - Google Patents
Multiple low and high k gate oxides on single gate for lower miller capacitance and improved drive currentInfo
- Publication number
- TW200713456A TW200713456A TW095134869A TW95134869A TW200713456A TW 200713456 A TW200713456 A TW 200713456A TW 095134869 A TW095134869 A TW 095134869A TW 95134869 A TW95134869 A TW 95134869A TW 200713456 A TW200713456 A TW 200713456A
- Authority
- TW
- Taiwan
- Prior art keywords
- gate
- gate oxide
- oxide
- overlaying
- drive current
- Prior art date
Links
- 239000004020 conductor Substances 0.000 abstract 5
- 239000000463 material Substances 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/018—Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
- H10D64/683—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being parallel to the channel plane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/162,778 US20070063277A1 (en) | 2005-09-22 | 2005-09-22 | Multiple low and high k gate oxides on single gate for lower miller capacitance and improved drive current |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW200713456A true TW200713456A (en) | 2007-04-01 |
Family
ID=37883219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW095134869A TW200713456A (en) | 2005-09-22 | 2006-09-20 | Multiple low and high k gate oxides on single gate for lower miller capacitance and improved drive current |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20070063277A1 (enExample) |
| EP (1) | EP1927128A4 (enExample) |
| JP (1) | JP2009509359A (enExample) |
| KR (1) | KR20080058341A (enExample) |
| CN (1) | CN101268543A (enExample) |
| TW (1) | TW200713456A (enExample) |
| WO (1) | WO2007038237A2 (enExample) |
Families Citing this family (19)
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| US7326655B2 (en) * | 2005-09-29 | 2008-02-05 | Tokyo Electron Limited | Method of forming an oxide layer |
| US8187486B1 (en) | 2007-12-13 | 2012-05-29 | Novellus Systems, Inc. | Modulating etch selectivity and etch rate of silicon nitride thin films |
| US7964467B2 (en) * | 2008-03-26 | 2011-06-21 | International Business Machines Corporation | Method, structure and design structure for customizing history effects of soi circuits |
| US8420460B2 (en) * | 2008-03-26 | 2013-04-16 | International Business Machines Corporation | Method, structure and design structure for customizing history effects of SOI circuits |
| US8410554B2 (en) * | 2008-03-26 | 2013-04-02 | International Business Machines Corporation | Method, structure and design structure for customizing history effects of SOI circuits |
| JP4902888B2 (ja) * | 2009-07-17 | 2012-03-21 | パナソニック株式会社 | 半導体装置およびその製造方法 |
| US9257325B2 (en) * | 2009-09-18 | 2016-02-09 | GlobalFoundries, Inc. | Semiconductor structures and methods for forming isolation between Fin structures of FinFET devices |
| US8436404B2 (en) | 2009-12-30 | 2013-05-07 | Intel Corporation | Self-aligned contacts |
| DE102010042229B4 (de) * | 2010-10-08 | 2012-10-25 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zum Steigern der Integrität eines Gatestapels mit großem ε durch Erzeugen einer gesteuerten Unterhöhlung auf der Grundlage einer Nasschemie und mit den Verfahren hergestellter Transistor |
| US8896030B2 (en) | 2012-09-07 | 2014-11-25 | Intel Corporation | Integrated circuits with selective gate electrode recess |
| US9064948B2 (en) | 2012-10-22 | 2015-06-23 | Globalfoundries Inc. | Methods of forming a semiconductor device with low-k spacers and the resulting device |
| JP5973665B2 (ja) * | 2013-06-13 | 2016-08-23 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Sgtを有する半導体装置とその製造方法 |
| US9385214B2 (en) * | 2013-07-17 | 2016-07-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a selectively adjustable gate structure |
| US9431268B2 (en) | 2015-01-05 | 2016-08-30 | Lam Research Corporation | Isotropic atomic layer etch for silicon and germanium oxides |
| US9425041B2 (en) | 2015-01-06 | 2016-08-23 | Lam Research Corporation | Isotropic atomic layer etch for silicon oxides using no activation |
| WO2019226341A1 (en) | 2018-05-25 | 2019-11-28 | Lam Research Corporation | Thermal atomic layer etch with rapid temperature cycling |
| EP3821457A4 (en) | 2018-07-09 | 2022-04-13 | Lam Research Corporation | ETCHING ATOMIC LAYER ETCHING USING ELECTRON EXCITATION |
| JP7739434B2 (ja) | 2021-02-03 | 2025-09-16 | ラム リサーチ コーポレーション | 原子層エッチングにおけるエッチング選択性の制御 |
| CN117613005B (zh) * | 2024-01-23 | 2024-04-26 | 中国科学院长春光学精密机械与物理研究所 | 一种混合型cmos器件及其制作方法 |
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| JP3266433B2 (ja) * | 1994-12-22 | 2002-03-18 | 三菱電機株式会社 | 半導体装置の製造方法 |
| JPH113990A (ja) * | 1996-04-22 | 1999-01-06 | Sony Corp | 半導体装置およびその製造方法 |
| KR100268933B1 (ko) * | 1997-12-27 | 2000-10-16 | 김영환 | 반도체 소자의 구조 및 제조 방법 |
| US6140167A (en) * | 1998-08-18 | 2000-10-31 | Advanced Micro Devices, Inc. | High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation |
| US6492695B2 (en) * | 1999-02-16 | 2002-12-10 | Koninklijke Philips Electronics N.V. | Semiconductor arrangement with transistor gate insulator |
| US6103559A (en) * | 1999-03-30 | 2000-08-15 | Amd, Inc. (Advanced Micro Devices) | Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication |
| US6194748B1 (en) * | 1999-05-03 | 2001-02-27 | Advanced Micro Devices, Inc. | MOSFET with suppressed gate-edge fringing field effect |
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| JP2001284360A (ja) * | 2000-03-31 | 2001-10-12 | Hitachi Ltd | 半導体装置 |
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| US6586289B1 (en) * | 2001-06-15 | 2003-07-01 | International Business Machines Corporation | Anti-spacer structure for improved gate activation |
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| US6544874B2 (en) * | 2001-08-13 | 2003-04-08 | International Business Machines Corporation | Method for forming junction on insulator (JOI) structure |
| US6642147B2 (en) * | 2001-08-23 | 2003-11-04 | International Business Machines Corporation | Method of making thermally stable planarizing films |
| US6656798B2 (en) * | 2001-09-28 | 2003-12-02 | Infineon Technologies, Ag | Gate processing method with reduced gate oxide corner and edge thinning |
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| DE10351030B4 (de) * | 2003-10-31 | 2008-05-29 | Qimonda Ag | Speicherzelle, DRAM und Verfahren zur Herstellung einer Transistorstruktur in einem Halbleitersubstrat |
| US7122849B2 (en) * | 2003-11-14 | 2006-10-17 | International Business Machines Corporation | Stressed semiconductor device structures having granular semiconductor material |
| US7247534B2 (en) * | 2003-11-19 | 2007-07-24 | International Business Machines Corporation | Silicon device on Si:C-OI and SGOI and method of manufacture |
| US6989322B2 (en) * | 2003-11-25 | 2006-01-24 | International Business Machines Corporation | Method of forming ultra-thin silicidation-stop extensions in mosfet devices |
| US7160771B2 (en) * | 2003-11-28 | 2007-01-09 | International Business Machines Corporation | Forming gate oxides having multiple thicknesses |
| US7705345B2 (en) * | 2004-01-07 | 2010-04-27 | International Business Machines Corporation | High performance strained silicon FinFETs device and method for forming same |
| US7161203B2 (en) * | 2004-06-04 | 2007-01-09 | Micron Technology, Inc. | Gated field effect device comprising gate dielectric having different K regions |
| JP2007019177A (ja) * | 2005-07-06 | 2007-01-25 | Toshiba Corp | 半導体装置 |
-
2005
- 2005-09-22 US US11/162,778 patent/US20070063277A1/en not_active Abandoned
-
2006
- 2006-09-20 TW TW095134869A patent/TW200713456A/zh unknown
- 2006-09-22 EP EP06804017A patent/EP1927128A4/en not_active Withdrawn
- 2006-09-22 WO PCT/US2006/036916 patent/WO2007038237A2/en not_active Ceased
- 2006-09-22 KR KR1020087006660A patent/KR20080058341A/ko not_active Ceased
- 2006-09-22 CN CNA2006800342746A patent/CN101268543A/zh active Pending
- 2006-09-22 JP JP2008532402A patent/JP2009509359A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007038237A2 (en) | 2007-04-05 |
| EP1927128A2 (en) | 2008-06-04 |
| WO2007038237A3 (en) | 2007-07-26 |
| CN101268543A (zh) | 2008-09-17 |
| KR20080058341A (ko) | 2008-06-25 |
| EP1927128A4 (en) | 2009-01-28 |
| JP2009509359A (ja) | 2009-03-05 |
| US20070063277A1 (en) | 2007-03-22 |
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