TW200712524A - Fault diagnosis apparatus and method for system-on-chip (SoC) and SoC in which fault is capable of being diagnosed - Google Patents
Fault diagnosis apparatus and method for system-on-chip (SoC) and SoC in which fault is capable of being diagnosedInfo
- Publication number
- TW200712524A TW200712524A TW095132530A TW95132530A TW200712524A TW 200712524 A TW200712524 A TW 200712524A TW 095132530 A TW095132530 A TW 095132530A TW 95132530 A TW95132530 A TW 95132530A TW 200712524 A TW200712524 A TW 200712524A
- Authority
- TW
- Taiwan
- Prior art keywords
- soc
- fault
- chip
- fault diagnosis
- diagnosed
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050084424A KR100727975B1 (ko) | 2005-09-10 | 2005-09-10 | 시스템 온 칩의 고장 진단 장치 및 방법과 고장 진단이가능한 시스템 온 칩 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200712524A true TW200712524A (en) | 2007-04-01 |
Family
ID=37651164
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095132530A TW200712524A (en) | 2005-09-10 | 2006-09-04 | Fault diagnosis apparatus and method for system-on-chip (SoC) and SoC in which fault is capable of being diagnosed |
Country Status (6)
Country | Link |
---|---|
US (1) | US20070061621A1 (zh) |
EP (1) | EP1762856A1 (zh) |
JP (1) | JP2007078689A (zh) |
KR (1) | KR100727975B1 (zh) |
CN (1) | CN1928573A (zh) |
TW (1) | TW200712524A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI403892B (zh) * | 2007-07-17 | 2013-08-01 | Advantest Corp | 電子元件、主機裝置、通信系統以及程式 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20110071254A (ko) | 2009-12-21 | 2011-06-29 | 삼성전자주식회사 | 시스템온칩 테스트 장치 및 이를 포함하는 시스템온칩 |
JP5347951B2 (ja) * | 2009-12-24 | 2013-11-20 | 富士通セミコンダクター株式会社 | 集積回路及び故障診断回路 |
KR101603287B1 (ko) | 2010-05-17 | 2016-03-14 | 삼성전자주식회사 | 시스템 온 칩 및 그것의 동작 방법 |
CN102508065A (zh) * | 2011-10-28 | 2012-06-20 | 中联重科股份有限公司 | 电气故障诊断方法、系统及工程机械 |
CN103675641B (zh) * | 2013-12-23 | 2016-04-27 | 龙芯中科技术有限公司 | 芯片故障定位方法、装置及系统 |
CN105974299B (zh) * | 2016-05-30 | 2019-08-09 | 珠海市一微半导体有限公司 | 芯片测试控制电路及其方法 |
US10359471B2 (en) * | 2016-06-09 | 2019-07-23 | International Business Machines Corporation | Implementing decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) through scan skewing |
CN108154230B (zh) * | 2016-12-05 | 2020-09-01 | 赛灵思公司 | 深度学习处理器的监控方法和监控装置 |
CN106814306A (zh) * | 2016-12-23 | 2017-06-09 | 深圳市紫光同创电子有限公司 | 一种iol测试验证方法和装置 |
US11408934B2 (en) * | 2017-12-22 | 2022-08-09 | Nvidia Corporation | In system test of chips in functional systems |
KR102453710B1 (ko) | 2018-02-12 | 2022-10-11 | 삼성전자주식회사 | 반도체 장치 |
KR20220094480A (ko) | 2020-12-29 | 2022-07-06 | 에스케이하이닉스 주식회사 | I/o 인터페이스 회로의 옵션 설정을 위한 반도체 장치 |
CN113238535B (zh) * | 2021-06-03 | 2022-02-11 | 中国核动力研究设计院 | 一种核安全级dcs模拟量输入模块故障诊断方法及系统 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5694399A (en) * | 1996-04-10 | 1997-12-02 | Xilinix, Inc. | Processing unit for generating signals for communication with a test access port |
US5983380A (en) * | 1997-09-16 | 1999-11-09 | International Business Machines Corporation | Weighted random pattern built-in self-test |
KR20000044680A (ko) * | 1998-12-30 | 2000-07-15 | 김영환 | 셀프테스트회로를 내장한 반도체 메모리장치 |
US6684358B1 (en) * | 1999-11-23 | 2004-01-27 | Janusz Rajski | Decompressor/PRPG for applying pseudo-random and deterministic test patterns |
US7168032B2 (en) * | 2000-12-15 | 2007-01-23 | Intel Corporation | Data synchronization for a test access port |
US6728916B2 (en) | 2001-05-23 | 2004-04-27 | International Business Machines Corporation | Hierarchical built-in self-test for system-on-chip design |
JP4846128B2 (ja) * | 2001-07-12 | 2011-12-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびそのテスト方法 |
KR20060019552A (ko) * | 2003-05-22 | 2006-03-03 | 테세다 코포레이션 | 반도체 집적회로 테스트용 테스터 구조 |
KR20050055870A (ko) * | 2003-12-09 | 2005-06-14 | 엘지전자 주식회사 | 제이텍을 이용한 원격 다운로딩 장치 및 그 방법 |
WO2005078465A1 (en) * | 2004-02-17 | 2005-08-25 | Institut National Polytechnique De Grenoble | Integrated circuit chip with communication means enabling remote control of testing means of ip cores of the integrated circuit |
KR100594257B1 (ko) * | 2004-02-26 | 2006-06-30 | 삼성전자주식회사 | 내장형 셀프 테스트 회로를 가지는 soc 및 그 셀프테스트 방법 |
US7181663B2 (en) * | 2004-03-01 | 2007-02-20 | Verigy Pte, Ltd. | Wireless no-touch testing of integrated circuits |
KR100641706B1 (ko) * | 2004-11-03 | 2006-11-03 | 주식회사 하이닉스반도체 | 온칩 셀프 테스트 회로 및 신호 왜곡 셀프 테스트 방법 |
KR100683436B1 (ko) * | 2004-08-25 | 2007-02-20 | 숭실대학교산학협력단 | 메모리 자체 테스트 회로 생성기 |
-
2005
- 2005-09-10 KR KR1020050084424A patent/KR100727975B1/ko not_active IP Right Cessation
-
2006
- 2006-08-30 US US11/512,375 patent/US20070061621A1/en not_active Abandoned
- 2006-09-04 TW TW095132530A patent/TW200712524A/zh unknown
- 2006-09-05 EP EP06120122A patent/EP1762856A1/en not_active Withdrawn
- 2006-09-08 JP JP2006244606A patent/JP2007078689A/ja active Pending
- 2006-09-11 CN CNA2006101516501A patent/CN1928573A/zh active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI403892B (zh) * | 2007-07-17 | 2013-08-01 | Advantest Corp | 電子元件、主機裝置、通信系統以及程式 |
Also Published As
Publication number | Publication date |
---|---|
EP1762856A1 (en) | 2007-03-14 |
KR100727975B1 (ko) | 2007-06-14 |
KR20070029528A (ko) | 2007-03-14 |
US20070061621A1 (en) | 2007-03-15 |
JP2007078689A (ja) | 2007-03-29 |
CN1928573A (zh) | 2007-03-14 |
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