TW200710993A - Method for forming self-aligned, dual silicon nitride liner for CMOS devices - Google Patents
Method for forming self-aligned, dual silicon nitride liner for CMOS devicesInfo
- Publication number
- TW200710993A TW200710993A TW095106575A TW95106575A TW200710993A TW 200710993 A TW200710993 A TW 200710993A TW 095106575 A TW095106575 A TW 095106575A TW 95106575 A TW95106575 A TW 95106575A TW 200710993 A TW200710993 A TW 200710993A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- aligned
- type nitride
- silicon nitride
- cmos devices
- Prior art date
Links
- 229910052581 Si3N4 Inorganic materials 0.000 title abstract 2
- 230000009977 dual effect Effects 0.000 title abstract 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title abstract 2
- 150000004767 nitrides Chemical class 0.000 abstract 7
- 239000000463 material Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/906,670 US7101744B1 (en) | 2005-03-01 | 2005-03-01 | Method for forming self-aligned, dual silicon nitride liner for CMOS devices |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200710993A true TW200710993A (en) | 2007-03-16 |
Family
ID=36939409
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095106575A TW200710993A (en) | 2005-03-01 | 2006-02-27 | Method for forming self-aligned, dual silicon nitride liner for CMOS devices |
Country Status (6)
Country | Link |
---|---|
US (1) | US7101744B1 (zh) |
EP (1) | EP1856726A1 (zh) |
JP (1) | JP5147414B2 (zh) |
CN (1) | CN101133481A (zh) |
TW (1) | TW200710993A (zh) |
WO (1) | WO2006093730A1 (zh) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7485517B2 (en) * | 2006-04-07 | 2009-02-03 | United Microelectronics Corp. | Fabricating method of semiconductor device |
US7521307B2 (en) | 2006-04-28 | 2009-04-21 | International Business Machines Corporation | CMOS structures and methods using self-aligned dual stressed layers |
US7585720B2 (en) * | 2006-07-05 | 2009-09-08 | Toshiba America Electronic Components, Inc. | Dual stress liner device and method |
US7482215B2 (en) * | 2006-08-30 | 2009-01-27 | International Business Machines Corporation | Self-aligned dual segment liner and method of manufacturing the same |
DE102006041006B4 (de) | 2006-08-31 | 2018-05-03 | Advanced Micro Devices, Inc. | Verfahren zur Strukturierung von Kontaktätzstoppschichten unter Anwendung eines Planarisierungsprozesses |
US20080169510A1 (en) * | 2007-01-17 | 2008-07-17 | International Business Machines Corporation | Performance enhancement on both nmosfet and pmosfet using self-aligned dual stressed films |
US7626244B2 (en) * | 2007-02-28 | 2009-12-01 | International Business Machines Corporation | Stressed dielectric devices and methods of fabricating same |
US20090014807A1 (en) * | 2007-07-13 | 2009-01-15 | Chartered Semiconductor Manufacturing, Ltd. | Dual stress liners for integrated circuits |
US7610160B2 (en) * | 2007-09-18 | 2009-10-27 | Globalfoundries Inc. | Integrated circuit tester information processing system |
US7630850B2 (en) * | 2007-10-15 | 2009-12-08 | Advanced Micro Devices, Inc. | Integrated circuit tester information processing system for nonlinear mobility model for strained device |
US7572689B2 (en) * | 2007-11-09 | 2009-08-11 | International Business Machines Corporation | Method and structure for reducing induced mechanical stresses |
JP5285287B2 (ja) * | 2008-02-01 | 2013-09-11 | ローム株式会社 | 半導体装置の製造方法 |
JP5593961B2 (ja) * | 2010-08-25 | 2014-09-24 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
CN102709246B (zh) * | 2012-05-22 | 2015-01-21 | 上海华力微电子有限公司 | 一种形成双应力刻蚀阻挡层的方法 |
CN102709247B (zh) * | 2012-05-22 | 2015-03-18 | 上海华力微电子有限公司 | 一种形成双应力刻蚀阻挡层的方法 |
US10038063B2 (en) | 2014-06-10 | 2018-07-31 | International Business Machines Corporation | Tunable breakdown voltage RF FET devices |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4851370A (en) | 1987-12-28 | 1989-07-25 | American Telephone And Telegraph Company, At&T Bell Laboratories | Fabricating a semiconductor device with low defect density oxide |
US5166771A (en) | 1990-01-12 | 1992-11-24 | Paradigm Technology, Inc. | Self-aligning contact and interconnect structure |
JPH0799189A (ja) | 1993-04-28 | 1995-04-11 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US5633552A (en) | 1993-06-04 | 1997-05-27 | The Regents Of The University Of California | Cantilever pressure transducer |
US5580815A (en) | 1993-08-12 | 1996-12-03 | Motorola Inc. | Process for forming field isolation and a structure over a semiconductor substrate |
JP3304621B2 (ja) | 1994-07-29 | 2002-07-22 | 三菱電機株式会社 | 半導体装置の製造方法 |
US5633202A (en) | 1994-09-30 | 1997-05-27 | Intel Corporation | High tensile nitride layer |
US5506169A (en) | 1994-10-20 | 1996-04-09 | Texas Instruments Incorporated | Method for reducing lateral dopant diffusion |
US6040619A (en) | 1995-06-07 | 2000-03-21 | Advanced Micro Devices | Semiconductor device including antireflective etch stop layer |
TW328147B (en) | 1996-05-07 | 1998-03-11 | Lucent Technologies Inc | Semiconductor device fabrication |
US5891798A (en) | 1996-12-20 | 1999-04-06 | Intel Corporation | Method for forming a High dielectric constant insulator in the fabrication of an integrated circuit |
US5851893A (en) | 1997-07-18 | 1998-12-22 | Advanced Micro Devices, Inc. | Method of making transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection |
US5847463A (en) | 1997-08-22 | 1998-12-08 | Micron Technology, Inc. | Local interconnect comprising titanium nitride barrier layer |
US5985737A (en) | 1998-03-04 | 1999-11-16 | Texas Instruments - Acer Incorporated | Method for forming an isolation region in an integrated circuit |
US6146975A (en) | 1998-07-10 | 2000-11-14 | Lucent Technologies Inc. | Shallow trench isolation |
US6436848B1 (en) | 1999-03-30 | 2002-08-20 | Cypress Semiconductor Corp. | Method for forming nitrogen-rich silicon oxide-based dielectric materials |
US6228777B1 (en) | 1999-06-08 | 2001-05-08 | Intel Corporation | Integrated circuit with borderless contacts |
US6509230B1 (en) | 1999-06-24 | 2003-01-21 | Lucent Technologies Inc. | Non-volatile memory semiconductor device including a graded, grown, high quality oxide layer and associated methods |
US6395610B1 (en) | 1999-06-24 | 2002-05-28 | Lucent Technologies Inc. | Method of making bipolar transistor semiconductor device including graded, grown, high quality oxide layer |
US6214733B1 (en) | 1999-11-17 | 2001-04-10 | Elo Technologies, Inc. | Process for lift off and handling of thin film materials |
US6476462B2 (en) | 1999-12-28 | 2002-11-05 | Texas Instruments Incorporated | MOS-type semiconductor device and method for making same |
US6261924B1 (en) | 2000-01-21 | 2001-07-17 | Infineon Technologies Ag | Maskless process for self-aligned contacts |
US6724053B1 (en) | 2000-02-23 | 2004-04-20 | International Business Machines Corporation | PMOSFET device with localized nitrogen sidewall implantation |
JP2001284466A (ja) * | 2000-03-29 | 2001-10-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2003060076A (ja) * | 2001-08-21 | 2003-02-28 | Nec Corp | 半導体装置及びその製造方法 |
JP4173672B2 (ja) * | 2002-03-19 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
US6573172B1 (en) * | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
US6825529B2 (en) * | 2002-12-12 | 2004-11-30 | International Business Machines Corporation | Stress inducing spacers |
BE1015721A3 (nl) * | 2003-10-17 | 2005-07-05 | Imec Inter Uni Micro Electr | Werkwijze voor het reduceren van de contactweerstand van de aansluitgebieden van een halfgeleiderinrichting. |
US8008724B2 (en) * | 2003-10-30 | 2011-08-30 | International Business Machines Corporation | Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers |
JP4794838B2 (ja) * | 2004-09-07 | 2011-10-19 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
JP5002891B2 (ja) * | 2004-12-17 | 2012-08-15 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
-
2005
- 2005-03-01 US US10/906,670 patent/US7101744B1/en not_active Expired - Fee Related
-
2006
- 2006-02-21 WO PCT/US2006/006143 patent/WO2006093730A1/en active Application Filing
- 2006-02-21 CN CNA2006800066572A patent/CN101133481A/zh active Pending
- 2006-02-21 EP EP06720946A patent/EP1856726A1/en not_active Withdrawn
- 2006-02-21 JP JP2007558060A patent/JP5147414B2/ja not_active Expired - Fee Related
- 2006-02-27 TW TW095106575A patent/TW200710993A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
JP5147414B2 (ja) | 2013-02-20 |
WO2006093730A1 (en) | 2006-09-08 |
JP2008532316A (ja) | 2008-08-14 |
US20060199320A1 (en) | 2006-09-07 |
US7101744B1 (en) | 2006-09-05 |
EP1856726A1 (en) | 2007-11-21 |
CN101133481A (zh) | 2008-02-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200710993A (en) | Method for forming self-aligned, dual silicon nitride liner for CMOS devices | |
TW200723511A (en) | Semiconductor devices, CMOS image sensors, and methods of manufacturing same | |
SG166085A1 (en) | Semiconductor device including a mos transistor and production method therefor | |
WO2006026010A3 (en) | Forming abrupt source drain metal gate transistors | |
TW200709415A (en) | Gate pattern of semiconductor device and method for fabricating the same | |
TW200620456A (en) | Processes for pre-tapering silicon or silicon-germanium prior to etching shallow trenches | |
TW200741978A (en) | Stressor integration and method thereof | |
TW200620668A (en) | Vertical trench gate transistor semiconductor device and method for fabricating the same | |
WO2011087605A3 (en) | Wrap-around contacts for finfet and tri-gate devices | |
AU2003303885A1 (en) | Semiconductor substrate, field-effect transistor, and their production methods | |
WO2007146872A3 (en) | Scalable process and structure for jfet for small and decreasing line widths | |
TW200625529A (en) | Contact hole structures and contact structures and fabrication methods thereof | |
WO2005122284A3 (en) | Semiconductor-on-diamond devices and methods of forming | |
TW200742045A (en) | Semiconductor device having a recess channel transistor | |
TW200633125A (en) | Semiconductor device and method of semiconductor device | |
WO2006036297A3 (en) | Organic electroluminescence device and method of production of same | |
WO2006036985A3 (en) | Shallow source mosfet | |
WO2004081982A3 (en) | Shallow trench isolation process | |
TW200703638A (en) | Image sensor and method for fabricating the same | |
JP2007520891A5 (zh) | ||
TW200601593A (en) | Gate electrode for a semiconductor fin device | |
WO2011071598A3 (en) | Quantum-well-based semiconductor devices | |
WO2010051133A3 (en) | Semiconductor devices having faceted silicide contacts, and related fabrication methods | |
GB2457411A (en) | Stress enhanced transistor and methods for its fabrication | |
WO2007078957A3 (en) | Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers |