TW200710651A - Automatic detection of micro-tile enabled memory - Google Patents

Automatic detection of micro-tile enabled memory

Info

Publication number
TW200710651A
TW200710651A TW095123913A TW95123913A TW200710651A TW 200710651 A TW200710651 A TW 200710651A TW 095123913 A TW095123913 A TW 095123913A TW 95123913 A TW95123913 A TW 95123913A TW 200710651 A TW200710651 A TW 200710651A
Authority
TW
Taiwan
Prior art keywords
memory
cache line
micro
tile
bit pattern
Prior art date
Application number
TW095123913A
Other languages
English (en)
Other versions
TWI336837B (en
Inventor
Douglas Gabel
James Akiyama
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW200710651A publication Critical patent/TW200710651A/zh
Application granted granted Critical
Publication of TWI336837B publication Critical patent/TWI336837B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
TW095123913A 2005-06-30 2006-06-30 Automatic detection of micro-tile enabled memory TWI336837B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/172,766 US7558941B2 (en) 2005-06-30 2005-06-30 Automatic detection of micro-tile enabled memory

Publications (2)

Publication Number Publication Date
TW200710651A true TW200710651A (en) 2007-03-16
TWI336837B TWI336837B (en) 2011-02-01

Family

ID=37591166

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095123913A TWI336837B (en) 2005-06-30 2006-06-30 Automatic detection of micro-tile enabled memory

Country Status (7)

Country Link
US (1) US7558941B2 (zh)
EP (1) EP1896961B1 (zh)
JP (1) JP4838843B2 (zh)
KR (1) KR100947132B1 (zh)
CN (1) CN1928919B (zh)
TW (1) TWI336837B (zh)
WO (1) WO2007005551A2 (zh)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8253751B2 (en) 2005-06-30 2012-08-28 Intel Corporation Memory controller interface for micro-tiled memory access
US8878860B2 (en) * 2006-12-28 2014-11-04 Intel Corporation Accessing memory using multi-tiling
US8427497B1 (en) 2008-08-01 2013-04-23 Marvell International Ltd. Methods and apparatuses for processing cached image data
US8988443B2 (en) * 2009-09-25 2015-03-24 Arm Limited Methods of and apparatus for controlling the reading of arrays of data from memory
US9406155B2 (en) * 2009-09-25 2016-08-02 Arm Limited Graphics processing systems
US9349156B2 (en) 2009-09-25 2016-05-24 Arm Limited Adaptive frame buffer compression
GB0916924D0 (en) * 2009-09-25 2009-11-11 Advanced Risc Mach Ltd Graphics processing systems
US8661200B2 (en) 2010-02-05 2014-02-25 Nokia Corporation Channel controller for multi-channel cache
US20110197031A1 (en) * 2010-02-05 2011-08-11 Nokia Corporation Update Handler For Multi-Channel Cache
GB201105716D0 (en) 2011-04-04 2011-05-18 Advanced Risc Mach Ltd Method of and apparatus for displaying windows on a display
US9195426B2 (en) 2013-09-20 2015-11-24 Arm Limited Method and apparatus for generating an output surface from one or more input surfaces in data processing systems
US9182934B2 (en) 2013-09-20 2015-11-10 Arm Limited Method and apparatus for generating an output surface from one or more input surfaces in data processing systems
GB2524467B (en) 2014-02-07 2020-05-27 Advanced Risc Mach Ltd Method of and apparatus for generating an overdrive frame for a display
GB2528265B (en) 2014-07-15 2021-03-10 Advanced Risc Mach Ltd Method of and apparatus for generating an output frame
KR102358177B1 (ko) * 2015-12-24 2022-02-07 에스케이하이닉스 주식회사 제어회로 및 제어회로를 포함하는 메모리 장치
US10067903B2 (en) 2015-07-30 2018-09-04 SK Hynix Inc. Semiconductor device
US11755255B2 (en) 2014-10-28 2023-09-12 SK Hynix Inc. Memory device comprising a plurality of memories sharing a resistance for impedance matching
GB2540562B (en) 2015-07-21 2019-09-04 Advanced Risc Mach Ltd Method of and apparatus for generating a signature representative of the content of an array of data
CN105138380B (zh) * 2015-09-21 2018-06-19 天脉聚源(北京)传媒科技有限公司 一种Linux系统的启动方法及装置
CN108763106B (zh) * 2018-05-31 2020-07-24 西安微电子技术研究所 一种基于交叉存储的Cache实现方法
US10949278B2 (en) * 2018-06-26 2021-03-16 Qualcomm Incorporated Early detection of execution errors
CN111566614B (zh) * 2018-12-14 2023-09-08 深圳市汇顶科技股份有限公司 位宽匹配电路、数据写入装置、数据读出装置和电子设备

Family Cites Families (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3323109A (en) 1963-12-30 1967-05-30 North American Aviation Inc Multiple computer-multiple memory system
JPS51127626A (en) 1975-04-30 1976-11-06 Hitachi Ltd Information processor
US3988717A (en) 1975-08-06 1976-10-26 Litton Systems, Inc. General purpose computer or logic chip and system
NL7510904A (nl) 1975-09-17 1977-03-21 Philips Nv Woordgroepsprioriteitsinrichting.
US4124891A (en) 1976-11-18 1978-11-07 Honeywell Information Systems Inc. Memory access system
JPS5725052A (en) * 1980-07-22 1982-02-09 Nec Corp Memory control device
US4495570A (en) 1981-01-14 1985-01-22 Hitachi, Ltd. Processing request allocator for assignment of loads in a distributed processing system
US4504902A (en) 1982-03-25 1985-03-12 At&T Bell Laboratories Cache arrangement for direct memory access block transfer
JPH083805B2 (ja) 1985-06-28 1996-01-17 ヒューレット・パッカード・カンパニー Ｔｌｂ制御方法
JPH0267622A (ja) 1988-09-01 1990-03-07 Kansai Nippon Denki Software Kk ディスク入出力方式
US5325510A (en) 1990-05-25 1994-06-28 Texas Instruments Incorporated Multiprocessor system and architecture with a computation system for minimizing duplicate read requests
US5251310A (en) 1990-06-29 1993-10-05 Digital Equipment Corporation Method and apparatus for exchanging blocks of information between a cache memory and a main memory
JPH056305A (ja) * 1991-06-27 1993-01-14 Oki Electric Ind Co Ltd 主記憶装置構成制御方式
US5526507A (en) 1992-01-06 1996-06-11 Hill; Andrew J. W. Computer memory array control for accessing different memory banks simullaneously
US5459842A (en) 1992-06-26 1995-10-17 International Business Machines Corporation System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory
JPH0695959A (ja) * 1992-09-09 1994-04-08 Hitachi Ltd 情報処理装置
JP3240709B2 (ja) 1992-10-30 2001-12-25 株式会社アドバンテスト メモリ試験装置
US6804760B2 (en) * 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
JP3619565B2 (ja) * 1995-04-26 2005-02-09 株式会社ルネサステクノロジ データ処理装置、及びそれを用いたシステム
US5649157A (en) 1995-03-30 1997-07-15 Hewlett-Packard Co. Memory controller with priority queues
WO1996041274A1 (en) 1995-06-07 1996-12-19 Advanced Micro Devices, Inc. Dynamically reconfigurable data bus
JPH09120371A (ja) * 1995-10-26 1997-05-06 Nec Corp メモリ制御装置
US5799209A (en) 1995-12-29 1998-08-25 Chatter; Mukesh Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration
US6061773A (en) 1996-05-03 2000-05-09 Digital Equipment Corporation Virtual memory system with page table space separating a private space and a shared space in a virtual memory
US5761708A (en) 1996-05-31 1998-06-02 Sun Microsystems, Inc. Apparatus and method to speculatively initiate primary memory accesses
US5905725A (en) 1996-12-16 1999-05-18 Juniper Networks High speed switching device
US5748554A (en) * 1996-12-20 1998-05-05 Rambus, Inc. Memory and method for sensing sub-groups of memory elements
US6308248B1 (en) 1996-12-31 2001-10-23 Compaq Computer Corporation Method and system for allocating memory space using mapping controller, page table and frame numbers
US5790118A (en) 1997-03-07 1998-08-04 International Business Machines Corporation Mobile client programmed to hide empty table elements
US5913231A (en) 1997-03-31 1999-06-15 International Business Machines Corporation Method and system for high speed memory address forwarding mechanism
US6145065A (en) 1997-05-02 2000-11-07 Matsushita Electric Industrial Co., Ltd. Memory access buffer and reordering apparatus using priorities
US6151641A (en) 1997-09-30 2000-11-21 Lsi Logic Corporation DMA controller of a RAID storage controller with integrated XOR parity computation capability adapted to compute parity in parallel with the transfer of data segments
US6122709A (en) 1997-12-19 2000-09-19 Sun Microsystems, Inc. Cache with reduced tag information storage
WO1999034294A1 (en) 1997-12-24 1999-07-08 Creative Technology Ltd. Optimal multi-channel memory controller system
US6438675B1 (en) 1998-03-23 2002-08-20 Ati Technologies, Inc. Variable format memory access device
JP4081860B2 (ja) * 1998-06-25 2008-04-30 ソニー株式会社 画像処理装置
US6249851B1 (en) 1998-08-25 2001-06-19 Stmicroelectronics, Inc. Computer system having non-blocking cache and pipelined bus interface unit
US6405273B1 (en) 1998-11-13 2002-06-11 Infineon Technologies North America Corp. Data processing device with memory coupling unit
US6453380B1 (en) 1999-01-23 2002-09-17 International Business Machines Corporation Address mapping for configurable memory system
US6389488B1 (en) 1999-01-28 2002-05-14 Advanced Micro Devices, Inc. Read ahead buffer for read accesses to system memory by input/output devices with buffer valid indication
JP3639464B2 (ja) * 1999-07-05 2005-04-20 株式会社ルネサステクノロジ 情報処理システム
US6708248B1 (en) 1999-07-23 2004-03-16 Rambus Inc. Memory system with channel multiplexing of multiple memory devices
JP2001060169A (ja) 1999-08-24 2001-03-06 Hitachi Ltd キャッシュコントローラ及びコンピュータシステム
JP2001176282A (ja) 1999-12-20 2001-06-29 Fujitsu Ltd 半導体記憶装置およびその制御方法
US6678810B1 (en) 1999-12-30 2004-01-13 Intel Corporation MFENCE and LFENCE micro-architectural implementation method and system
US6430672B1 (en) 2000-07-17 2002-08-06 International Business Machines Corporation Method for performing address mapping using two lookup tables
EP1182564A3 (en) 2000-08-21 2004-07-28 Texas Instruments France Local memory with indicator bits to support concurrent DMA and CPU access
US7006505B1 (en) 2000-10-23 2006-02-28 Bay Microsystems, Inc. Memory management system and algorithm for network processor architecture
US6745272B2 (en) 2001-04-04 2004-06-01 Advanced Micro Devices, Inc. System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system
US7200759B2 (en) 2001-06-08 2007-04-03 Safenet B.V. Method and device for making information contents of a volatile semiconductor memory irretrievable
US20030056058A1 (en) 2001-09-17 2003-03-20 Alistair Veitch Logical volume data migration
US6812928B2 (en) 2002-01-30 2004-11-02 Sun Microsystems, Inc. Performance texture mapping by combining requests for image data
US20030179598A1 (en) * 2002-03-20 2003-09-25 Yu-Guang Chen Device for selectively providing read-only data
DE10216611A1 (de) 2002-04-15 2003-11-06 Infineon Technologies Ag Verfahren zum Ersetzen eines Inhalts einer Datenspeichereinheit
US6842828B2 (en) 2002-04-30 2005-01-11 Intel Corporation Methods and arrangements to enhance an upbound path
US7028200B2 (en) 2002-05-15 2006-04-11 Broadcom Corporation Method and apparatus for adaptive power management of memory subsystem
US6934804B2 (en) 2002-05-28 2005-08-23 Sun Microsystems, Inc. Method and system for striping spares in a data storage system including an array of disk drives
US6820181B2 (en) 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
US6851030B2 (en) 2002-10-16 2005-02-01 International Business Machines Corporation System and method for dynamically allocating associative resources
US7130229B2 (en) 2002-11-08 2006-10-31 Intel Corporation Interleaved mirrored memory systems
US6836434B2 (en) * 2002-11-21 2004-12-28 Micron Technology, Inc. Mode selection in a flash memory device
US7255895B2 (en) 2003-01-21 2007-08-14 Bioarray Solutions, Ltd. Method for controlling solute loading of polymer microparticles
US7243172B2 (en) 2003-10-14 2007-07-10 Broadcom Corporation Fragment storage for data alignment and merger
JP4601305B2 (ja) * 2004-02-27 2010-12-22 富士通セミコンダクター株式会社 半導体装置
US8332598B2 (en) 2005-06-23 2012-12-11 Intel Corporation Memory micro-tiling request reordering
US7765366B2 (en) * 2005-06-23 2010-07-27 Intel Corporation Memory micro-tiling
US7587521B2 (en) 2005-06-23 2009-09-08 Intel Corporation Mechanism for assembling memory access requests while speculatively returning data
US8253751B2 (en) * 2005-06-30 2012-08-28 Intel Corporation Memory controller interface for micro-tiled memory access
US8032688B2 (en) * 2005-06-30 2011-10-04 Intel Corporation Micro-tile memory interfaces
US7872892B2 (en) * 2005-07-05 2011-01-18 Intel Corporation Identifying and accessing individual memory devices in a memory channel

Also Published As

Publication number Publication date
WO2007005551A2 (en) 2007-01-11
CN1928919B (zh) 2010-09-22
KR20080015893A (ko) 2008-02-20
US7558941B2 (en) 2009-07-07
WO2007005551A3 (en) 2007-08-16
EP1896961A2 (en) 2008-03-12
JP4838843B2 (ja) 2011-12-14
EP1896961B1 (en) 2012-08-01
KR100947132B1 (ko) 2010-03-12
US20070005890A1 (en) 2007-01-04
JP2008545201A (ja) 2008-12-11
CN1928919A (zh) 2007-03-14
TWI336837B (en) 2011-02-01

Similar Documents

Publication Publication Date Title
TW200710651A (en) Automatic detection of micro-tile enabled memory
TW200733099A (en) Dynamic semiconductor memory with improved refresh mechanism
TW200710661A (en) Memory controller interface for micro-tiled memory access
TW200710662A (en) Micro-tile memory interfaces
TWI257099B (en) Integrated circuit device for providing selectively variable write latency and method thereof
CA2469682A1 (en) Cache operation with non-cache memory
DE602007007566D1 (de) Verschleierung von Speicherzugriffsmustern
TW200710667A (en) Identifying and accessing individual memory devices in a memory channel
SG190955A1 (en) Transaction log recovery
TW200508862A (en) Implementation of memory access control using optimizations
ATE438915T1 (de) Tragbare datenspeichereinrichtung mit einer speicheradressen-abbildungstabelle
TW200710656A (en) Nonvolatile memory device and method of reducing data transfer time of nonvolatile memory device
TW200713283A (en) Semiconductor storage apparatus
DE602007002484D1 (de) Speichervorrichtung mit modus-auswählbarer vorausladung und clock-to-core-taktung
CA2538568A1 (en) Data profiling
ATE509317T1 (de) Verfahren und vorrichtung zur bereitstellung von unabhängigem logischem adressenraum und zugangsverwaltung
TW200641625A (en) Command protocol method for nonvolatile memory
IN2014MN01739A (zh)
WO2008027691A3 (en) Phase-change random access memory employing read before write for resistance stabilization
TW200709216A (en) Memory device and method having a data bypass path to allow rapid testing and calibration
WO2006102665A3 (en) Global modified indicator to reduce power consumption on cache miss
DE602006016041D1 (de) Magnetischer Direktzugriffsspeicherarray mit Bit-/Wortleitungen für gemeinsame Schreibauswahl- und Leseoperationen
WO2008050337A3 (en) Erase history-based flash writing method
WO2011163022A3 (en) Memory write operation methods and circuits
GB2425377B (en) External state cache for computer processor

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees