TW200707456A - Wrapper circuit and method for interfacing between non-muxed type memory controller and muxed type memory - Google Patents

Wrapper circuit and method for interfacing between non-muxed type memory controller and muxed type memory

Info

Publication number
TW200707456A
TW200707456A TW095129356A TW95129356A TW200707456A TW 200707456 A TW200707456 A TW 200707456A TW 095129356 A TW095129356 A TW 095129356A TW 95129356 A TW95129356 A TW 95129356A TW 200707456 A TW200707456 A TW 200707456A
Authority
TW
Taiwan
Prior art keywords
muxed
type memory
address
memory controller
write data
Prior art date
Application number
TW095129356A
Other languages
English (en)
Inventor
Shin-Chan Kang
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200707456A publication Critical patent/TW200707456A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Communication Control (AREA)
  • Memory System (AREA)
TW095129356A 2005-08-11 2006-08-10 Wrapper circuit and method for interfacing between non-muxed type memory controller and muxed type memory TW200707456A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050073866A KR100792213B1 (ko) 2005-08-11 2005-08-11 메모리 컨트롤러와 메모리를 인터페이싱하는 랩퍼 회로

Publications (1)

Publication Number Publication Date
TW200707456A true TW200707456A (en) 2007-02-16

Family

ID=37738046

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095129356A TW200707456A (en) 2005-08-11 2006-08-10 Wrapper circuit and method for interfacing between non-muxed type memory controller and muxed type memory

Country Status (6)

Country Link
US (1) US7818527B2 (zh)
JP (1) JP2007048281A (zh)
KR (1) KR100792213B1 (zh)
CN (1) CN1917079B (zh)
DE (1) DE102006036969A1 (zh)
TW (1) TW200707456A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI773616B (zh) * 2020-12-28 2022-08-01 華邦電子股份有限公司 半導體記憶裝置
TWI824847B (zh) * 2022-11-24 2023-12-01 新唐科技股份有限公司 記憶體分享裝置、方法、可分享記憶體以及其使用之電子設備

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KR100855575B1 (ko) * 2007-04-19 2008-09-01 삼성전자주식회사 디먹스 회로를 가지는 반도체 메모리 장치 및 그의 테스트방법
CN101315807B (zh) * 2007-05-30 2010-04-14 北京芯技佳易微电子科技有限公司 一种随机存储器实现不同配置的方法
US8099539B2 (en) * 2008-03-10 2012-01-17 Lsi Corporation Method and system of a shared bus architecture
JP2011081553A (ja) * 2009-10-06 2011-04-21 Renesas Electronics Corp 情報処理装置及びその制御方法
MY174430A (en) 2011-09-12 2020-04-17 Mimos Berhad A wrapper circuit capable of reducing latency in operation between interfaced memory controller and memory
KR102084553B1 (ko) * 2013-01-03 2020-03-04 삼성전자주식회사 메모리 시스템
US9076553B2 (en) * 2013-11-13 2015-07-07 Taiwan Semiconductor Manufacturing Company Limited SPSRAM wrapper
US9959918B2 (en) 2015-10-20 2018-05-01 Samsung Electronics Co., Ltd. Memory device and system supporting command bus training, and operating method thereof
US9754650B2 (en) * 2015-10-20 2017-09-05 Samsung Electronics Co., Ltd. Memory device and system supporting command bus training, and operating method thereof

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI773616B (zh) * 2020-12-28 2022-08-01 華邦電子股份有限公司 半導體記憶裝置
TWI824847B (zh) * 2022-11-24 2023-12-01 新唐科技股份有限公司 記憶體分享裝置、方法、可分享記憶體以及其使用之電子設備

Also Published As

Publication number Publication date
US20070036005A1 (en) 2007-02-15
CN1917079B (zh) 2011-01-12
KR100792213B1 (ko) 2008-01-07
DE102006036969A1 (de) 2007-03-22
CN1917079A (zh) 2007-02-21
KR20070019880A (ko) 2007-02-15
US7818527B2 (en) 2010-10-19
JP2007048281A (ja) 2007-02-22

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