TW200641624A - Technical fieldmethods and apparatus for list transfers using dma transfers in a multi-processor system - Google Patents

Technical fieldmethods and apparatus for list transfers using dma transfers in a multi-processor system

Info

Publication number
TW200641624A
TW200641624A TW095100561A TW95100561A TW200641624A TW 200641624 A TW200641624 A TW 200641624A TW 095100561 A TW095100561 A TW 095100561A TW 95100561 A TW95100561 A TW 95100561A TW 200641624 A TW200641624 A TW 200641624A
Authority
TW
Taiwan
Prior art keywords
transfers
fieldmethods
technical
processor system
list
Prior art date
Application number
TW095100561A
Other languages
English (en)
Other versions
TWI352905B (en
Inventor
Takeshi Yamazaki
Tsutomu Horikawa
James Allan Kahle
Charles Ray Johns
Michael Norman Day
Peichun Peter Liu
Original Assignee
Sony Computer Entertainment Inc
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc, Ibm filed Critical Sony Computer Entertainment Inc
Publication of TW200641624A publication Critical patent/TW200641624A/zh
Application granted granted Critical
Publication of TWI352905B publication Critical patent/TWI352905B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
TW095100561A 2005-01-05 2006-01-05 Data processing apparatus, data processing method, TWI352905B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/029,891 US7698473B2 (en) 2005-01-05 2005-01-05 Methods and apparatus for list transfers using DMA transfers in a multi-processor system

Publications (2)

Publication Number Publication Date
TW200641624A true TW200641624A (en) 2006-12-01
TWI352905B TWI352905B (en) 2011-11-21

Family

ID=36641981

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095100561A TWI352905B (en) 2005-01-05 2006-01-05 Data processing apparatus, data processing method,

Country Status (8)

Country Link
US (1) US7698473B2 (zh)
EP (1) EP1834245B1 (zh)
JP (1) JP4346612B2 (zh)
KR (1) KR100938942B1 (zh)
CN (1) CN100524270C (zh)
DE (1) DE602006007944D1 (zh)
TW (1) TWI352905B (zh)
WO (1) WO2006073204A2 (zh)

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JP2007207026A (ja) * 2006-02-02 2007-08-16 Matsushita Electric Ind Co Ltd Ｄｍａ転送装置
JP2008071054A (ja) * 2006-09-13 2008-03-27 Ricoh Co Ltd データ転送制御方法、データ処理装置及び画像処理装置
US8041847B1 (en) 2007-05-10 2011-10-18 Marvell International Ltd. Periodic and conditional execution of DMA operations
KR100959136B1 (ko) 2008-07-16 2010-05-25 한국전자통신연구원 직접 메모리 접근 제어기 및 직접 메모리 접근 채널의데이터 전송 방법
US9128699B2 (en) * 2008-12-22 2015-09-08 Intel Corporation Method and system for queuing transfers of multiple non-contiguous address ranges with a single command
JP5423483B2 (ja) * 2010-03-04 2014-02-19 株式会社リコー データ転送制御装置
US10678744B2 (en) * 2010-05-03 2020-06-09 Wind River Systems, Inc. Method and system for lockless interprocessor communication
KR101706201B1 (ko) 2010-12-15 2017-02-15 한국전자통신연구원 다이렉트 메모리 액세스 컨트롤러 및 그것의 동작 방법
US9262163B2 (en) * 2012-12-29 2016-02-16 Intel Corporation Real time instruction trace processors, methods, and systems
KR102306359B1 (ko) * 2015-01-28 2021-09-30 삼성전자주식회사 복수의 프로세서들을 이용한 데이터 운용 방법 및 장치
JP7053891B2 (ja) * 2018-06-27 2022-04-12 シャンハイ カンブリコン インフォメーション テクノロジー カンパニー リミテッド オンチップコードのブレークポイントによるデバッグ方法、オンチッププロセッサ及びブレークポイントによるチップデバッグシステム
KR102075086B1 (ko) 2018-11-13 2020-02-07 현대오트론 주식회사 Dma를 활용한 epm 마이크로틱 생성 긴급 중단 방법
US11385820B2 (en) * 2020-03-04 2022-07-12 Micron Technology, Inc. Command batching for a memory sub-system
CN113849433B (zh) * 2021-09-14 2023-05-23 深圳市昂科技术有限公司 一种总线控制器的执行方法、装置、总线控制器、计算机设备和存储介质

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Also Published As

Publication number Publication date
JP4346612B2 (ja) 2009-10-21
WO2006073204A2 (en) 2006-07-13
WO2006073204A3 (en) 2007-02-08
TWI352905B (en) 2011-11-21
KR20070098900A (ko) 2007-10-05
CN100524270C (zh) 2009-08-05
EP1834245B1 (en) 2009-07-22
CN101099141A (zh) 2008-01-02
DE602006007944D1 (de) 2009-09-03
EP1834245A2 (en) 2007-09-19
JP2006190301A (ja) 2006-07-20
US20060149861A1 (en) 2006-07-06
US7698473B2 (en) 2010-04-13
KR100938942B1 (ko) 2010-01-26

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