MX2013015121A - Transferencia de datos simultanea y control de error para reducir la latencia y mejorar la capacidad de procesamiento a un anfitrion. - Google Patents

Transferencia de datos simultanea y control de error para reducir la latencia y mejorar la capacidad de procesamiento a un anfitrion.

Info

Publication number
MX2013015121A
MX2013015121A MX2013015121A MX2013015121A MX2013015121A MX 2013015121 A MX2013015121 A MX 2013015121A MX 2013015121 A MX2013015121 A MX 2013015121A MX 2013015121 A MX2013015121 A MX 2013015121A MX 2013015121 A MX2013015121 A MX 2013015121A
Authority
MX
Mexico
Prior art keywords
host
block
error
data transfer
error control
Prior art date
Application number
MX2013015121A
Other languages
English (en)
Inventor
Christopher J Sarcone
David G Conroy
Jim Keller
Original Assignee
Apple Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Inc filed Critical Apple Inc
Publication of MX2013015121A publication Critical patent/MX2013015121A/es

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Las modalidades descritas proporcionan un sistema que transfiere datos desde un dispositivo de almacenamiento a un anfitrión. El sistema incluye un mecanismo de comunicación que recibe una solicitud para leer un conjunto de bloques desde el anfitrión. Después, tras leer cada bloque del conjunto de bloques desde el dispositivo de almacenamiento, el mecanismo de comunicación transfiere el bloque a través de una interfaz con el anfitrión. El sistema también incluye un aparato de detección de error que realiza la detección de error en el bloque tras leer el bloque y un aparato de corrección de error que realiza corrección de error en el bloque si se detecta un error en el bloque. El mecanismo de comunicación puede entonces retransferir el bloque al anfitrión después de que el error es eliminado del bloque.
MX2013015121A 2011-09-02 2012-08-28 Transferencia de datos simultanea y control de error para reducir la latencia y mejorar la capacidad de procesamiento a un anfitrion. MX2013015121A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/224,714 US8656251B2 (en) 2011-09-02 2011-09-02 Simultaneous data transfer and error control to reduce latency and improve throughput to a host
PCT/US2012/052713 WO2013033121A1 (en) 2011-09-02 2012-08-28 Simultaneous data transfer and error control to reduce latency and improve throughput to a host

Publications (1)

Publication Number Publication Date
MX2013015121A true MX2013015121A (es) 2014-03-31

Family

ID=46801657

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2013015121A MX2013015121A (es) 2011-09-02 2012-08-28 Transferencia de datos simultanea y control de error para reducir la latencia y mejorar la capacidad de procesamiento a un anfitrion.

Country Status (9)

Country Link
US (2) US8656251B2 (es)
EP (1) EP2751688A1 (es)
JP (1) JP2014529132A (es)
KR (1) KR101598726B1 (es)
CN (1) CN103748561B (es)
AU (1) AU2012302094B2 (es)
BR (1) BR112014002172A2 (es)
MX (1) MX2013015121A (es)
WO (1) WO2013033121A1 (es)

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US11588783B2 (en) * 2015-06-10 2023-02-21 Cisco Technology, Inc. Techniques for implementing IPV6-based distributed storage space
US20170141878A1 (en) * 2015-11-16 2017-05-18 Western Digital Technologies, Inc. Systems and methods for sending data from non-volatile solid state devices before error correction
US10768856B1 (en) * 2018-03-12 2020-09-08 Amazon Technologies, Inc. Memory access for multiple circuit components
CN114978441B (zh) * 2022-06-14 2024-07-12 四川禹明光电技术有限公司 一种用于光纤传感同步传输的监测校正系统

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Also Published As

Publication number Publication date
AU2012302094A1 (en) 2014-01-16
BR112014002172A2 (pt) 2017-03-01
US20140195872A1 (en) 2014-07-10
US9015557B2 (en) 2015-04-21
CN103748561A (zh) 2014-04-23
KR20140025595A (ko) 2014-03-04
US8656251B2 (en) 2014-02-18
KR101598726B1 (ko) 2016-02-29
US20130061111A1 (en) 2013-03-07
JP2014529132A (ja) 2014-10-30
WO2013033121A1 (en) 2013-03-07
CN103748561B (zh) 2019-01-08
AU2012302094B2 (en) 2016-02-18
EP2751688A1 (en) 2014-07-09

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