TW200636907A - Semiconductor device and manufacturing method thereof, and semiconductor integrated circuit - Google Patents

Semiconductor device and manufacturing method thereof, and semiconductor integrated circuit

Info

Publication number
TW200636907A
TW200636907A TW095101851A TW95101851A TW200636907A TW 200636907 A TW200636907 A TW 200636907A TW 095101851 A TW095101851 A TW 095101851A TW 95101851 A TW95101851 A TW 95101851A TW 200636907 A TW200636907 A TW 200636907A
Authority
TW
Taiwan
Prior art keywords
type impurity
manufacturing
integrated circuit
semiconductor device
serving
Prior art date
Application number
TW095101851A
Other languages
English (en)
Chinese (zh)
Inventor
Toshiki Kanamoto
Masumi Yoshida
Tetsuya Watanabe
Takashi Ippoushi
Original Assignee
Renesas Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Tech Corp filed Critical Renesas Tech Corp
Publication of TW200636907A publication Critical patent/TW200636907A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions

Landscapes

  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW095101851A 2005-01-31 2006-01-18 Semiconductor device and manufacturing method thereof, and semiconductor integrated circuit TW200636907A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005022806 2005-01-31
JP2005354478A JP2006237564A (ja) 2005-01-31 2005-12-08 半導体装置及びその製造方法並びに半導体集積回路

Publications (1)

Publication Number Publication Date
TW200636907A true TW200636907A (en) 2006-10-16

Family

ID=36755625

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095101851A TW200636907A (en) 2005-01-31 2006-01-18 Semiconductor device and manufacturing method thereof, and semiconductor integrated circuit

Country Status (4)

Country Link
US (2) US7432581B2 (enExample)
JP (1) JP2006237564A (enExample)
KR (1) KR20060088023A (enExample)
TW (1) TW200636907A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI848274B (zh) * 2022-03-17 2024-07-11 旺宏電子股份有限公司 佈線圖案
US12205894B2 (en) 2022-03-17 2025-01-21 Macronix International Co., Ltd. Routing pattern

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5520435B2 (ja) * 2007-05-11 2014-06-11 ラピスセミコンダクタ株式会社 半導体素子の製造方法
FR2968128B1 (fr) * 2010-11-26 2013-01-04 St Microelectronics Sa Cellule precaracterisee pour circuit intégré
US9318607B2 (en) * 2013-07-12 2016-04-19 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
KR102101836B1 (ko) 2014-07-24 2020-04-17 삼성전자 주식회사 딜레이 셀 및 이를 적용하는 지연 동기 루프 회로와 위상 동기 루프 회로
CN117096160A (zh) * 2017-11-14 2023-11-21 瑞萨电子株式会社 半导体器件
KR102918411B1 (ko) * 2021-03-12 2026-01-26 삼성전자주식회사 반도체 장치

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6740958B2 (en) * 1985-09-25 2004-05-25 Renesas Technology Corp. Semiconductor memory device
US5452251A (en) * 1992-12-03 1995-09-19 Fujitsu Limited Semiconductor memory device for selecting and deselecting blocks of word lines
JP3173268B2 (ja) * 1994-01-06 2001-06-04 富士電機株式会社 Ｍｉｓ電界効果トランジスタを備えた半導体装置
US5702957A (en) * 1996-09-20 1997-12-30 Lsi Logic Corporation Method of making buried metallization structure
JP4278202B2 (ja) 1998-03-27 2009-06-10 株式会社ルネサステクノロジ 半導体装置の設計方法、半導体装置及び記録媒体
JP4540146B2 (ja) 1998-12-24 2010-09-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
TW498435B (en) * 2000-08-15 2002-08-11 Hitachi Ltd Method of producing semiconductor integrated circuit device and method of producing multi-chip module
US6627484B1 (en) * 2000-11-13 2003-09-30 Advanced Micro Devices, Inc. Method of forming a buried interconnect on a semiconductor on insulator wafer and a device including a buried interconnect
KR100672932B1 (ko) 2000-12-26 2007-01-23 삼성전자주식회사 실리콘 온 인슐레이터 트랜지스터 및 그 제조방법
US6800902B2 (en) * 2001-02-16 2004-10-05 Canon Kabushiki Kaisha Semiconductor device, method of manufacturing the same and liquid jet apparatus
JP4154578B2 (ja) 2002-12-06 2008-09-24 日本電気株式会社 半導体装置及びその製造方法
JP3809168B2 (ja) * 2004-02-03 2006-08-16 株式会社東芝 半導体モジュール
JP4814705B2 (ja) * 2005-10-13 2011-11-16 パナソニック株式会社 半導体集積回路装置及び電子装置
JP2007208004A (ja) * 2006-02-01 2007-08-16 Matsushita Electric Ind Co Ltd 半導体集積回路装置及び電子装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI848274B (zh) * 2022-03-17 2024-07-11 旺宏電子股份有限公司 佈線圖案
US12205894B2 (en) 2022-03-17 2025-01-21 Macronix International Co., Ltd. Routing pattern

Also Published As

Publication number Publication date
US20060170052A1 (en) 2006-08-03
US20090011568A1 (en) 2009-01-08
JP2006237564A (ja) 2006-09-07
KR20060088023A (ko) 2006-08-03
US7432581B2 (en) 2008-10-07

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