TW200632933A - Robust and high-speed memory access with adaptive interface timing - Google Patents
Robust and high-speed memory access with adaptive interface timingInfo
- Publication number
- TW200632933A TW200632933A TW094140729A TW94140729A TW200632933A TW 200632933 A TW200632933 A TW 200632933A TW 094140729 A TW094140729 A TW 094140729A TW 94140729 A TW94140729 A TW 94140729A TW 200632933 A TW200632933 A TW 200632933A
- Authority
- TW
- Taiwan
- Prior art keywords
- nand flash
- flash memory
- memory access
- memory
- adaptive interface
- Prior art date
Links
- 230000003044 adaptive effect Effects 0.000 title abstract 3
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4403—Processor initialisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Quality & Reliability (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/993,034 US7061804B2 (en) | 2004-11-18 | 2004-11-18 | Robust and high-speed memory access with adaptive interface timing |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200632933A true TW200632933A (en) | 2006-09-16 |
Family
ID=36386084
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094140729A TW200632933A (en) | 2004-11-18 | 2005-11-18 | Robust and high-speed memory access with adaptive interface timing |
Country Status (5)
Country | Link |
---|---|
US (1) | US7061804B2 (zh) |
CN (1) | CN100578660C (zh) |
MX (1) | MX2007006033A (zh) |
TW (1) | TW200632933A (zh) |
WO (1) | WO2006055717A2 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI505086B (zh) * | 2009-09-21 | 2015-10-21 | Sandisk Technologies Inc | 具有可擴展管線誤差修正之非揮發性記憶體控制器 |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FI20035072A0 (fi) * | 2003-05-22 | 2003-05-22 | Nokia Corp | Liitäntäväylä, elektroniikkalaite ja järjestelmä |
JP4922932B2 (ja) | 2005-06-28 | 2012-04-25 | スパンション エルエルシー | 半導体装置およびその制御方法 |
JP4991131B2 (ja) * | 2005-08-12 | 2012-08-01 | 株式会社東芝 | 半導体記憶装置 |
CN100349108C (zh) * | 2005-11-21 | 2007-11-14 | 北京中星微电子有限公司 | 与非门快闪存储器的物理接口、接口方法和管理设备 |
KR100678124B1 (ko) * | 2006-01-26 | 2007-02-02 | 삼성전자주식회사 | 화상 통신 단말 및 화상 통신 단말의 화상 통신 데이터처리 방법 |
US7773421B2 (en) * | 2006-05-08 | 2010-08-10 | Macronix International Co., Ltd. | Method and apparatus for accessing memory with read error by changing comparison |
US8077516B2 (en) * | 2006-05-08 | 2011-12-13 | Macronix International Co., Ltd. | Method and apparatus for accessing memory with read error by changing comparison |
US7471562B2 (en) * | 2006-05-08 | 2008-12-30 | Macronix International Co., Ltd. | Method and apparatus for accessing nonvolatile memory with read error by changing read reference |
JP2008090433A (ja) * | 2006-09-29 | 2008-04-17 | Toshiba Corp | メモリコントローラ、メモリシステム及びデータ転送方法 |
KR100784865B1 (ko) * | 2006-12-12 | 2007-12-14 | 삼성전자주식회사 | 낸드 플래시 메모리 장치 및 그것을 포함한 메모리 시스템 |
US8065583B2 (en) | 2007-07-06 | 2011-11-22 | Micron Technology, Inc. | Data storage with an outer block code and a stream-based inner code |
US8051358B2 (en) | 2007-07-06 | 2011-11-01 | Micron Technology, Inc. | Error recovery storage along a nand-flash string |
KR101394693B1 (ko) | 2007-08-08 | 2014-05-15 | 엘지전자 주식회사 | Pld 및 nand 플래시 메모리를 이용한 전자기기의 부팅 방법 |
US8499229B2 (en) | 2007-11-21 | 2013-07-30 | Micro Technology, Inc. | Method and apparatus for reading data from flash memory |
US8327245B2 (en) * | 2007-11-21 | 2012-12-04 | Micron Technology, Inc. | Memory controller supporting rate-compatible punctured codes |
US8046542B2 (en) | 2007-11-21 | 2011-10-25 | Micron Technology, Inc. | Fault-tolerant non-volatile integrated circuit memory |
EP2286412A1 (en) | 2007-12-21 | 2011-02-23 | Rambus Inc. | Flash memory timing pre-characterization for use in ormal operation |
US9152496B2 (en) * | 2007-12-21 | 2015-10-06 | Cypress Semiconductor Corporation | High performance flash channel interface |
KR100897298B1 (ko) * | 2007-12-27 | 2009-05-14 | (주)인디링스 | 읽기 신호 타이밍을 조정하는 플래시 메모리 장치 및플래시 메모리 장치의 읽기 제어 방법 |
CN101645026B (zh) * | 2008-08-07 | 2011-11-16 | 创惟科技股份有限公司 | 根据错误更正码更新闪存页面的储存装置与方法 |
US8175012B2 (en) * | 2009-03-26 | 2012-05-08 | Mediatek Inc. | Decoding/encoding method for booting from a NAND flash and system thereof |
CN102034552A (zh) * | 2009-09-25 | 2011-04-27 | 威刚科技(苏州)有限公司 | 存储装置与其资料处理方法 |
US8843692B2 (en) | 2010-04-27 | 2014-09-23 | Conversant Intellectual Property Management Inc. | System of interconnected nonvolatile memories having automatic status packet |
US8386895B2 (en) | 2010-05-19 | 2013-02-26 | Micron Technology, Inc. | Enhanced multilevel memory |
US8555050B2 (en) * | 2010-07-15 | 2013-10-08 | Broadcom Corporation | Apparatus and method thereof for reliable booting from NAND flash memory |
US8464137B2 (en) | 2010-12-03 | 2013-06-11 | International Business Machines Corporation | Probabilistic multi-tier error correction in not-and (NAND) flash memory |
US8595597B2 (en) | 2011-03-03 | 2013-11-26 | Intel Corporation | Adjustable programming speed for NAND memory devices |
US8972824B1 (en) | 2012-05-22 | 2015-03-03 | Pmc-Sierra, Inc. | Systems and methods for transparently varying error correction code strength in a flash drive |
US9176812B1 (en) | 2012-05-22 | 2015-11-03 | Pmc-Sierra, Inc. | Systems and methods for storing data in page stripes of a flash drive |
US8793556B1 (en) | 2012-05-22 | 2014-07-29 | Pmc-Sierra, Inc. | Systems and methods for reclaiming flash blocks of a flash drive |
US9047214B1 (en) | 2012-05-22 | 2015-06-02 | Pmc-Sierra, Inc. | System and method for tolerating a failed page in a flash device |
US8788910B1 (en) | 2012-05-22 | 2014-07-22 | Pmc-Sierra, Inc. | Systems and methods for low latency, high reliability error correction in a flash drive |
US9021337B1 (en) | 2012-05-22 | 2015-04-28 | Pmc-Sierra, Inc. | Systems and methods for adaptively selecting among different error correction coding schemes in a flash drive |
US8996957B1 (en) | 2012-05-22 | 2015-03-31 | Pmc-Sierra, Inc. | Systems and methods for initializing regions of a flash drive having diverse error correction coding (ECC) schemes |
US9183085B1 (en) | 2012-05-22 | 2015-11-10 | Pmc-Sierra, Inc. | Systems and methods for adaptively selecting from among a plurality of error correction coding schemes in a flash drive for robustness and low latency |
US9021336B1 (en) | 2012-05-22 | 2015-04-28 | Pmc-Sierra, Inc. | Systems and methods for redundantly storing error correction codes in a flash drive with secondary parity information spread out across each page of a group of pages |
US9021333B1 (en) | 2012-05-22 | 2015-04-28 | Pmc-Sierra, Inc. | Systems and methods for recovering data from failed portions of a flash drive |
US9577673B2 (en) | 2012-11-08 | 2017-02-21 | Micron Technology, Inc. | Error correction methods and apparatuses using first and second decoders |
US9081701B1 (en) | 2013-03-15 | 2015-07-14 | Pmc-Sierra, Inc. | Systems and methods for decoding data for solid-state memory |
US9053012B1 (en) | 2013-03-15 | 2015-06-09 | Pmc-Sierra, Inc. | Systems and methods for storing data for solid-state memory |
US9009565B1 (en) | 2013-03-15 | 2015-04-14 | Pmc-Sierra, Inc. | Systems and methods for mapping for solid-state memory |
US9026867B1 (en) | 2013-03-15 | 2015-05-05 | Pmc-Sierra, Inc. | Systems and methods for adapting to changing characteristics of multi-level cells in solid-state memory |
US9208018B1 (en) | 2013-03-15 | 2015-12-08 | Pmc-Sierra, Inc. | Systems and methods for reclaiming memory for solid-state memory |
CN103455454B (zh) * | 2013-09-02 | 2016-09-07 | 华为技术有限公司 | 一种控制存储器启动的方法和装置 |
KR102239356B1 (ko) | 2015-02-17 | 2021-04-13 | 삼성전자주식회사 | 클록 제어 유닛 또는 전원 제어 유닛을 포함하는 저장 장치와 메모리 시스템, 그리고 그것의 동작 방법 |
US9772777B2 (en) | 2015-04-27 | 2017-09-26 | Southwest Research Institute | Systems and methods for improved access to flash memory devices |
EP3480698B1 (en) * | 2016-06-28 | 2020-12-09 | Nippon Seiki Co., Ltd. | Display device for vehicle |
US9672905B1 (en) * | 2016-07-22 | 2017-06-06 | Pure Storage, Inc. | Optimize data protection layouts based on distributed flash wear leveling |
CN109903800A (zh) * | 2019-03-15 | 2019-06-18 | 中国科学院上海微系统与信息技术研究所 | 相变储存器控制装置、相变储存器控制方法、电子装置及存储介质 |
CN110955387B (zh) * | 2019-10-25 | 2023-10-24 | 合肥沛睿微电子股份有限公司 | 自适应识别闪存类型方法及计算机可读取存储介质及装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5210870A (en) * | 1990-03-27 | 1993-05-11 | International Business Machines | Database sort and merge apparatus with multiple memory arrays having alternating access |
US5784332A (en) * | 1996-12-12 | 1998-07-21 | Micron Technology Corporation | Clock frequency detector for a synchronous memory device |
JP3999900B2 (ja) * | 1998-09-10 | 2007-10-31 | 株式会社東芝 | 不揮発性半導体メモリ |
JP2002063069A (ja) * | 2000-08-21 | 2002-02-28 | Hitachi Ltd | メモリ制御装置、データ処理システム及び半導体装置 |
-
2004
- 2004-11-18 US US10/993,034 patent/US7061804B2/en active Active
-
2005
- 2005-11-16 CN CN200580046330.3A patent/CN100578660C/zh active Active
- 2005-11-16 MX MX2007006033A patent/MX2007006033A/es active IP Right Grant
- 2005-11-16 WO PCT/US2005/041692 patent/WO2006055717A2/en active Application Filing
- 2005-11-18 TW TW094140729A patent/TW200632933A/zh unknown
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI505086B (zh) * | 2009-09-21 | 2015-10-21 | Sandisk Technologies Inc | 具有可擴展管線誤差修正之非揮發性記憶體控制器 |
Also Published As
Publication number | Publication date |
---|---|
US7061804B2 (en) | 2006-06-13 |
US20060104115A1 (en) | 2006-05-18 |
CN100578660C (zh) | 2010-01-06 |
MX2007006033A (es) | 2007-07-20 |
CN101099216A (zh) | 2008-01-02 |
WO2006055717A3 (en) | 2006-09-14 |
WO2006055717A2 (en) | 2006-05-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200632933A (en) | Robust and high-speed memory access with adaptive interface timing | |
US9229806B2 (en) | Block closure techniques for a data storage device | |
US9165670B2 (en) | Data retention detection techniques for a data storage device | |
KR101369444B1 (ko) | 정정 불가능한 에러를 해결하는 하이브리드 에러 정정 코딩 | |
KR102164630B1 (ko) | 메모리 컨트롤러 및 상기 메모리 컨트롤러의 동작 방법 | |
JP6014748B2 (ja) | メモリのブロックに対してプログラミングステップサイズを調整するシステムおよび方法 | |
US9362003B2 (en) | System and method to decode data subject to a disturb condition | |
US8862967B2 (en) | Statistical distribution based variable-bit error correction coding | |
US9240235B2 (en) | Mitigating disturb effects for non-volatile memory | |
US10474573B2 (en) | Method for managing flash memory module and associated flash memory controller and electronic device | |
TWI417893B (zh) | 資料存取裝置及資料存取方法 | |
US8982617B1 (en) | Block closure techniques for a data storage device | |
WO2014113402A1 (en) | Systems and methods of updating read voltages | |
US9218851B2 (en) | Power drop protection for a data storage device | |
US8589756B2 (en) | Semiconductor memory device, semiconductor memory system, and erasure correction method | |
US9043672B2 (en) | Memory controller, storage device, and memory control method | |
CN106205709B (zh) | 半导体设备及其操作方法 | |
US9183135B2 (en) | Preparation of memory device for access using memory access type indicator signal | |
KR20170035983A (ko) | 고체 상태 드라이브의 전송 버퍼 사용률을 향상시키기 위해 nand 페이지 버퍼들을 사용하는 방법 및 시스템 | |
TWI797464B (zh) | 資料讀取方法、記憶體儲存裝置及記憶體控制電路單元 | |
US9223649B2 (en) | System and method of sending correction data to a buffer of a non-volatile memory | |
US9704594B1 (en) | Inter-cell interference reduction in flash memory devices | |
US20240160566A1 (en) | Independent flash translation layer tables for memory | |
US11977745B2 (en) | Data retry-read method, memory storage device, and memory control circuit element | |
TWI831297B (zh) | 快閃記憶體控制器的控制方法、快閃記憶體控制器以及電子裝置 |