TW200625459A - Method of producing an epitaxial layer on a semiconductor substrate and device produced with such a method - Google Patents
Method of producing an epitaxial layer on a semiconductor substrate and device produced with such a methodInfo
- Publication number
- TW200625459A TW200625459A TW094142656A TW94142656A TW200625459A TW 200625459 A TW200625459 A TW 200625459A TW 094142656 A TW094142656 A TW 094142656A TW 94142656 A TW94142656 A TW 94142656A TW 200625459 A TW200625459 A TW 200625459A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor substrate
- layer
- atoms
- epitaxial layer
- silicon dioxide
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
- H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/914—Doping
- Y10S438/916—Autodoping control or utilization
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Recrystallisation Techniques (AREA)
- Bipolar Transistors (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04106310 | 2004-12-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200625459A true TW200625459A (en) | 2006-07-16 |
Family
ID=36143482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094142656A TW200625459A (en) | 2004-12-06 | 2005-12-02 | Method of producing an epitaxial layer on a semiconductor substrate and device produced with such a method |
Country Status (6)
Country | Link |
---|---|
US (1) | US7923339B2 (zh) |
EP (1) | EP1825503B1 (zh) |
JP (1) | JP4696127B2 (zh) |
CN (1) | CN100533685C (zh) |
TW (1) | TW200625459A (zh) |
WO (1) | WO2006061731A1 (zh) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4182986B2 (ja) * | 2006-04-19 | 2008-11-19 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
US8305829B2 (en) | 2009-02-23 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same |
US8305790B2 (en) | 2009-03-16 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical anti-fuse and related applications |
US8957482B2 (en) | 2009-03-31 | 2015-02-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical fuse and related applications |
US8912602B2 (en) | 2009-04-14 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and methods for forming the same |
US8461015B2 (en) | 2009-07-08 | 2013-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | STI structure and method of forming bottom void in same |
US8482073B2 (en) | 2010-03-25 | 2013-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit including FINFETs and methods for forming the same |
US8623728B2 (en) * | 2009-07-28 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming high germanium concentration SiGe stressor |
US8497528B2 (en) | 2010-05-06 | 2013-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a strained structure |
US9484462B2 (en) | 2009-09-24 | 2016-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of fin field effect transistor |
US8298925B2 (en) | 2010-11-08 | 2012-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming ultra shallow junction |
US8440517B2 (en) | 2010-10-13 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET and method of fabricating the same |
US8629478B2 (en) | 2009-07-31 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure for high mobility multiple-gate transistor |
US8264032B2 (en) * | 2009-09-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Accumulation type FinFET, circuits and fabrication method thereof |
US8980719B2 (en) | 2010-04-28 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for doping fin field-effect transistors |
US8759943B2 (en) | 2010-10-08 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor having notched fin structure and method of making the same |
US8472227B2 (en) | 2010-01-27 | 2013-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and methods for forming the same |
US8264021B2 (en) | 2009-10-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Finfets and methods for forming the same |
US9040393B2 (en) | 2010-01-14 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor structure |
US8603924B2 (en) | 2010-10-19 | 2013-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming gate dielectric material |
US8769446B2 (en) | 2010-11-12 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and device for increasing fin device density for unaligned fins |
US8877602B2 (en) | 2011-01-25 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms of doping oxide for forming shallow trench isolation |
US8592915B2 (en) | 2011-01-25 | 2013-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doped oxide for shallow trench isolation (STI) |
US8431453B2 (en) | 2011-03-31 | 2013-04-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure |
CN102412271A (zh) * | 2011-09-15 | 2012-04-11 | 上海晶盟硅材料有限公司 | 外延片衬底、外延片及半导体器件 |
US8889461B2 (en) | 2012-05-29 | 2014-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | CIS image sensors with epitaxy layers and methods for forming the same |
JP6030455B2 (ja) * | 2013-01-16 | 2016-11-24 | 東京エレクトロン株式会社 | シリコン酸化物膜の成膜方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5256550A (en) | 1988-11-29 | 1993-10-26 | Hewlett-Packard Company | Fabricating a semiconductor device with strained Si1-x Gex layer |
JP2821628B2 (ja) * | 1989-11-10 | 1998-11-05 | ソニー株式会社 | 半導体装置の製造方法 |
JP3074834B2 (ja) | 1991-09-17 | 2000-08-07 | 日本電気株式会社 | シリコンヘテロ接合バイポーラトランジスタ |
JPH07153685A (ja) * | 1993-11-29 | 1995-06-16 | Oki Electric Ind Co Ltd | 歪ヘテロ超格子構造の薄膜形成方法 |
DE69632175T2 (de) | 1995-08-31 | 2004-09-02 | Texas Instruments Inc., Dallas | Herstellungsverfahren einer epitaktischen Schicht mit minimaler Selbstdotierung |
JPH11500873A (ja) * | 1995-12-15 | 1999-01-19 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | SiGe層を具えた半導体電界効果デバイス |
EP0818829A1 (en) | 1996-07-12 | 1998-01-14 | Hitachi, Ltd. | Bipolar transistor and method of fabricating it |
US6723621B1 (en) | 1997-06-30 | 2004-04-20 | International Business Machines Corporation | Abrupt delta-like doping in Si and SiGe films by UHV-CVD |
JP3189878B2 (ja) * | 1997-07-16 | 2001-07-16 | 日本電気株式会社 | バイポーラトランジスタ |
JP3658745B2 (ja) | 1998-08-19 | 2005-06-08 | 株式会社ルネサステクノロジ | バイポーラトランジスタ |
US6346453B1 (en) * | 2000-01-27 | 2002-02-12 | Sige Microsystems Inc. | Method of producing a SI-GE base heterojunction bipolar device |
US6576535B2 (en) * | 2001-04-11 | 2003-06-10 | Texas Instruments Incorporated | Carbon doped epitaxial layer for high speed CB-CMOS |
JP2004538646A (ja) | 2001-08-07 | 2004-12-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | バイポーラトランジスタ及びその製造方法 |
US20030082882A1 (en) * | 2001-10-31 | 2003-05-01 | Babcock Jeffrey A. | Control of dopant diffusion from buried layers in bipolar integrated circuits |
US6764918B2 (en) * | 2002-12-02 | 2004-07-20 | Semiconductor Components Industries, L.L.C. | Structure and method of making a high performance semiconductor device having a narrow doping profile |
-
2005
- 2005-11-29 US US11/721,033 patent/US7923339B2/en active Active
- 2005-11-29 JP JP2007543957A patent/JP4696127B2/ja not_active Expired - Fee Related
- 2005-11-29 WO PCT/IB2005/053945 patent/WO2006061731A1/en active Application Filing
- 2005-11-29 CN CNB2005800419211A patent/CN100533685C/zh active Active
- 2005-11-29 EP EP05807007A patent/EP1825503B1/en active Active
- 2005-12-02 TW TW094142656A patent/TW200625459A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
EP1825503A1 (en) | 2007-08-29 |
JP4696127B2 (ja) | 2011-06-08 |
CN101073148A (zh) | 2007-11-14 |
CN100533685C (zh) | 2009-08-26 |
US7923339B2 (en) | 2011-04-12 |
WO2006061731A1 (en) | 2006-06-15 |
JP2008523584A (ja) | 2008-07-03 |
EP1825503B1 (en) | 2012-08-22 |
US20090305488A1 (en) | 2009-12-10 |
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