TW200620322A - Method for controlling time point for data output in synchronous memory device - Google Patents
Method for controlling time point for data output in synchronous memory deviceInfo
- Publication number
- TW200620322A TW200620322A TW094126115A TW94126115A TW200620322A TW 200620322 A TW200620322 A TW 200620322A TW 094126115 A TW094126115 A TW 094126115A TW 94126115 A TW94126115 A TW 94126115A TW 200620322 A TW200620322 A TW 200620322A
- Authority
- TW
- Taiwan
- Prior art keywords
- memory device
- time point
- synchronous memory
- data output
- read command
- Prior art date
Links
- 230000001360 synchronised effect Effects 0.000 title abstract 5
- 230000003111 delayed effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040101265A KR100608372B1 (ko) | 2004-12-03 | 2004-12-03 | 동기식 메모리 장치의 데이타 출력 시점 조절 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200620322A true TW200620322A (en) | 2006-06-16 |
TWI281674B TWI281674B (en) | 2007-05-21 |
Family
ID=36666291
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094126115A TWI281674B (en) | 2004-12-03 | 2005-08-02 | Method for controlling time point for data output in synchronous memory device |
Country Status (4)
Country | Link |
---|---|
US (3) | US7251191B2 (zh) |
JP (1) | JP4854258B2 (zh) |
KR (1) | KR100608372B1 (zh) |
TW (1) | TWI281674B (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100608372B1 (ko) * | 2004-12-03 | 2006-08-08 | 주식회사 하이닉스반도체 | 동기식 메모리 장치의 데이타 출력 시점 조절 방법 |
KR100746229B1 (ko) * | 2006-07-07 | 2007-08-03 | 삼성전자주식회사 | 반도체 메모리 장치 |
KR100857450B1 (ko) * | 2007-08-10 | 2008-09-10 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 출력 인에이블 신호 생성 회로 및방법 |
CN103871444A (zh) * | 2012-12-14 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | 非挥发性存储器的读时序产生电路 |
KR102162804B1 (ko) | 2014-01-15 | 2020-10-07 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 이의 동작 방법 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4286933B2 (ja) * | 1998-09-18 | 2009-07-01 | 富士通マイクロエレクトロニクス株式会社 | 半導体記憶装置 |
JP2000163961A (ja) * | 1998-11-26 | 2000-06-16 | Mitsubishi Electric Corp | 同期型半導体集積回路装置 |
KR100499623B1 (ko) | 1998-12-24 | 2005-09-26 | 주식회사 하이닉스반도체 | 내부 명령신호 발생장치 및 그 방법 |
KR100304705B1 (ko) | 1999-03-03 | 2001-10-29 | 윤종용 | 포스티드 카스 레이턴시 기능을 가지는 동기식 반도체 메모리 장치 및 카스 레이턴시 제어 방법 |
JP4190662B2 (ja) * | 1999-06-18 | 2008-12-03 | エルピーダメモリ株式会社 | 半導体装置及びタイミング制御回路 |
JP4045064B2 (ja) * | 2000-03-30 | 2008-02-13 | 富士通株式会社 | 半導体記憶装置 |
US6918016B1 (en) * | 2001-07-17 | 2005-07-12 | Advanced Micro Devices, Inc. | Method and apparatus for preventing data corruption during a memory access command postamble |
JP4308461B2 (ja) * | 2001-10-05 | 2009-08-05 | ラムバス・インコーポレーテッド | 半導体記憶装置 |
KR100425472B1 (ko) | 2001-11-12 | 2004-03-30 | 삼성전자주식회사 | 동기식 반도체 메모리 장치의 출력 제어 신호 발생 회로및 출력 제어 신호 발생 방법 |
JP4434568B2 (ja) * | 2002-11-14 | 2010-03-17 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
KR100468776B1 (ko) | 2002-12-10 | 2005-01-29 | 삼성전자주식회사 | 클락 지터의 영향을 감소시킬 수 있는 동기식 반도체메모리장치 |
KR100522433B1 (ko) * | 2003-04-29 | 2005-10-20 | 주식회사 하이닉스반도체 | 도메인 크로싱 회로 |
JP4354284B2 (ja) * | 2004-01-20 | 2009-10-28 | 富士通マイクロエレクトロニクス株式会社 | メモリ制御装置およびメモリ制御システム |
KR100608372B1 (ko) * | 2004-12-03 | 2006-08-08 | 주식회사 하이닉스반도체 | 동기식 메모리 장치의 데이타 출력 시점 조절 방법 |
-
2004
- 2004-12-03 KR KR1020040101265A patent/KR100608372B1/ko not_active IP Right Cessation
-
2005
- 2005-08-02 US US11/194,934 patent/US7251191B2/en active Active
- 2005-08-02 TW TW094126115A patent/TWI281674B/zh active
- 2005-10-11 JP JP2005295961A patent/JP4854258B2/ja not_active Expired - Fee Related
-
2007
- 2007-07-09 US US11/774,657 patent/US7466622B2/en active Active
-
2008
- 2008-11-12 US US12/269,163 patent/US7649802B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US7251191B2 (en) | 2007-07-31 |
TWI281674B (en) | 2007-05-21 |
JP2006164491A (ja) | 2006-06-22 |
US20080016261A1 (en) | 2008-01-17 |
JP4854258B2 (ja) | 2012-01-18 |
US7649802B2 (en) | 2010-01-19 |
US20050265118A1 (en) | 2005-12-01 |
KR20060062429A (ko) | 2006-06-12 |
US20090073787A1 (en) | 2009-03-19 |
KR100608372B1 (ko) | 2006-08-08 |
US7466622B2 (en) | 2008-12-16 |
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