US7251191B2 - Method for controlling time point for data output in synchronous memory device - Google Patents

Method for controlling time point for data output in synchronous memory device Download PDF

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US7251191B2
US7251191B2 US11/194,934 US19493405A US7251191B2 US 7251191 B2 US7251191 B2 US 7251191B2 US 19493405 A US19493405 A US 19493405A US 7251191 B2 US7251191 B2 US 7251191B2
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read command
memory device
cas latency
signal
synchronous memory
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US20050265118A1 (en
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Hyun Woo Lee
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Definitions

  • the present invention relates to a method for controlling a time point for data output in a synchronous memory device, and more particular to a method for controlling a time point for data output in a synchronous memory device according to CAS latency.
  • a memory device such as a DDR SDRAM generates a plurality of control signals (e.g., OE 00 , OE 10 , OE 30 , and OE 50 shown in FIG. 1E ) used for controlling the operation of a data output driver according to CAS latency.
  • control signals are sequentially generated.
  • the control signals are generated in the order of OE 00 , OE 10 , OE 20 , OE 30 , OE 40 and OE 50 .
  • the OE 20 is generated with delay of 1tCK (1tCK is a period of an internal clock signal) as compared with the OE 10
  • the OE 30 is generated with delay of 1tCK as compared with the OE 20
  • the OE 40 is generated with delay of 1tCK as compared with the OE 30 .
  • the OE 00 and the OE 10 are generated with a time difference of 1tCK
  • the OE 10 and the OE 20 are generated with a time difference of 1tCK.
  • a time difference between OE signals adjacent to each other is 1tCK.
  • the time difference may decrease below 1tCK.
  • the control signals (OE signal) sequentially generated with the time difference of 1tCK may collide with each other. This collision may cause malfunction when the memory device outputs data.
  • an object of the present invention is to provide a method for controlling time point for data output by generating control signals (OE signals) with a time difference of 2tCK when the operation frequency increases.
  • a method for controlling a time point for data output of a synchronous memory device comprising the step of varying a time point of an internal read command of the synchronous memory device, which is generated in response to an external read command according to the CAS latency of the synchronous memory device, depending on the CAS latency having an odd number or an even number.
  • a plurality of control signals are outputted in response to the internal read command, the control signals being used for controlling a time point to enable a data output driver of the synchronous memory device.
  • a time point to generate a first internal read command by receiving an external read command when the CAS latency corresponds to 2N+2 is delayed by 1tCK as compared with a time point to generate a second internal read command by receiving the external read command when the CAS latency corresponds to 2N+1, the first internal read command being used in the memory device, and the 1tCK is a period of an external clock applied to the synchronous memory device.
  • a time until the first control signal is generated from after the first internal read command is generated is identical to a time until the second control signal is generated from after the second internal read command is generated.
  • FIGS. 1A to 1E are schematic views of the present invention.
  • FIG. 2 illustrates a time chart for explaining operations of circuits shown in FIGS. 1A to 1E ;
  • FIG. 3 illustrates an example of an output enable signal generating part employed in a counter circuit shown in FIG. 1E ;
  • FIG. 4 illustrates an example of a divider shown in FIG. 1C ;
  • FIG. 5 illustrates a detailed example of a two-divider shown in FIG. 4 ;
  • FIG. 6 illustrates an example of a read command generator described with reference to FIG. 1A .
  • FIG. 1A is a block diagram illustrating a read command generator according to the present invention.
  • ‘CLKb’ denotes an inverted external clock signal
  • ‘casb’ denotes a column address strobe bar signal
  • ‘we’ denotes a write enable signal
  • ‘ras’ denotes a row address strobe signal
  • ‘csb’ denotes a chip select bar signal
  • ‘pwrup’ denotes a power up signal
  • ‘RD_COMMAND’ denotes an internal read command generated by the external read command.
  • CAS latency is the number of clocks corresponding to a time interval required for outputting data after an external read command is applied.
  • the read command generator shown in FIG. 1A receives the external signal and generates a read command used in a memory device.
  • a detailed circuit of FIG. 1A is shown in FIG. 6 . The description about the detailed circuit of FIG. 1A will be described later.
  • FIG. 1B is a block diagram illustrating a counter signal generator for generating an internal counter signal OE 00 which is a control signal used for controlling a time point for read data output by receiving the read command RD_COMMAND.
  • the internal counter signal OE 00 stands for an output enable signal used for transmitting read data to the outside of the memory device.
  • the waveform of the internal counter signal OE 00 is shown in FIG. 2 .
  • Another plurality of internal counter signals OE 10 , OE 30 , OE 50 , etc., to be described later are generated by using the internal counter signal OE 00 (see FIG. 1E ).
  • These internal counter signals OE 10 , OE 30 , OE 50 , etc. control a time point to operate an output driver, thereby controlling a time point for data output stored in the output driver.
  • the internal counter signals OE 10 , OE 30 , OE 50 , OE 70 , etc. are generated in synchronization with a rising edge of a DLL clock
  • the internal counter output signals OE 35 , OE 55 , OE 75 , and OE 95 to be described are generated in synchronization with a falling edge of the DLL clock.
  • a time difference between neighboring signals among the sequentially-generated internal counter signals OE 10 , OE 30 , OE 50 , etc., shown in FIG. 1B corresponds to 2tCK.
  • a time difference between the internal counter signal OE 10 and the internal counter signal OE 30 corresponds to 2tCK
  • a time difference between the internal counter signal OE 30 and the internal counter signal OE 50 corresponds to 2tCK also.
  • FIG. 1C is a block diagram illustrating a divider.
  • the divider shown in FIG. 1C receives a rising DLL clock RCLK_DLL and a falling DLL clock FCLK_DLL output from a DLL circuit of the memory device.
  • the divider divides the frequency of an input signal in the two-division ratio. Accordingly, output signals RCLK_DLL_ 2 X and FCLK_DLL_ 2 X of the divider have double periods as compared with the periods of the input signals RCLK_DLL and FOLK_DLL.
  • FIG. 4 a detailed circuit in FIG. 1C is shown in FIG. 4 .
  • FIG. 1D is a block diagram illustrating a delay circuit delaying the output signals of the divider by a predetermined time interval according to CAS latency.
  • FIG. 1E is a block diagram illustrating a counter including a plurality of output enable signal generating parts.
  • An output enable signal generating part 11 receives the internal counter signal OE 00 (an output signal shown in FIG. 1B ), the delay signal RCLK_DLL_OE 1 output from the delay circuit shown in FIG. 1D , and a reset signal RSTZ, thereby outputting a count signal OE 10 .
  • An output enable signal generating part 13 receives the count signal OE 30 (the output signal of the output enable signal generating part 12 ), the delay signal RCLK_DLL_OE 5 output from the delay circuit shown in FIG. 1D , and a reset signal RSTZ, thereby outputting a count signal OE 05 .
  • An output enable signal generating part 13 receives the count signal OE 30 (the output signal of the output enable signal generating part 12 ), the delay signal RCLK_DLL_OE 5 output from the delay circuit shown in FIG. 1D , and a reset signal RSTZ, thereby outputting a count signal OE 30 .
  • An output enable signal generating part 14 receives the count signal OE 50 (the output signal of the output enable signal generating part 13 ), the delay signal RCLK_DLL_OE 7 output from the delay circuit shown in FIG. 1D ; and a reset signal RSTZ, thereby outputting a count signal OE 70 .
  • An output enable signal generating part 15 receives the count signal OE 70 , which is the output signal of the output enable signal generating part 14 , the delay signal RCLK_DLL_ 2 X output from the divider shown in FIG. 1C , and a reset signal RSTZ, thereby outputting a count signal OE 90 .
  • An output enable signal generating part 16 receives the count signal OE 30 , which is the output signal of the output enable signal generating part 12 , the delay signal RCLK_DLL_OE 35 output from the delay circuit shown in FIG. 1D , and a reset signal RSTZ, thereby outputting a count signal OE 35 .
  • An output enable signal generating part 17 receives the count signal OE 35 , which is the output signal of the output enable signal generating part 16 , the delay signal RCLK_DLL_OE 55 output from the delay circuit shown in FIG. 1D , and a reset signal RSTZ, thereby outputting a count signal OE 55 .
  • An output enable signal generating part 18 receives the count signal OE 55 , which is the output signal of the output enable signal generating part 17 , the delay signal RCLK_DLL_OE 75 output from the delay circuit shown in FIG. 1D , and a reset signal RSTZ, thereby outputting a count signal OE 75 .
  • An output enable signal generating part 19 receives the count signal OE 75 , which is the output signal of the output enable signal generating part 17 , the delay signal RCLK_DLL_ 2 X output from the divider shown in FIG. 1C , and a reset signal RSTZ, thereby outputting a count signal OE 95 .
  • the output signals OE 10 , OE 30 , . . . , OE 95 shown in FIG. 1E controls a time point for data output stored in the output driver of the memory device. According to CAS latency, one of these output signals is selected so as to determine a time point to enable the output driver.
  • the output signal OE 30 is outputted with negative delay of 2tCK- ⁇ as compared with the output signal OE 10
  • the output signal OE 50 is outputted with negative delay of 2tCK- ⁇ as compared with the output signal OE 30 .
  • the remaining output signals are outputted in the same manner.
  • the output signals OE 10 , OE 30 , OE 50 , OE 70 , and OE 90 are generated based on the rising edge of the DLL clock, and the output signals OE 35 , OE 55 , OE 75 , and OE 95 are generated based on the falling edge of the DLL clock.
  • the output signals OE 35 and OE 55 are generated with an interval of 2tCK.
  • the remaining output signals are also generated with an interval of 2tCK.
  • FIG. 2 illustrates a time chart for explaining operations of circuits shown in FIGS. 1A to 1E .
  • RCLK_DLL stands for a rising DLL clock outputted from the DLL circuit
  • CLK stands for an external clock
  • RD_COMMAND stands for an internal read command signal generated from the read command generator.
  • Signals RCLK_DLL_OE 1 , RCLK_DLL_OE 3 , RLCK_DLL_OE 5 , and RLCK_DLL_OE 7 represent signals output from the delay circuit shown in FIG. 1D .
  • the signal RCLK_DLL_ 2 X is obtained by dividing the signal RCLK_DLL in the two-division ratio.
  • FIG. 2 illustrates a time chart when CAS latency corresponds to 9.
  • a synchronous memory device employs the DLL clock RCLK_DLL generated from the DLL circuit.
  • the DLL clock RCLK_DLL rises in synchronization with the rising edge of the external clock applied to the memory device
  • the DLL clock FOLK_DLL rises in synchronization with the falling edge of the external clock applied to the memory device.
  • the DLL clock RCLK_DLL is negatively delayed with respect to the external clock CLK. As generally known, this is because it is necessary to compensate for delay when data are output after the read command is applied from an external device. As shown in FIG. 2 , the numerals marked on the DLL clock RCLK_DLL correspond to the rising edges of the external clock signal CLK.
  • the internal counter signal OE 00 is generated in response to the read command RD_COMMAND (see FIGS. 1 b and 6 ).
  • the counter signal OE 10 is generated by the counter signal OE 00 and the signal RCLK_DLL_OE 1 .
  • the counter signal OE 30 is generated by the counter signal OE 10 and the signal RCLK_DLL_OE 3 .
  • the counter signal OE 50 is generated by the counter signal OE 30 and the signal RCLK_DLL_OE 5 .
  • the counter signal OE 70 is generated by the counter signal OE 50 and the signal RCLK_DLL_OE 7 .
  • the counter signal OE 90 is generated by the counter signal OE 70 and the signal RCLK_DLL_ 2 X. In addition, the counter signal OE 90 is output correspondingly to the ninth rising edge of the DLL clock RCLK_DLL.
  • the data output driver (not shown) is enabled. As shown in FIG. 2 , the data output driver outputs data in synchronization with the ninth pulse of the external clock CLK from after the read command is applied. In other words, since the output driver is enabled while the counter signal OE 90 is being enabled at a high level, data may be output to an external device after a predetermined time interval. Herein, the data are output to an external device from the ninth pulse of the external clock signal CLK after the read command is applied.
  • FIG. 3 illustrates an example of an output enable signal generating part employed in the counter circuit shown in FIG. 1E .
  • ‘RSTZ’ represents a reset signal
  • ‘IN’ represents one of the output signals OE 00 , OE 10 , OE 30 , OE 50 , OE 70 , OE 35 , OE 55 , and OE 75 applied to output enable signal generating parts
  • ‘CLK’ represents one of the signals RCLK_DLL_OE 1 , RCLK_DLL_OE 3 , RCLK_DLL_OE 5 , RCLK_DLL_OE 7 , RCLK_DLL_OE 35 , RCLK_DLL_OE 55 , RCLK_DLL_OE 75 , RCLK_DLL_ 2 X, and FCLK_DLL_ 2 X applied to the output enable signal generating parts, respectively
  • ‘OUT’ represents the output of each output enable signal generating part.
  • the signals RCLK_DLL_ 2 X and FLCK_DLL_ 2 X have double periods as compared with that of the DLL clocks RCLK_DLL and FCLK_DLL. These signals will be described later with reference to FIG. 4 .
  • the IN signal is received and latched when the CLK is at a low level, and the latched IN signal is outputted when the CLK is at a high level.
  • the RSTZ maintains a high level in a normal operation.
  • FIG. 4 illustrates an example of the divider shown in FIG. 1C .
  • the rising DLL clock RCLK_DLL is applied to a two-divider 41 and is outputted as a signal RCLK_DLL_ 2 X having a double period as compared with that of the RCLK_DLL.
  • the falling DLL clock FCLK_DLL is applied to a two-divider 42 and is outputted as a signal FCLK_DLL_ 2 X having a double period as compared with that of the FCLK_DLL.
  • FIG. 5 illustrates a detailed example of the two-divider 41 or 42 shown in FIG. 4 .
  • FIG. 5 illustrates an example of the two-divider shown in FIG. 4 .
  • a divider 51 doubles the period of an input signal, and a delay unit 52 delays the input signal by a predetermined time interval.
  • the output signal DLL_CLK_ 2 X shown in FIG. 4 indicates the output signal RCLK_DLL 2 X or FCLK DLL 2 X shown in FIG. 4 .
  • the input signal DLL_CLK shown in FIG. 5 indicates the input signal RCLK_DLL or FCLK_DLL shown in FIG. 4 .
  • Those skilled in the art variously realize a circuit of doubling the period of the input signal in addition to the example shown in FIG. 5 and employ the realized circuit for the circuit shown in FIG. 4 .
  • FIG. 6 illustrates an example of the read command generator described with reference to FIG. 1A .
  • the read command generator generates a read command signal by combining received external signals casb, we, ras, and csb.
  • the internal read command applied to the memory device is ‘RD_COMMAND’.
  • the read command determined by the external signal is delayed in the delay circuit 61 by a predetermined time interval and then is applied to the inside of the memory device by the switch element 62 .
  • the delay circuit 61 is controlled by the external clock signals CLK and CLKb, and the delay time point of the delay circuit 61 corresponds to 1tCK.
  • the tCK represents the period of the external clock signal CLK.
  • the read command generator disclosed in FIG. 6 directly delivers the read command applied from an external device to the inside of the memory device when CAS latency corresponds to an odd number.
  • the read command generator delays the read command by a time interval of 1tCK and then delivers the read command to the inside of the memory device.
  • the internal read command RD_COMMAND is delayed by a predetermined time interval of 1tCK and then outputted when CL corresponds to an even number, so that operation timing when CL corresponds to an even number can be identical to that when CL corresponds to an odd number.
  • a time point for data output can be controlled with respect to all cases where CAS latency corresponds to 2, 3, 4, 5, 6, 7, etc.
  • the conventional technique having generated internal counter signals with a time interval of 1tCK has a high probability of causing a superposition phenomenon between the internal counter signals.
  • the superposition between the internal counter signals causes an erroneous time point to output data.
  • internal counter signals are generated with a time interval of 2tCK, thereby enabling a stable data output operation even when the operation frequency of the memory device increases.
  • the effect of the present invention may be significantly represented, as the operation frequency of the memory device increases.
  • the present invention proposes a method for controlling a data output driver using control signals generated with a time interval of 2 clock, thereby enabling data output correspondingly to CAS latency even when the operation frequency of the memory device increases.

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US20090073787A1 (en) 2009-03-19
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US7466622B2 (en) 2008-12-16
TW200620322A (en) 2006-06-16
JP2006164491A (ja) 2006-06-22
KR100608372B1 (ko) 2006-08-08
US7649802B2 (en) 2010-01-19
KR20060062429A (ko) 2006-06-12
JP4854258B2 (ja) 2012-01-18
US20050265118A1 (en) 2005-12-01

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