TW200535950A - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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- TW200535950A TW200535950A TW094106390A TW94106390A TW200535950A TW 200535950 A TW200535950 A TW 200535950A TW 094106390 A TW094106390 A TW 094106390A TW 94106390 A TW94106390 A TW 94106390A TW 200535950 A TW200535950 A TW 200535950A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 193
- 238000009792 diffusion process Methods 0.000 claims abstract description 71
- 239000010410 layer Substances 0.000 claims description 135
- 239000010408 film Substances 0.000 claims description 69
- 239000000758 substrate Substances 0.000 claims description 50
- 239000002344 surface layer Substances 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 239000013039 cover film Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 7
- 241000283690 Bos taurus Species 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 150000001412 amines Chemical class 0.000 claims 1
- 229910052734 helium Inorganic materials 0.000 claims 1
- 239000001307 helium Substances 0.000 claims 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims 1
- 238000002161 passivation Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 230000009467 reduction Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- NIHNNTQXNPWCJQ-UHFFFAOYSA-N fluorene Chemical compound C1=CC=C2CC3=CC=CC=C3C2=C1 NIHNNTQXNPWCJQ-UHFFFAOYSA-N 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 241000251468 Actinopterygii Species 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 241000238631 Hexapoda Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 241001674048 Phthiraptera Species 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 125000005442 diisocyanate group Chemical group 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910001416 lithium ion Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
Description
200535950 九、發明說明： [發明所屬之技術領域] 本發明係有關於一種半導體裝置及其制 -種包含具有偏離結構（offset structure)':二::尤指 體之半導體裝置及其製造方法。 回电塵電晶 [先前技術] 結構之耐高電壓電晶體作為具有穩定的財 j及漏琶特性之電晶體係已為習知（例如第6圖，日本已 之編號為9-223 793之專利)。於此類 中，有沒極擴散層包括位於問電極側方之 “低雜質濃度區，，）及比低雜f、 （乂下稱為 作所低亦隹貝/辰度區的雜質濃度更高之 雜為“高雜質濃度區”）。此種電晶體係以例 ：的局部氧化)或使用STI(淺通道隔離)結構進 灯哀置隔 _ (device isolation)。 第二圖係顯示一橫斷面示意圖’係為具有補償裝置的 M0S笔日日體之半導體梦署么 牛广以置U由LOCOS進行裝置隔 〇弟@所不，半導體基板包括用於形成耐高電壓電 曰曰體20d之半導體基極】以及於其上方形成的第一導電型 井區擴散層2。於該井區擴散層2之表層上，形成了用於 裝置隔離之LOCOS氧化膜6a及6b。 第一‘電型源極擴散層u a形成於該井區擴散層2 中a ^為了與该L0C0S氧化膜6a相連。第二導電型汲極 &放f <!】b包括低雜質濃度區5a及高雜質濃度區5b。該 低雜質濃度區53係位於該源極擴散層】】a侧方（即該低雜 316835 5 200535950 質濃度區5a較該高雜質濃度區％1靠近該源極擴散層 11 a)及該LOCOS氧化膜6a下方。該低雜質濃度區&因其 具有如此之結構也可稱作“補償汲極擴散層”。 於該井區擴散層2中，且位於該源極㈣層山及該 汲極擴散I 間的區域係作為通道區(以下就稱為200535950 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor device and a manufacturing method thereof-a semiconductor device including an offset structure ': two :: especially a semiconductor device and a manufacturing method thereof. Recycling dust transistor [prior art] Structure of high-voltage-resistant transistor is known as a transistor system with stable properties and leakage characteristics (for example, Figure 6, Japanese patent No. 9-223 793) ). In this class, the electrode diffusion layer includes a "low impurity concentration region" located on the side of the interfacial electrode, and an impurity concentration greater than that of the low impurity f, (hereinafter referred to as the "low impurity" / "degree region"). High impurities are "high impurity concentration regions"). Examples of this type of transistor system are: local oxidation) or using STI (Shallow Channel Isolation) structure for lamp isolation. The second picture shows a The cross-section schematic diagram is the semiconductor dream department of the M0S pen solar system with a compensation device. Niu Guangyi sets the device to be installed by LOCOS. The younger brother @ 所 不, the semiconductor substrate includes a body for forming a high-voltage resistant battery. 20d semiconductor base] and a first conductive well region diffusion layer 2 formed thereon. On the surface layer of the well region diffusion layer 2, LOCOS oxide films 6a and 6b for device isolation are formed. First ' An electric type source diffusion layer ua is formed in the well area diffusion layer 2 a to connect with the L0C0S oxide film 6a. The second conductivity type drain &amp; f <!] B includes a low impurity concentration region 5a and high Impurity concentration region 5b. The low impurity concentration region 53 is located in the source diffusion layer]] a side ( The low impurity 316835 5 200535950 mass concentration region 5a is closer to the source diffusion layer 11 a) and below the LOCOS oxide film 6a than the high impurity concentration region% 1. The low impurity concentration region & It is called “compensated drain diffusion layer.” The area in the well area diffusion layer 2 located between the source ridge layer mountain and the drain diffusion I is used as the channel area (hereinafter referred to as “channel area”).
“通道區”）。第一導電型雜質層15形成為覆蓋該通道區 及該源極擴散層lla。於該通道區上方，形成閘絕緣膜8, 並且於該閘絕緣膜8上，形成閘電極9。 該雜質層15係為—臨限電壓（thresh〇id v〇ita㈣調整 =雜質層，用以調整該耐高電麗電晶體2Qd之臨限電壓。 猎由離子注人方式或其他方式將第__導電雜質導入該源極 擴散層11 a和該通道區中，廿 Ύ 亚猎由熱擴散該導入雜質，從 而形成該雜質層1 5。由於兮崎所恳〗ς〆 力…系喊貝層1 5係於該通道區中形 成，因此可以將高壓施加於 刀万…亥閘電極9或該汲極擴散層 11 b 〇 如I然而’具有上述結構之耐高電Μ電晶體2Gd存在-個 二：問題，因爲電流驅動性能很容易降低。“圖中箭 係為通道區側方之Locos氧化膜6b中 端二 如::部分所示，該 ;，與，雜質濃度…互重疊之部分㈣“重疊區 之導=_=與該低雜質濃度區w互間具有相反 的濃度會降:二產！促成導電之載體(car㈣ 可生黾阻（卩31-35出(：resistance)，並 316835 6 200535950 =:高電阻。這樣會降低該耐高電壓電晶體之電流驅動 為解決上述問題，日本已公開的 利提出-項技術，即給具有上述之^ 223793之專 「咖另一種雜質層。第7圖係==咖 體裳置之橫斷面示意圖。如第7圖所；：=、=半導 通道區具有第6圖所示之半導 "導版装置之 成且古命版通逼區相同之結構，並形 ，= = = :=型相同之高雜質濃度區 將鱼兮、及極nh方、^質層15形成之後形成，係 H及極擴放層llb具有相同 區並以熱處理擴散該雜質而形成。 4…该通道 於具有這結構之耐高電愿電晶體20e，該雜 诔質補償了該低雜質濃度區 、曰 擴展了空乏声60。之亦隹貝，亚於該重疊區30 之古…i 而，該汲極擴散層1lb或該閘電極9 之;軸可以得到保證，，因為該 星電日邮μ + 值達到—期望水準，使得該耐高電 '曰曰體施之電流驅動性能可以得到改善。 及該古，准所存在以下問題。當形成該雜質層15 以熱 得所期望之重疊區…广貝，辰編加以控制以獲 雜質濃度。另外，該：“ 6〇。但是」艮難以熱擴散控制該 重叠，造成該通道區^ 及5亥南雜質濃度區40相互 [發明内容] 表層‘刀之濃度難以控制。 316835 7 200535950 - 4=Γ::之缺點，本發明之主要目的係提供 ;::衣置，俾易於控制汲極擴散層之低雜質濃度區 :通逼區之雜質濃度，俾保證該汲極擴散層或該 ，高耐電壓，並抑制該電晶體電流驅動性能之降低程 又。本發明亦提供該半導體裝置之製造方法。 為達上述目的，本發明具有以下之功效。 發：ί第一方面係關於具有耐高電壓電晶體之半導 •:二〃半導體裝置包含具有第-導電型表層部分之半 =基板；形成於該半導體基板之第二導電㈣極擴散 丄方及第一導電型雜質層；並且對半導體基板 上方故有閘笔極及閘絕緣膜。該沒極擴 擴散層側方形成之第二導電型 枯方…亥源極 質濃度區之雜質濃度高之：；：!：：度區，及較該低雜 有用以#^-= ⑮度該半導體基板設 =，_vlceiS0latl01— 辰度&可以係形成在該絕緣膜下方之偏 • (offset drain diffusion fi]m) 〇 L 政層 及，=…體裝置之特徵之-係將該低雜質濃度區 及“貝區女置成可以防止雜質相互補償之位置 :° : V防止该雜質層之雜質補償該低雜質濃度區之雜 =因此，可以限制寄生電阻之產生，進而抑制電流離動 散Τ’降低。另外’可將高壓施加至該間電極及該汲極擴 為防止該低雜質濃度區及該雜質區相互 補償所安置之結構，即為該低雜質濃度區及該：質 3J6835 200535950 互分隔亦相互關聯之結構。於該低雜質濃度區及該雜質層 之間可能進一步設第二導電型邊界雜質層。 本發明之第二方面係關於具有上述結構之半導體裝置 製造方法。於該方法步驟中，首先，令第二導電型雜質導 入具有第一導電型表層部分之半導體基板中，從而於該半 導體基板中形成一低雜質濃度區。其次，於該半導體基板 中^成對用於裝置隔離（device isolation)之絕緣膜，這樣 其中之一對絕緣膜並可位於該低雜質濃度區上方。接著， 於形成於該低雜質濃度區上方之一對絕緣膜之一個之上方 形成一抗蝕圖案（resist pattern)，該抗蝕圖案也覆蓋了作為 通迢區的-部分。然後，使用抗钱圖案及絕緣膜作為罩膜 (mask)將第—導電型雜質導人半導體基板中，從而於、 導體基板中形成一雜質層並與該低雜質濃度區隔離。再 而’去除該抗姓圖案，並且於半導體基板中作為通道區的 區間形成閘絕緣膜。閘電極於該問絕緣膜上方形成。使用 該對絕緣膜及該閘電極作為罩膜而令第二導電型雜 半導體基板中，從而於該半導體基板中形成 散 汲極擴散層。 L成漕和 形成該閘電極步驟之後，向 Φ ^^ 個方向沿者該半導體 =之主表層作熱處理，使該雜質層之雜質及該低 度區生擴散運動直至這兩種雜質相互接觸為止。 “ J 供了另一種半導體裝置製造方法。於哕方 法步驟中，首先，令第二導電 二方 型表層部分之半導體基板，從而㈣半：:弟夕電類 、Θ牛蛉體基板中形成低 316835 200535950 雜質漠度區’·接著，形成一對用於半導體基 (deV1CeiS〇]^ 純雜質濃度區上·，然後，使用該對絕緣膜作為罩膜而令 弟一導電型雜質導入半導體基板中，從而形成、 =於該半導體基板上方形成—抗物，該抗㈣宰 在至二位於作為一通道區之_部分上方有—開口，該部 位於該低雜質濃度區側方。使用抗蝕 刀 Γ二導:半導體基板中一半導體 成 層（bGrder lmpurity Iayer)。 姓圖案。於作爲通道區之區域上形成—閉絕緣膜 :::ί:形成一開電極。最後’使用該對絕緣膜及該閉 :極作為罩膜令第二導電型雜質導入半導體基板中，從而 於该半導體基板中形成源極擴散層和沒極擴散層。 Λ用。玄衣方法，易於控制汲極擴散層之低雜質濃声 =:==:;雜質濃度。而包含具有極好的電流二 月b而、1^电壓電晶體之半導體裝置可以容易製成。 依據本發明，如上述，該沒極擴散層之低雜質濃度區 質層具有相反之導電型，將於通道區形成之低雜質 二又品及雜質區定位成可以防止雜質相互補償之位置。因 明提供半導體裝置，係包含允許將高電壓施加於 Μ1包極或該汲極擴散層並抑制該通道區之電流驅動性能 、牛低之耐回電壓電晶體，還提供半導體裝置之製造方法。 以下係藉由特定的具體實例結合附圖說明本發明 他優點與功效。 /、 316835 10 200535950 [實施方式] 實施例1 如第1圖所示，係用以說明本發明之半導體裝置及其 製造方法之實施例1之半導體裝置結構之橫斷面示意圖， 該半導體裝置包括具有偏離結構並藉由L〇c〇s形成裝置 隔喊的電晶體。如第1圖所示，具有第一導電型雜 質表層部分之半導體基板。於本圖中，半導體基板包括用 於形成耐高電壓電晶體20a之半導體基極丨以及於其上方 形成的第一導電型井區擴散層2。於該井區擴散層2之表 層上f，形成了用於裝置隔離之LOCOS氧化膜63及6b。 第二導電型源極擴散層lla形成於該井區擴散層2 中俾”。亥LOCOS氧化膜6a相連。第二導電型汲極# & 層括—低雜質濃度區5a及一高雜質濃度區外。該 低雜質濃度區5a係位於該源極擴散@ n"Aisle area"). The first conductivity type impurity layer 15 is formed to cover the channel region and the source diffusion layer 11a. A gate insulating film 8 is formed above the channel region, and a gate electrode 9 is formed on the gate insulating film 8. The impurity layer 15 is a threshold voltage adjustment (thresh〇id v〇ita㈣ adjustment = impurity layer, used to adjust the threshold voltage of the high-resistance Li-ion crystal 2Qd. _Conductive impurities are introduced into the source diffusion layer 11a and the channel region, and the sublayers diffuse the introduced impurities by heat, thereby forming the impurity layer 15. Due to the force of Xiqi, it is called the shell layer. 15 is formed in the channel region, so high voltage can be applied to the Daowan ... Hai gate electrode 9 or the drain diffusion layer 11 b 〇 As I However, 'high-voltage resistant transistor 2Gd with the above structure exists-one Second: The problem, because the current drive performance is easily reduced. "The arrow in the figure is the middle end of the Locos oxide film 6b on the side of the channel area. As shown in the :: part, this, and, the impurity concentration ... overlaps with each other. "The conductance of the overlap region = _ = and the low impurity concentration region w has opposite concentrations from each other and will decrease: secondary production! Promote conductive carriers (car㈣ can generate resistance (卩 31-35 出 (: resistance), and 316835 6 200535950 =: High resistance. This will reduce the current drive of this high voltage resistant transistor To solve the above problem, Japan has published a technology-namely, that is to give another special layer of coffee with the above-mentioned ^ 223793. Fig. 7 is a schematic cross-sectional view of = = body body. As shown in Fig. 7 So: =, = The semiconducting channel area has the structure of the semiconducting " guide plate device shown in Fig. 6 and the same structure of the ancient force version, and the shape is the same, = = =: = high impurities of the same type The concentration region is formed after the fish layer and the polar layer 15 are formed. The system H and the polarized layer 11b have the same region and are formed by diffusing the impurities by heat treatment. 4 ... The channel has a high resistance to this structure. The electric transistor 20e compensates for the low impurity concentration region and expands the empty noise 60. It is also lower than the overlapping region 30 ... i. Moreover, the drain diffusion layer 1lb or the The axis of the gate electrode 9 can be guaranteed, because the value of the μ + value of the star power daily mail reaches the desired level, so that the current driving performance of the high-voltage resistant system can be improved. The following problem. When the impurity layer 15 is formed to heat the desired overlap region ... Control to obtain the impurity concentration. In addition, this: "60." However, it is difficult to control the overlap by thermal diffusion, which causes the channel region ^ and the impurity concentration region 40 of the southern Hainan region 40 to each other. [Summary of the Invention] The concentration of the surface layer knife is difficult to control. 316835 7 200535950-4 = Γ :: Disadvantages, the main purpose of the present invention is to provide ::: clothing, 俾 easy to control the low impurity concentration region of the drain diffusion layer: the impurity concentration of the pass-through region, 俾 guarantee the drain The diffusion layer may have a high withstand voltage and suppress the reduction of the current driving performance of the transistor. The present invention also provides a method for manufacturing the semiconductor device. To achieve the above object, the present invention has the following effects. Hair: The first aspect is about a semiconductor with a high-voltage-resistant transistor. The second semiconductor device includes a half having a -conductivity type surface layer portion = a substrate; and a second conductive electrode diffusion formed on the semiconductor substrate. And a first conductive type impurity layer; and a gate pen electrode and a gate insulating film are formed above the semiconductor substrate. The second conductivity type dry square formed on the side of the non-polarized diffusion layer ... The impurity concentration in the source concentration region of the source is higher than ::! :: degree region, and # ^-= The semiconductor substrate is provided with a _vlceiS0latl01— Chen Du & can be formed under the insulating film • (offset drain diffusion fi] m) 〇L and the characteristics of the bulk device-is the low impurity The position of the concentration area and the "shell area" can prevent the mutual compensation of impurities: °: V prevents the impurities in the impurity layer from compensating for the impurities in the low impurity concentration area = Therefore, it can limit the generation of parasitic resistance, and then suppress the current dispersion Τ'reduced. In addition, the structure where the high voltage can be applied to the inter-electrode and the drain to prevent the low impurity concentration region and the impurity region from compensating each other is the low impurity concentration region and the: 3J6835 200535950 Structures separated from each other and related to each other. A second conductivity type boundary impurity layer may be further provided between the low impurity concentration region and the impurity layer. A second aspect of the present invention relates to a method for manufacturing a semiconductor device having the above structure. In this method step, first, a second conductivity type impurity is introduced into a semiconductor substrate having a first conductivity type surface layer portion, so that a low impurity concentration region is formed in the semiconductor substrate. Second, a pair is formed in the semiconductor substrate. An insulating film for device isolation, such that one pair of insulating films can be positioned over the low impurity concentration region. Next, it is formed over one of the pair of insulating films formed over the low impurity concentration region A resist pattern, which also covers the-portion which is the through-hole region. Then, the anti-conductivity pattern and the insulating film are used as a mask to introduce the first conductive type impurity into the semiconductor substrate. Thus, an impurity layer is formed in the conductive substrate and is isolated from the low impurity concentration region. Then, the anti-surname pattern is removed, and a gate insulating film is formed in the semiconductor substrate as a channel region. The gate electrode is insulated at this point. Formed over the film. Using the pair of insulating films and the gate electrode as a cover film, the second conductive type semiconductor semiconductor substrate is placed in the semiconductor substrate. After the step of forming the gate electrode and forming the gate electrode, heat treatment is performed to the main surface layer of the semiconductor = in Φ ^^ directions, so that the impurities in the impurity layer and the low-level region generate diffusion movement until These two impurities come into contact with each other. "J provides another method for manufacturing semiconductor devices. In the method step, first, the semiconductor substrate of the second conductive two-sided surface layer portion is formed, so as to form a half :: a low-level 316835 200535950 impurity impurity region is formed in a xixi type, θ bovine body substrate, and then, is formed A pair is used for semiconductor-based (deV1CeiS〇) ^ pure impurity concentration region. Then, the pair of insulating films are used as a cover film to introduce a conductive impurity into a semiconductor substrate, so as to be formed on the semiconductor substrate. —Resistant, which is located above the part that is a channel region—the opening is located at the side of the low impurity concentration region. Using a resist knifeΓ Conductor: A semiconductor layer in a semiconductor substrate ( bGrder lmpurity Iayer). Surname pattern. Formed on the area as the channel area-closed insulation film ::: ί: forming an open electrode. Finally 'use the pair of insulation films and the closed: electrode as a cover film to make the second conductive type Impurities are introduced into the semiconductor substrate, thereby forming a source diffusion layer and a non-polar diffusion layer in the semiconductor substrate. Λ for use. Xuan Yi method, easy to control the low impurity concentration of the drain diffusion layer =: == :; impurities And a semiconductor device including a voltage transistor with a good current b and a voltage of 1 ^ can be easily manufactured. According to the present invention, as described above, the low impurity concentration region of the non-polar diffusion layer has the opposite quality Conductive type, which locates the low impurity impurity formed in the channel region and the impurity region to prevent the mutual compensation of impurities. Yinming provides semiconductor devices that include a high voltage applied to the M1 envelope or the drain diffusion layer and Suppressing the current driving performance of the channel region, low back-voltage withstand voltage transistor, and manufacturing method of semiconductor device are provided below. The specific advantages and effects of the present invention will be described with specific examples and drawings. /, 316835 10 200535950 [Embodiment Mode] Example 1 is a schematic cross-sectional view of a semiconductor device structure of Example 1 for explaining a semiconductor device and a manufacturing method thereof according to Embodiment 1 as shown in FIG. A transistor formed by the device is formed by Locos. As shown in FIG. 1, a semiconductor substrate having a surface layer portion of a first conductivity type impurity. As shown in FIG. The semiconductor substrate includes a semiconductor base for forming a high-voltage-resistant transistor 20a and a first conductive well region diffusion layer 2 formed thereon. On the surface layer f of the well region diffusion layer 2, a layer for forming Device-isolated LOCOS oxide films 63 and 6b. A second conductivity type source diffusion layer 11a is formed in the well area diffusion layer 2 ". The LOCOS oxide film 6a is connected. The second conductivity type drain electrode & Outside the low impurity concentration region 5a and a high impurity concentration region. The low impurity concentration region 5a is located at the source diffusion @ n
LOCOS氧化膜6a下方曲 U gi m h “ 雜貝濃度區5a因具有如此之 、、ό構也可彳冉作 偽a# u 〇 偏硪/及極擴散層（offset draln dlffusi〇】] layer) 〇 雜貝層7係錯由蔣盘兮/江、曲— 棺田將與遠低濃度雜質區5&導 雜質，即第一導電型雜斯 ^ 守私尘相反之Under the LOCOS oxide film 6a, the curve U gi mh "The miscellaneous shell concentration region 5a has such a structure, and its structure can also be false a # u 〇 bias and / or an extreme diffusion layer (offset draln dlffusi〇]] layer) 〇 Layer 7 is wrong. Jiang Panxi / Jiang, Qu—The coffin field will be opposite to the impurity region 5 & conducting impurities, which is the first conductivity type.
入該源極擴散層lla和哕诵、#卩+ 凡八他万式V „ RB D玄通迢區中而形成。該雜質層7係 一 S品限笔塵調整雜暂 、 /、 • -t ,、 貝層（threshoId v〇】tage adJustma 卿，y ^調整㈣高電壓電晶艮: 麗。閘電極9形成於該通道 區之間夾設一問絕緣膜8。 万、閉包杬與逋迺 316835 200535950 本員例之半導體裝置與第6圖及第7圖所示之習知半 導體裝置不同，該雜質層7及該低雜質濃度區5a係定位成 可以防止雜貝相互補償之位置，即相互間有一個距離τ予 以Pw _。由於s玄雜質層7及該低雜質濃度區&採用了這樣 一個位置關係’ f知技術裏的重疊區3G之問題得以排除。 因此’該通道區側方之低雜質濃度區5a末端的寄生電「阻 產生問題可以得到解決。 • 由於設在該通道區之該雜質I 7’該臨限電壓可以被 调整至期望水準，而且該耐高電壓電晶體2〇a之電流驅動 性能可以得到改善。因為形成了該偏離汲極擴散層Γ言帝 壓便可轭加於該閘電極9或該汲極擴散層"b 道區僅僅形成該雜晳厗1 „ . 哀通 分之濃度。亦隹貝層7，所以便於控制該通道區表層部 第2 A至2E圖係為如第！圖所示之半導體裝置 步驟中形成的半導體基板及A 。 翁 也、断面不意圖。參閱 :至2ΕΘ，描述了本實施例1之半導體裝置之製造方 氧化顯示—狀態，係於該半導體基板上方形成一 ^ 和—氮切膜之狀態。由以下方式可以得到此社 構。於該ρ型半導許美才 ° ,2。接英：基極1之表層，形成該Ρ型井區擴散 層2 接者，於該Ρ型井區擴散声2之矣·β _丄 CVD( e月文層2之表層，猎由氧化或 =7 “沉積）過程順序沉積Si〇2(氧化石夕）膜And formed into the source diffusion layer 11a and 哕, # 卩 + 凡 八 他 万 式 V „RB D Xuantong 迢 area. The impurity layer 7 is a S-type pen-limited dust adjustment, /, •,-- t ,, shell layer (threshoId v0) tage adJustma, y ^ adjustment ㈣ high-voltage transistor: Li. Gate electrode 9 is formed between the channel region with an interposed insulating film 8. million, closure 杬 and 逋迺 316835 200535950 The semiconductor device of this example is different from the conventional semiconductor device shown in Figs. 6 and 7. The impurity layer 7 and the low impurity concentration region 5a are positioned to prevent the mutual compensation of impurities. There is a distance τ between each other to give Pw _. Since the s-based impurity layer 7 and the low impurity concentration region & adopt such a positional relationship, the problem of the overlapping region 3G in the known technology is eliminated. Therefore, 'the channel region side The problem of the parasitic resistance at the end of the low impurity concentration region 5a can be solved. • Because the impurity I 7 'provided in the channel region, the threshold voltage can be adjusted to the desired level, and the high voltage resistant transistor The current driving performance of 20a can be improved. In order to form the deviated drain diffusion layer, the pressure can be added to the gate electrode 9 or the drain diffusion layer " b. The channel region only forms the impurity 厗 1. Shell layer 7, so it is easy to control the surface area of the channel area. The 2A to 2E diagrams are the semiconductor substrate and A formed in the step of the semiconductor device as shown in the figure. Weng Ye, the cross section is not intended. See: To 2EΘ, The oxidation display state of the semiconductor device in this embodiment 1 is described, which is a state in which a nitrogen-cut film is formed on the semiconductor substrate. This structure can be obtained in the following manner. Xu Meicai °, 2. Connection: The surface layer of the base 1 to form the P-type well area diffusion layer 2. Then, 矣 · β 丄 CVD (e-texture layer 2 surface layer) is diffused in the P-type well area. SiO 2 (Stone Oxide) Films Deposited by Oxidation or = 7 "Deposition" Process
SiN(虱化矽）膜4。 弟2B圖顯示一狀態，係於該半導體基板上方形成用 J2 316835 200535950 以形：該低雜質濃度區5a之罩膜圖案之狀態。由以 此Γ構。該Sl〇2膜3及該siN膜4例如使用絲 :〇= 式餘刻法予以處·，而後形成開口， 要來威：:广6a及6b即於該開口形成。然後，為了保持 ^成錢極擴散層llb《―側之開口益覆蓋其他之開 乃匕加抗蝕劑’而形成抗蝕膜。經曝光和顯像處理該 抗姓膜，形成可生成期望形狀之圖案之抗姓圖案12。使用 =形成罩膜圖案之Sl〇2膜3、SlN膜4及抗姓圖案⑴ =型雜質離子（如H録）注人該井區擴散層2中。於 疋亥井區擴散層2上方形成該低雜質濃度區化。 第2C圖顯示一狀態，係於該井區擴散層2之表層形 ocos氧化膜6&及6b之狀態。藉由以下方式可以得 =結構。去除該抗姓圖案12。在職溫度下，熱處理 二成結構’因此使用_膜4作為抗氧化膜熱氧化該井 區擴散層2之表層，同時熱擴散該低雜f濃度@ 5a^ '雜質。從而，於該井區擴散層2之表層形成厚度大約達 :之L〇C〇S氧化膜63及6b，同時，該低雜質濃度區 m寻更深。經錢刻移除該叫膜3及該SlN膜4。 …第2D圖顯示-狀態，係於該半導體基板上方形成可 形成期望形狀的圖案之抗蝕圖案]3並於井區擴散層2中形 成該雜質層7之狀態。藉由以下方式可以得到此結構。該 ―圖案U於LOCOS氧化膜6b上方形成，俾覆蓋一部 分通運區。使用該抗！虫圖案13及該L〇c〇s氧化膜以作 為罩膜，將p型雜質離子（如硼、銘）注入該井區擴散層2 316835 ]3 .200535950 中。於該井區擴散層2上方形成該雜質層7，其位置與該 低雜^ )辰度區5 a相差一 T距離。 第2E圖顯示一狀態，係於該井區擴散層2中形成該 源極擴散層11a及該汲極擴散層llb，並於半導體基板上 方形成5亥閘纟巴緣膜8及該閘電極9之狀態。藉由以下方式 可以得到此結構。首先，去除該抗蝕圖案丨3。於該井區擴 月欠層2之表層於该LOCOS氧化膜6a及6b之間，藉由熱 修氧化或CVD過程沉積一 Si〇2膜。藉由CVD過程於該以〇2 朕上方沉積一多矽膜。使用光蝕刻法及乾式蝕刻法處理這 些膜，將每個膜生成一期望之圖案。便形成該閘絕緣膜8 及该問電極9。SiN (lice silicon) film 4. Figure 2B shows a state, which is formed on the semiconductor substrate in the shape of J2 316835 200535950: the state of the mask pattern of the low impurity concentration region 5a. Therefore Γ structure. The SlO2 film 3 and the siN film 4 are processed using, for example, a silk: 〇 = equation method, and then an opening is formed. It is formed in the openings 6a and 6b. Then, a resist film is formed in order to keep the coin diffusion layer 11b "the openings on one side are covered with the other openings, and a resist is added." The anti-surname film is processed by exposure and development to form an anti-surname pattern 12 which can generate a pattern of a desired shape. The S02 film 3, the SN film 4 and the anti-surname pattern ⑴, which form a mask film pattern, are injected into the well area diffusion layer 2 using a type impurity ion (such as H record). The low-impurity-concentration region is formed above the diffusion layer 2 in the Xihai well region. Fig. 2C shows a state, which is a state of the surface-type ocos oxide films 6 & and 6b of the diffusion layer 2 in the well area. The structure can be obtained by: Remove the anti-surname pattern 12. At the service temperature, the heat-treated binary structure 'therefore uses _film 4 as an anti-oxidation film to thermally oxidize the surface layer of the well area diffusion layer 2 while thermally diffusing the low impurity f concentration @ 5a ^' impurities. Therefore, the surface layer of the diffusion layer 2 in the well region is formed with LOCOS oxide films 63 and 6b having a thickness of about 100 Å, and the low impurity concentration region m is further deepened. The so-called film 3 and the SlN film 4 are removed by money engraving. ... Fig. 2D shows a state where a resist pattern is formed on the semiconductor substrate to form a desired shape] 3 and the impurity layer 7 is formed in the well region diffusion layer 2. This structure can be obtained in the following manner. The "pattern U" is formed above the LOCOS oxide film 6b, and the 俾 pattern covers a part of the transport area. Use this anti! The insect pattern 13 and the Locos oxide film are used as a cover film, and p-type impurity ions (such as boron and ming) are implanted into the well area diffusion layer 2 316835] 3.200535950. An impurity layer 7 is formed above the well region diffusion layer 2 and its position is a distance T away from the low impurity region 5a. FIG. 2E shows a state where the source diffusion layer 11a and the drain diffusion layer 11b are formed in the well area diffusion layer 2, and a gate electrode film 5 and a gate electrode 9 are formed on the semiconductor substrate. Of the state. This structure can be obtained in the following manner. First, the resist pattern 3 is removed. A surface layer of the underlayer 2 in the well area is deposited between the LOCOS oxide films 6a and 6b, and a SiO2 film is deposited by a thermal repair oxidation or CVD process. A polysilicon film is deposited over the 0 2 朕 through a CVD process. These films are processed using photo-etching and dry-etching to produce each film with a desired pattern. The gate insulating film 8 and the interrogation electrode 9 are formed.
、 使用該閘電極9及該LOCOS氧化膜6a和0D 作為罩膜，將N型雜質離子注人該井區擴散層2中，而形 成該高雜質濃度區5bA該源極擴散層na。從而，具有一 偏離結構之耐高電壓電晶體20a便形成。 所曲具有上述結構之耐高電壓電晶體20a之代表性表層雜 貝/辰度心、有·在邊井區擴散層2中，大約有3χ】〇]5源子/ 立方f分⑼⑽SW);於該低雜質濃度區5a中，大約有5 X 1 〇】6肩+ / ☆古八乂 ，、 方A刀；於該源極擴散層〗]a及該高雜質濃 t，大約有5x 1〇2°原子/立方公分；於該雜質層7 中，大：有】X】〇]7原子/立方公分。 Μ本實例之半導體裝置特徵之-係介於該雜質戶7及該 低雜質濃度區5 貝廣 a之間存在該距離丁，將於此加以详述。如 Θ不，列如，介於該低雜質濃度區5a及該雜質層7 14 316835 200535950 隹丁係大約小於或等於1//H]。因爲介於 區5a及該層7之 卜 舄彳丨於该 仏、一間存在之距離丁大約小於或等於， 所以运樣會有低的 ^ Ώ _ 笔壓，因而不可能引起一電阻增加。 另外，介於該雜暂Jg 7 n , 力 -區間，但並不:田 嘴濃度區&之間形成 ,_ .....於臨限電壓調整之雜質注入該區。田 匕’石亥低雜質濃度區5 a之p刑％ ^ 雜質不會相互間進^二，隹質及該雜質層7之n型 ，質濃度區5a末端之載卿貝曲戶大而抑制通道區側方之該低雜 流驅動性能之電晶體 ㈣’從而可獲得具有高電 可以：第3圖所示’該低雜質濃度區5a及於該雜質声7 可以相互接觸。通過以下方式可以得到圖3所干之=7 裝置。於如第2E _ 3所不之+導體 所不之步驟中，該雜質層7及該低雜 二-度區5a之雜質經由熱處理向同—個方向沿著，：：Using the gate electrode 9 and the LOCOS oxide films 6a and 0D as a cover film, N-type impurity ions are injected into the well region diffusion layer 2 to form the high impurity concentration region 5bA and the source diffusion layer na. Thus, a high-voltage-resistant transistor 20a having a deviation structure is formed. The representative surface layer of the high-voltage resistant transistor 20a with the above-mentioned structure is composed of miscellaneous shells / Chen Duxin, and in the diffusion layer 2 in the side-well area, there are approximately 3 ×] 〇] 5 source units / cubic f minus SW); In the low impurity concentration region 5a, there are approximately 5 X 1 〇] 6 shoulder + / ☆ ancient Hachiman, square A knife; in the source diffusion layer]] a and the high impurity concentration t, approximately 5x 1 〇2 ° atoms / cubic centimeter; in the impurity layer 7, large: Yes] X] 〇] 7 atoms / cubic centimeter. The characteristic of the semiconductor device of this example is that the distance D exists between the impurity household 7 and the low impurity concentration region 5 Beguang a, which will be described in detail here. If Θ is not, as shown below, the low impurity concentration region 5a and the impurity layer 7 14 316835 200535950 fluorene system is approximately less than or equal to 1 // H]. Because the distance D between the region 5a and the layer 7 is approximately less than or equal to 仏, there is a low ^ Ώ _ pen pressure, so it is impossible to cause an increase in resistance. In addition, between the miscellaneous temporary Jg 7 n, the force-interval, but not: the formation of the tianzui concentration region &, the impurities adjusted to the threshold voltage are injected into the region. Tianjian 'Shihai low impurity concentration area 5 a p% ^ Impurities will not enter each other ^ Second, the n-type and the n-type of the impurity layer 7, the load concentration at the end of the mass concentration area 5a is large and suppressed The transistor 低 with low low-current drive performance at the side of the channel region can obtain high electric power: As shown in FIG. 3, the low impurity concentration region 5a and the impurity sound 7 can be in contact with each other. In the following manner, the device of Fig. 3 = 7 can be obtained. In the step as described in 2E _3 and + Conductor, the impurities in the impurity layer 7 and the low-impurity two-degree region 5a follow the same direction through heat treatment ::
體基板之主表層擴散，從 + V r r 雜貝層7及該低雜皙、、曹疮 品a相互接觸。此結構可經由 埶、/又 度而實現。 田您万式才工制熱處理之程 於具有此結構之耐高電壓電晶體鳥中， 該低雜質濃度區5a及該雜質層7 , 在”方； 介八兮卩< η外既 間之工隙。因為如上述 "方“玄區5a及该層7之間之距離 位於該區狀臨限電㈣低的，因此電㈣^—’ ]]t上所述’ 7重疊該通道區及該源極擴散層 :。。而該雜質層7僅需於該通道區形 二 電壓調整雜質層。 卜局s°°丨民 實施例2 316835 15 200535950 於本實例中，半導體努η於^ t ^ 、且i了、包括設在該低雜質濃度區 5 a及$玄雜貝層7間之邊界雜暂思 l » .. i，丨滩貝層。本實例之半導體裝置有 很多與實施例1之半導體梦罢4 卞〒旦衣置相同之處，以下僅對不同之 處予以描述。 弟4圖係一谱斷面元音同 分θ 一 …，…· w圖，其頒示本發明半導體裝置 及其製，方法之實施例2之半導體裝置結構之橫斷面示意 圖。如第4圖所示，第二導雷 令电型邊界雜質層10設在該低雜 貝 >辰度區5a及該雜質層7之間。 第5A至5Ε@係為如第4圖所示之半導體裝置之 ㈣中形成的半導體基板及其元件之橫斷面示意圖。參閱 第5二至5Ε圖，描述了本實例2之半導體裝置之製造方 法。第5AS5C圖所示之步驟與本實施例】之第2八至％ 圖所示之步驟相同，因此將不予以描述。 弟5D圖顯示一狀態，係形成可生成期望形狀的圖案 之抗㈣t 14’並於井區擴散層2中形成該雜質層7及該 邊界雜質層1G之狀態。藉由以下方式可以得到此結構。首 使用該LOCOS氧化膜6a及6b作為罩膜，將N型雜 質離子(如磷、砷)注入該井區擴散層2中，而於該井區擴 散層2上方形成N型雜質層。介於該L〇c〇s氧化膜心及 b之間的n型竑貝層之一部分係為用於調整該臨限電壓 之雜質層7。 接著，施加抗蝕劑以覆蓋該合成結構之表層，從而形 成具有通道50之抗蝕圖案]4,該通道5〇係至少位於該低 雜質濃度區5a側方之通道區末端之上方。然後，使用該抗 316835 16 200535950 蝕圖案14及該LOCOS氧化膜6b作為一罩膜，注入一 p 型雜質離子，這樣該表層雜質濃度大約係1χ ι〇η原子/立 方公分。從而，形成了介於該低雜質濃度區化及該雜 7之間之邊界雜質層10。該邊界雜質層1〇重疊了該雜質^ 度區5a及該雜f層7。該邊界雜質層1G更適宜具有大約 小於或等於1 // m之寬度。 一如帛5E圖所示之步驟與第2E目所示之步驟相同，這 晨將不予以描述。參閱f 2E圖’通過執行如上所述之相 同處理方式，便形成具有偏離結構之耐高電壓電晶體I。 於包含具有上述結構之对高電壓電晶體2〇c之半導體 裝置中，儘管該雜質層7與該低雜質濃度區&相互重爲， 但是由於該邊界雜質層1〇，該低雜質濃度區^ : 度得以增加。因此，抑制該寄生電阻的產 氏’ 該臨限電壓。因為該邊 牛低了 之〜“上 、◎隹貝層10八有小於或等於1 // m 見：上；。之小’所以該通道區之嶋度易於控制。 5a及該雜ir/r界雜質層1〇係設於該低雜質濃度區 7及今… 重疊之區域。代替方案為，該雜質層 /及ό亥低雜質道庚f < 、 的，並且二:所述可能相互間係分開 空隙内。邊界雜質層]。可設在該…該層7之間之 別述之貫例，描述了具有偏離結構且Α τ 行裝置隔離之ΜΩς + ^ 稱且猎由L〇C〇S進 由如進”置二“體。本發明對具有偏離結構且藉 二丁衣置隔雄之M〇s電晶體仍然有效。The main surface layer of the body substrate diffuses, and the + V r r miscellaneous layer 7 and the low miscellaneous, septic a are in contact with each other. This structure can be implemented via 埶, / again. In the process of heat treatment by Tianyou Wanshi, in the high-voltage resistant transistor with this structure, the low impurity concentration region 5a and the impurity layer 7 are in a square shape. Work gap. Because the distance between the "Xuan area 5a" and "Layer 7" is located at the lower threshold voltage of the zone as described above, the voltage "7" on the above mentioned channel overlaps the channel area. And the source diffusion layer :. . The impurity layer 7 only needs to form a voltage adjustment impurity layer in the channel region. Example s °° 丨 Example 2 316835 15 200535950 In this example, the semiconductor device is at ^ t ^ and i, including the boundary between the low impurity concentration region 5 a and the $ 5 impurity layer 7 Miscellaneous thinking l ».. i, beach shell. The semiconductor device of this example has many similarities with the semiconductor device of the first embodiment, and only the differences will be described below. Figure 4 is a schematic cross-sectional view of a vowel with the same cross-section θ, ..., w, which shows a schematic cross-sectional view of the structure of a semiconductor device according to the second embodiment of the semiconductor device and its manufacturing method. As shown in Fig. 4, the second lightning-type electrical boundary impurity layer 10 is provided between the low impurity < > temperature region 5a and the impurity layer 7. 5A to 5E @ are schematic cross-sectional views of a semiconductor substrate and its components formed in the frame of the semiconductor device shown in FIG. 4. Referring to Figs. 52 to 5E, a method of manufacturing the semiconductor device of this example 2 is described. The steps shown in Fig. 5AS5C are the same as those shown in Figs. 28 to% of this embodiment, and therefore will not be described. The figure 5D shows a state where the anti-t 14 'which can generate a pattern of a desired shape is formed, and the impurity layer 7 and the boundary impurity layer 1G are formed in the well area diffusion layer 2. This structure can be obtained in the following manner. First, the LOCOS oxide films 6a and 6b are used as a cover film, and N-type impurity ions (such as phosphorus and arsenic) are implanted into the well area diffusion layer 2, and an N-type impurity layer is formed above the well area diffusion layer 2. A part of the n-type nuclei layer between the Locos oxide film core and b is an impurity layer 7 for adjusting the threshold voltage. Next, a resist is applied to cover the surface layer of the composite structure, thereby forming a resist pattern having a channel 50] 4, the channel 50 being located at least above the end of the channel region to the side of the low impurity concentration region 5a. Then, using the anti-316835 16 200535950 etch pattern 14 and the LOCOS oxide film 6b as a cover film, a p-type impurity ion is implanted, so that the impurity concentration of the surface layer is about 1 x ηηη / cm³. Thus, a boundary impurity layer 10 is formed between the low impurity concentration region and the impurities 7. The boundary impurity layer 10 overlaps the impurity region 5 a and the impurity f layer 7. The boundary impurity layer 1G more preferably has a width of approximately less than or equal to 1 // m. As shown in Figure 5E, the steps shown in item 2E are the same, and will not be described this morning. Referring to the f 2E diagram ', by performing the same processing as described above, a high-voltage-resistant transistor I having a deviation structure is formed. In a semiconductor device including a pair of high-voltage transistors 20c having the above-mentioned structure, although the impurity layer 7 and the low impurity concentration region & mutually overlap, the low impurity concentration region due to the boundary impurity layer 10 ^: The degree is increased. Therefore, the threshold voltage of the parasitic resistance is suppressed. Because the side cow is low ~ "up, ◎ 隹 shell layer 108 has less than or equal to 1 // m See: upper; ... is small, so the degree of the channel area is easy to control. 5a and the miscellaneous ir / r The boundary impurity layer 10 is provided in the low impurity concentration region 7 and the area where the ... overlaps. The alternative is that the impurity layer and / or low impurity channel G f < It is separated in the gap. The boundary impurity layer]. The other conventional examples that can be placed between the layers 7 describe the MΩς + ^ term with a deviating structure and A τ line device isolation and hunting by LOC. The S-in-Yin-Jin "set two" body. The present invention is still effective for Mos transistors that have a deviated structure and are separated by a diisocyanate.
刖述之實例，描述了 P型M0S電晶體。本發明對N 316835 ]7 200535950 型M〇S電晶體同樣實用。在N型MOS電晶體中，該半導 體基板之雜質表層部分係N型，該源極擴散層及該汲極擴 散層係P型。包含CMOS電晶體之耐高電壓電晶體可以以 如前所述之電晶體大量相同之方式建構。 本發明之半導體裝置具有抑制於該通道區上方之汲極 擴散層之一部分之寄生電阻的產生之功效，以維持該耐高 電壓電晶體之電流驅動性能之穩定性。因此，本發明用於 $例如包含具有偏離結構且以LOCOS或STI實現之耐高電 壓電晶體之半導體裝置及其製造方法中係實用的。 本發明已作詳細說明，但上述實施例僅例示性說明本 發明之原理及其功效，而非用於限制本發明。任何熟習此 項技藝之人士均可在不違背本發明之範疇下，對上述實施 例進行修飾與改變。 [圖式簡單說明] 第1圖係一橫斷面示意圖，其顯示本發明半導體裝置 •及其製造方法之實例1之半導體裝置結構之橫斷面示意 圖； 第2 A至2E圖係本發明半導體裝置及其製造方法之半 導體裝置製造流程示意圖； 第3圖係一橫斷面示意圖，其顯示本發明半導體裝置 及其製造方法之實例1之另一半導體裝置結構之橫斷面示 意圖； 第4圖係一橫斷面示意圖，其顯示本發明半導體裝置 及其製造方法之實例2之半導體裝置結構之橫斷面示意 316835 200535950 圖； 第5A至5E圖係第4圖所示之半導體裝置之製造流程 示意圖； 第6圖係一橫斷面示意圖，其顯示一習知半導體裝置 結構之橫斷面示意圖；以及 第7圖係一橫斷面示意圖，其顯示另一習知半導體裝 置結構之橫斷面示意圖。 k [主要元件符號說明] 1 半導體基極 2 井區擴散層 3 Si〇2膜 4 SiN膜 5a 低雜質濃度區 5b 、40 南雜質濃度區 6a、6b LOCOS氧乂匕月莫 7、 1 5雜質層 8 閘絕緣膜 9 閘電極 10 邊界雜質層 lli i 源極擴散層 lib 汲極擴散層 12 、13、14 抗蝕圖案 20a至 20e 耐高電壓電晶體 30 重疊區 60 空乏層 T 距離 31683$The described example describes a P-type MOS transistor. The present invention is also practical for N 316835] 7 200535950 MOS transistor. In the N-type MOS transistor, the impurity surface layer portion of the semiconductor substrate is N-type, and the source diffusion layer and the drain diffusion layer are P-type. High-voltage-resistant transistors including CMOS transistors can be constructed in much the same way as the transistors described above. The semiconductor device of the present invention has the effect of suppressing the generation of parasitic resistance in a part of the drain diffusion layer above the channel region, so as to maintain the stability of the current driving performance of the high-voltage-resistant transistor. Therefore, the present invention is practically used in, for example, a semiconductor device including a high-voltage resistant piezoelectric crystal having a deviated structure and realized by LOCOS or STI, and a method for manufacturing the same. The present invention has been described in detail, but the above-mentioned embodiments merely exemplify the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the scope of the present invention. [Brief Description of the Drawings] Figure 1 is a schematic cross-sectional view showing a semiconductor device structure of the semiconductor device of the present invention and its manufacturing method example 1; Figures 2 A to 2E are semiconductors of the present invention Schematic diagram of the semiconductor device manufacturing process of the device and its manufacturing method; FIG. 3 is a schematic cross-sectional view showing a schematic cross-sectional view of another semiconductor device structure of Example 1 of the semiconductor device and its manufacturing method of the present invention; It is a schematic cross-sectional view showing a schematic cross-sectional view of a semiconductor device structure of Example 2 of the semiconductor device and the manufacturing method of the present invention. 316835 200535950 Figures; Figures 5A to 5E are the manufacturing process of the semiconductor device shown in Figure 4 FIG. 6 is a schematic cross-sectional view showing a cross-sectional view of a conventional semiconductor device structure; and FIG. 7 is a cross-sectional view showing a cross-section of another conventional semiconductor device structure. schematic diagram. k [Description of main component symbols] 1 Semiconductor base 2 Well region diffusion layer 3 Si〇2 film 4 SiN film 5a Low impurity concentration region 5b, 40 South impurity concentration region 6a, 6b LOCOS oxygen oxide, 1, 5 Impurity Layer 8 Gate insulation film 9 Gate electrode 10 Boundary impurity layer lli i Source diffusion layer lib Drain diffusion layer 12, 13, 14 Resist patterns 20a to 20e High-voltage-resistant transistor 30 Overlapping area 60 Empty layer T Distance 31683 $
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| JP2004070784A JP4711636B2 (en) | 2004-03-12 | 2004-03-12 | Manufacturing method of semiconductor device |
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| US (1) | US7196393B2 (en) |
| JP (1) | JP4711636B2 (en) |
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| US8174071B2 (en) * | 2008-05-02 | 2012-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | High voltage LDMOS transistor |
| US8163621B2 (en) | 2008-06-06 | 2012-04-24 | Globalfoundries Singapore Pte. Ltd. | High performance LDMOS device having enhanced dielectric strain layer |
| JP4587003B2 (en) * | 2008-07-03 | 2010-11-24 | セイコーエプソン株式会社 | Semiconductor device |
| JP5437602B2 (en) * | 2008-07-29 | 2014-03-12 | セイコーインスツル株式会社 | Semiconductor device and manufacturing method thereof |
| JP2010067955A (en) * | 2008-08-13 | 2010-03-25 | Seiko Instruments Inc | Semiconductor device and method of manufacturing the same |
| JP5452146B2 (en) * | 2009-09-17 | 2014-03-26 | セイコーインスツル株式会社 | Semiconductor device |
| WO2011161748A1 (en) | 2010-06-21 | 2011-12-29 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method for manufacturing same |
| US11888062B2 (en) * | 2021-10-01 | 2024-01-30 | Globalfoundries U.S. Inc. | Extended-drain metal-oxide-semiconductor devices with a silicon-germanium layer beneath a portion of the gate |
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| JPS62101074A (en) * | 1985-10-28 | 1987-05-11 | Hitachi Ltd | Semiconductor device |
| JPH01123416A (en) * | 1987-11-06 | 1989-05-16 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH01264262A (en) * | 1988-04-15 | 1989-10-20 | Toshiba Corp | Mos type field-effect transistor |
| US5512769A (en) * | 1992-05-25 | 1996-04-30 | Matsushita Electronics Corporation | High breakdown voltage semiconductor device and method of fabricating the same |
| JPH06338616A (en) * | 1993-05-28 | 1994-12-06 | Sanyo Electric Co Ltd | Vertical mos device and manufacture thereof |
| JP3332114B2 (en) * | 1994-03-08 | 2002-10-07 | 株式会社東芝 | High breakdown voltage field effect transistor |
| JP3055424B2 (en) * | 1994-04-28 | 2000-06-26 | 株式会社デンソー | Method of manufacturing MIS type semiconductor device |
| JPH08236754A (en) * | 1995-02-22 | 1996-09-13 | Fuji Electric Co Ltd | P-channel type high breakdown strength mosfet |
| JPH0955502A (en) * | 1995-08-14 | 1997-02-25 | Sony Corp | Transistor and its manufacture |
| JPH09223793A (en) * | 1996-02-16 | 1997-08-26 | Sony Corp | Semiconductor device and its manufacture |
| JP2000252465A (en) * | 1999-03-03 | 2000-09-14 | Sony Corp | Semiconductor device and manufacture thereof |
| JP2001068560A (en) * | 1999-08-30 | 2001-03-16 | Sanyo Electric Co Ltd | Fabrication of semiconductor device and semiconductor device |
| JP3442009B2 (en) * | 1999-09-24 | 2003-09-02 | 松下電器産業株式会社 | Structure of high voltage MOS transistor |
| JP3350014B2 (en) * | 2000-01-31 | 2002-11-25 | 松下電器産業株式会社 | Semiconductor device |
| KR100386610B1 (en) * | 2000-05-01 | 2003-06-02 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing the same |
| JP2003060199A (en) * | 2001-08-10 | 2003-02-28 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
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| KR101084490B1 (en) | 2011-11-21 |
| JP4711636B2 (en) | 2011-06-29 |
| CN1667837A (en) | 2005-09-14 |
| US7196393B2 (en) | 2007-03-27 |
| US20050199962A1 (en) | 2005-09-15 |
| JP2005260055A (en) | 2005-09-22 |
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