TW200518319A - Semiconductor memory device and method of fabricating the same - Google Patents

Semiconductor memory device and method of fabricating the same

Info

Publication number
TW200518319A
TW200518319A TW093129201A TW93129201A TW200518319A TW 200518319 A TW200518319 A TW 200518319A TW 093129201 A TW093129201 A TW 093129201A TW 93129201 A TW93129201 A TW 93129201A TW 200518319 A TW200518319 A TW 200518319A
Authority
TW
Taiwan
Prior art keywords
trench
memory device
semiconductor memory
fabricating
same
Prior art date
Application number
TW093129201A
Other languages
English (en)
Other versions
TWI240407B (en
Inventor
Hajime Arai
Original Assignee
Renesas Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Tech Corp filed Critical Renesas Tech Corp
Publication of TW200518319A publication Critical patent/TW200518319A/zh
Application granted granted Critical
Publication of TWI240407B publication Critical patent/TWI240407B/zh

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923Programmable transistors with more than two possible different levels of programmation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
TW093129201A 2003-10-10 2004-09-27 Semiconductor memory device and method of fabricating the same TWI240407B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003352514A JP4334315B2 (ja) 2003-10-10 2003-10-10 半導体記憶装置の製造方法

Publications (2)

Publication Number Publication Date
TW200518319A true TW200518319A (en) 2005-06-01
TWI240407B TWI240407B (en) 2005-09-21

Family

ID=34419855

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093129201A TWI240407B (en) 2003-10-10 2004-09-27 Semiconductor memory device and method of fabricating the same

Country Status (4)

Country Link
US (1) US7138679B2 (zh)
JP (1) JP4334315B2 (zh)
KR (1) KR100702102B1 (zh)
TW (1) TWI240407B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070057318A1 (en) * 2005-09-15 2007-03-15 Lars Bach Semiconductor memory device and method of production
JP2008305942A (ja) * 2007-06-07 2008-12-18 Tokyo Electron Ltd 半導体メモリ装置およびその製造方法
JP5405737B2 (ja) * 2007-12-20 2014-02-05 スパンション エルエルシー 半導体装置およびその製造方法
CN113471285B (zh) * 2020-03-30 2022-08-02 长鑫存储技术有限公司 半导体结构及其制备方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5386132A (en) * 1992-11-02 1995-01-31 Wong; Chun C. D. Multimedia storage system with highly compact memory device
US5460988A (en) * 1994-04-25 1995-10-24 United Microelectronics Corporation Process for high density flash EPROM cell
US5554550A (en) * 1994-09-14 1996-09-10 United Microelectronics Corporation Method of fabricating electrically eraseable read only memory cell having a trench
US6093606A (en) 1998-03-05 2000-07-25 Taiwan Semiconductor Manufacturing Company Method of manufacture of vertical stacked gate flash memory device
JP3930256B2 (ja) 2001-02-07 2007-06-13 スパンション エルエルシー 半導体装置及びその製造方法
DE10129958B4 (de) * 2001-06-21 2006-07-13 Infineon Technologies Ag Speicherzellenanordnung und Herstellungsverfahren
US6486028B1 (en) * 2001-11-20 2002-11-26 Macronix International Co., Ltd. Method of fabricating a nitride read-only-memory cell vertical structure
DE10204868B4 (de) * 2002-02-06 2007-08-23 Infineon Technologies Ag Speicherzelle mit Grabenspeichertransistor und Oxid-Nitrid-Oxid-Dielektrikum
KR100487523B1 (ko) * 2002-04-15 2005-05-03 삼성전자주식회사 부유트랩형 비휘발성 메모리 소자 및 그 제조방법
US20040041214A1 (en) * 2002-08-29 2004-03-04 Prall Kirk D. One F2 memory cell, memory array, related devices and methods
US20030235076A1 (en) * 2002-06-21 2003-12-25 Micron Technology, Inc. Multistate NROM having a storage density much greater than 1 Bit per 1F2
CN100407427C (zh) * 2002-06-21 2008-07-30 微米技术股份有限公司 Nrom存储器元件,存储器阵列,相关装置和方法
JP4412903B2 (ja) 2002-06-24 2010-02-10 株式会社ルネサステクノロジ 半導体装置
DE10229065A1 (de) * 2002-06-28 2004-01-29 Infineon Technologies Ag Verfahren zur Herstellung eines NROM-Speicherzellenfeldes
TW583755B (en) * 2002-11-18 2004-04-11 Nanya Technology Corp Method for fabricating a vertical nitride read-only memory (NROM) cell
US7241654B2 (en) * 2003-12-17 2007-07-10 Micron Technology, Inc. Vertical NROM NAND flash memory array
KR100513751B1 (ko) * 2004-08-25 2005-09-13 현대엔지니어링 주식회사 친환경적인 하천법면 보호공 설치구조

Also Published As

Publication number Publication date
TWI240407B (en) 2005-09-21
JP4334315B2 (ja) 2009-09-30
KR20050035080A (ko) 2005-04-15
KR100702102B1 (ko) 2007-04-02
JP2005116964A (ja) 2005-04-28
US7138679B2 (en) 2006-11-21
US20050077565A1 (en) 2005-04-14

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees