TW200517835A - Cache memory and control method thereof - Google Patents

Cache memory and control method thereof

Info

Publication number
TW200517835A
TW200517835A TW093127737A TW93127737A TW200517835A TW 200517835 A TW200517835 A TW 200517835A TW 093127737 A TW093127737 A TW 093127737A TW 93127737 A TW93127737 A TW 93127737A TW 200517835 A TW200517835 A TW 200517835A
Authority
TW
Taiwan
Prior art keywords
cache memory
control register
control method
ways
control
Prior art date
Application number
TW093127737A
Other languages
English (en)
Inventor
Tetsuya Tanaka
Hazuki Okabayashi
Ryuta Nakanishi
Tokuzou Kiyohara
Takao Yamamoto
Keisuke Kaneko
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of TW200517835A publication Critical patent/TW200517835A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
TW093127737A 2003-11-12 2004-09-14 Cache memory and control method thereof TW200517835A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003382570 2003-11-12

Publications (1)

Publication Number Publication Date
TW200517835A true TW200517835A (en) 2005-06-01

Family

ID=34587259

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093127737A TW200517835A (en) 2003-11-12 2004-09-14 Cache memory and control method thereof

Country Status (7)

Country Link
US (1) US7502887B2 (zh)
EP (1) EP1684180A4 (zh)
JP (2) JP4044585B2 (zh)
KR (1) KR100813370B1 (zh)
CN (1) CN1879092B (zh)
TW (1) TW200517835A (zh)
WO (1) WO2005048112A1 (zh)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1686485A4 (en) * 2003-11-18 2008-10-29 Matsushita Electric Ind Co Ltd CACHE MEMORY AND ASSOCIATED CHECK
JP4753549B2 (ja) 2004-05-31 2011-08-24 パナソニック株式会社 キャッシュメモリおよびシステム
US7966511B2 (en) * 2004-07-27 2011-06-21 Intel Corporation Power management coordination in multi-core processors
US20070156992A1 (en) * 2005-12-30 2007-07-05 Intel Corporation Method and system for optimizing latency of dynamic memory sizing
US7664970B2 (en) * 2005-12-30 2010-02-16 Intel Corporation Method and apparatus for a zero voltage processor sleep state
US7263577B2 (en) * 2005-03-03 2007-08-28 Qualcomm Incorporated Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor state
US7818502B2 (en) 2005-03-31 2010-10-19 Semiconductor Energy Laboratory Co., Ltd. Selectively powering down tag or data memories in a cache based on overall cache hit rate and per set tag hit rate
CN101156139A (zh) * 2005-04-08 2008-04-02 松下电器产业株式会社 高速缓冲存储器
KR20070093452A (ko) 2005-04-08 2007-09-18 마쯔시다덴기산교 가부시키가이샤 캐시 메모리 시스템 및 그 제어 방법
US7647514B2 (en) * 2005-08-05 2010-01-12 Fujitsu Limited Reducing power consumption at a cache
US20070083783A1 (en) * 2005-08-05 2007-04-12 Toru Ishihara Reducing power consumption at a cache
TW200821831A (en) * 2005-12-21 2008-05-16 Nxp Bv Schedule based cache/memory power minimization technique
TW200746161A (en) * 2005-12-21 2007-12-16 Nxp Bv Power partitioning memory banks
US7516275B2 (en) * 2006-04-25 2009-04-07 International Business Machines Corporation Pseudo-LRU virtual counter for a locking cache
US8244980B2 (en) * 2006-06-21 2012-08-14 Intel Corporation Shared cache performance
US7861041B2 (en) * 2007-09-04 2010-12-28 Advanced Micro Devices, Inc. Second chance replacement mechanism for a highly associative cache memory of a processor
US7809980B2 (en) * 2007-12-06 2010-10-05 Jehoda Refaeli Error detector in a cache memory using configurable way redundancy
JP4635063B2 (ja) * 2008-03-11 2011-02-16 株式会社東芝 キャッシュメモリ制御回路及びプロセッサ
JP5040773B2 (ja) * 2008-03-31 2012-10-03 富士通株式会社 メモリバッファ割当装置およびプログラム
JP4767361B2 (ja) * 2008-03-31 2011-09-07 パナソニック株式会社 キャッシュメモリ装置、キャッシュメモリシステム、プロセッサシステム
CN102077172A (zh) * 2008-07-02 2011-05-25 Nxp股份有限公司 使用运行时间任务调度的多处理器电路
JP2010244435A (ja) * 2009-04-08 2010-10-28 Panasonic Corp キャッシュ制御装置及びキャッシュ制御方法
US8645629B2 (en) * 2009-09-16 2014-02-04 Intel Corporation Persistent cacheable high volume manufacturing (HVM) initialization code
JP5650441B2 (ja) * 2010-06-07 2015-01-07 キヤノン株式会社 演算装置、キャッシュ装置、その制御方法及びコンピュータプログラム
TW201220048A (en) * 2010-11-05 2012-05-16 Realtek Semiconductor Corp for enhancing access efficiency of cache memory
JP2012203560A (ja) * 2011-03-24 2012-10-22 Toshiba Corp キャッシュメモリおよびキャッシュシステム
WO2012169142A1 (en) 2011-06-09 2012-12-13 Semiconductor Energy Laboratory Co., Ltd. Cache memory and method for driving the same
JP6012263B2 (ja) 2011-06-09 2016-10-25 株式会社半導体エネルギー研究所 半導体記憶装置
CN102725741B (zh) * 2011-12-31 2014-11-05 华为技术有限公司 高速缓冲存储器控制方法、装置和系统
US9223709B1 (en) * 2012-03-06 2015-12-29 Marvell International Ltd. Thread-aware cache memory management
US9135182B2 (en) 2012-06-01 2015-09-15 Semiconductor Energy Laboratory Co., Ltd. Central processing unit and driving method thereof
US9400544B2 (en) 2013-04-02 2016-07-26 Apple Inc. Advanced fine-grained cache power management
US8984227B2 (en) * 2013-04-02 2015-03-17 Apple Inc. Advanced coarse-grained cache power management
US9396122B2 (en) 2013-04-19 2016-07-19 Apple Inc. Cache allocation scheme optimized for browsing applications
CN104346298B (zh) * 2013-08-06 2018-12-25 北京数码视讯软件技术发展有限公司 基于智能卡的数据处理方法、装置及智能卡
US10073787B2 (en) * 2016-04-18 2018-09-11 Via Alliance Semiconductor Co., Ltd. Dynamic powering of cache memory by ways within multiple set groups based on utilization trends
US10303612B2 (en) * 2016-12-30 2019-05-28 Intel Corporation Power and performance-efficient cache design for a memory encryption engine
US10783083B2 (en) 2018-02-12 2020-09-22 Stmicroelectronics (Beijing) Research & Development Co. Ltd Cache management device, system and method
CN112906332B (zh) * 2021-03-25 2022-08-23 山东高云半导体科技有限公司 Fpga设计的综合实现方法和装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4315312A (en) * 1979-12-19 1982-02-09 Ncr Corporation Cache memory having a variable data block size
JPH04100158A (ja) * 1990-08-18 1992-04-02 Pfu Ltd キャッシュ制御方式
JPH04137053A (ja) * 1990-09-28 1992-05-12 Nippon Telegr & Teleph Corp <Ntt> キャッシュメモリへのブロック登録制御方式
US5353425A (en) 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
JP3381079B2 (ja) 1993-03-16 2003-02-24 日本電信電話株式会社 キャッシュメモリを用いた排他制御システム
JPH08263370A (ja) * 1995-03-27 1996-10-11 Toshiba Microelectron Corp キャッシュメモリシステム
JP3348367B2 (ja) 1995-12-06 2002-11-20 富士通株式会社 多重アクセス方法および多重アクセスキャッシュメモリ装置
US6282505B1 (en) 1996-02-16 2001-08-28 Hitachi, Ltd. Multi-port memory and a data processor accessing the same
US6144924A (en) * 1996-05-20 2000-11-07 Crane Nuclear, Inc. Motor condition and performance analyzer
US5802568A (en) * 1996-06-06 1998-09-01 Sun Microsystems, Inc. Simplified least-recently-used entry replacement in associative cache memories and translation lookaside buffers
EP0856797B1 (en) * 1997-01-30 2003-05-21 STMicroelectronics Limited A cache system for concurrent processes
US6205519B1 (en) * 1998-05-27 2001-03-20 Hewlett Packard Company Cache management for a multi-threaded processor
US6349363B2 (en) * 1998-12-08 2002-02-19 Intel Corporation Multi-section cache with different attributes for each section
WO2002008911A1 (fr) * 2000-07-24 2002-01-31 Hitachi,Ltd Systeme de traitement de donnees
JP2002116956A (ja) 2000-10-06 2002-04-19 Nec Corp キャッシュ制御方法及びキャッシュ制御システム
JP3900025B2 (ja) 2002-06-24 2007-04-04 日本電気株式会社 共有キャッシュメモリのヒット判定制御方法及び共有キャッシュメモリのヒット判定制御方式

Also Published As

Publication number Publication date
KR100813370B1 (ko) 2008-03-12
JPWO2005048112A1 (ja) 2007-05-31
CN1879092A (zh) 2006-12-13
WO2005048112A1 (ja) 2005-05-26
EP1684180A1 (en) 2006-07-26
KR20060085677A (ko) 2006-07-27
US20070136530A1 (en) 2007-06-14
JP2007299423A (ja) 2007-11-15
JP4044585B2 (ja) 2008-02-06
EP1684180A4 (en) 2008-10-29
US7502887B2 (en) 2009-03-10
CN1879092B (zh) 2010-05-12
JP4098347B2 (ja) 2008-06-11

Similar Documents

Publication Publication Date Title
TW200517835A (en) Cache memory and control method thereof
TW200609730A (en) Information processing apparatus and information processing method
TW200500855A (en) Memory management in a data processing system
WO2007072367A3 (en) Memory with block-erasable locations
HK1104364A1 (en) A method and apparatus for reading film grain patterns in a raster order in film grain simulation
IL169265A0 (en) Page descriptors for prefetching and memory management
WO2010004242A3 (en) Data processing apparatus, for example using vector pointers
WO2002054230A3 (en) System and method for prefetching data into a cache based on miss distance
WO2009045884A3 (en) Address translation caching and i/o cache performance improvement in virtualized environments
DE60102017D1 (de) Räumungsfilter für adressenübersetzungspuffer
WO2008155815A1 (ja) 情報処理装置及びキャッシュ制御方法
GB2463828A (en) Technique for preserving cached information during low power mode
GB2430288A (en) Method and apparatus for run-ahead victim selection to reduce undesirable replacement behaviour in inclusive caches
EP1555611A3 (en) Microprocessor and apparatus for performing fast speculative pop operation from a stack memory cache
MX2009007948A (es) Metodo y aparato para fijar politicas para la memoria cache en un procesador.
TW200502954A (en) Cache integrity apparatus, systems, and methods
WO2008042494A3 (en) Data processing system having cache memory debugging support and method therefor
GB2377298A (en) Method for controlling cache system comprising direct-mapped cache and fully-associative buffer
CA2601779A1 (en) Global modified indicator to reduce power consumption on cache miss
TW200834322A (en) System and method for implementing an enhanced hover state with active prefetches
DE502006000801D1 (de) Ausfallsicheres System zum Verwalten von Client-Server-Kommunikation
ATE423345T1 (de) Prozessor mit verschiedenartigen steuerwerken für gemeinsam genutzte ressourcen
TW200746841A (en) Direct macroblock mode techniques for high performance hardware motion compensation
WO2001097041A3 (en) Compiler-based cache line optimization
DE602004025556D1 (de) Aufrechterhaltung der Cachespeicherkoherenz zum direkten Zugriff (DMA), Abschluss einer Aufgabe, zur Synchronisierung