WO2008155815A1 - 情報処理装置及びキャッシュ制御方法 - Google Patents

情報処理装置及びキャッシュ制御方法 Download PDF

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Publication number
WO2008155815A1
WO2008155815A1 PCT/JP2007/062286 JP2007062286W WO2008155815A1 WO 2008155815 A1 WO2008155815 A1 WO 2008155815A1 JP 2007062286 W JP2007062286 W JP 2007062286W WO 2008155815 A1 WO2008155815 A1 WO 2008155815A1
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WIPO (PCT)
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page
address
bit
access
byte area
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PCT/JP2007/062286
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English (en)
French (fr)
Inventor
Hideki Okawara
Iwao Yamazaki
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Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to CN2007800534219A priority Critical patent/CN101689144B/zh
Priority to KR1020097026126A priority patent/KR101032050B1/ko
Priority to JP2009520170A priority patent/JP4692678B2/ja
Priority to PCT/JP2007/062286 priority patent/WO2008155815A1/ja
Priority to EP07767160A priority patent/EP2159699A4/en
Publication of WO2008155815A1 publication Critical patent/WO2008155815A1/ja
Priority to US12/639,587 priority patent/US8225070B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)

Abstract

　 ６４ビットのアクセスアドレスの履歴を記録するキューの１つのエントリ２００に、１つのページアドレス２０１（ビット６３から２２）と、２つのページ内アドレス２０２，２０４（ビット２１から８）と、２つの４ビットからなる登録領域内アクセス履歴２０３，２０５を備える。登録領域内アクセス履歴２０３，２０５内の１つのビットは、一次キャッシュの登録単位である６４バイトの領域に対応し、その６４バイト領域へのアクセスがあったか否かを示す。ページアドレス２０１と２つのページ内アドレス２０２，２０４は、二次キャッシュの登録単位である２５６バイトの２つ分（５１２バイト）の領域に対応する。そして、ページアドレス２０１と２つのページ内アドレス２０２，２０４に対応する５１２バイトの領域の中心近傍に、最近のアクセスアドレスが位置するように、ページアドレス２０１と２つのページ内アドレス２０２，２０４を適宜更新する。
PCT/JP2007/062286 2007-06-19 2007-06-19 情報処理装置及びキャッシュ制御方法 WO2008155815A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CN2007800534219A CN101689144B (zh) 2007-06-19 2007-06-19 信息处理装置及其控制方法
KR1020097026126A KR101032050B1 (ko) 2007-06-19 2007-06-19 정보 처리 장치 및 캐시 제어 방법
JP2009520170A JP4692678B2 (ja) 2007-06-19 2007-06-19 情報処理装置
PCT/JP2007/062286 WO2008155815A1 (ja) 2007-06-19 2007-06-19 情報処理装置及びキャッシュ制御方法
EP07767160A EP2159699A4 (en) 2007-06-19 2007-06-19 INFORMATION PROCESSOR AND METHOD FOR CONTROLLING CACHE MEMORY
US12/639,587 US8225070B2 (en) 2007-06-19 2009-12-16 Information processing apparatus and cache memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062286 WO2008155815A1 (ja) 2007-06-19 2007-06-19 情報処理装置及びキャッシュ制御方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/639,587 Continuation US8225070B2 (en) 2007-06-19 2009-12-16 Information processing apparatus and cache memory control method

Publications (1)

Publication Number Publication Date
WO2008155815A1 true WO2008155815A1 (ja) 2008-12-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062286 WO2008155815A1 (ja) 2007-06-19 2007-06-19 情報処理装置及びキャッシュ制御方法

Country Status (6)

Country Link
US (1) US8225070B2 (ja)
EP (1) EP2159699A4 (ja)
JP (1) JP4692678B2 (ja)
KR (1) KR101032050B1 (ja)
CN (1) CN101689144B (ja)
WO (1) WO2008155815A1 (ja)

Cited By (7)

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JP2012079108A (ja) * 2010-10-01 2012-04-19 Fujitsu Semiconductor Ltd メモリアクセス判定回路、メモリアクセス判定方法、キャッシュ制御装置および電子機器
JP5229383B2 (ja) * 2009-03-30 2013-07-03 富士通株式会社 プリフェッチ要求回路
CN104615548A (zh) * 2010-03-29 2015-05-13 威盛电子股份有限公司 数据预取方法以及微处理器
JP2017045153A (ja) * 2015-08-24 2017-03-02 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US9720600B2 (en) 2013-05-23 2017-08-01 Fujitsu Limited Apparatus and method for transferring data between storages having different access speeds
JP2019164411A (ja) * 2018-03-19 2019-09-26 株式会社東芝 管理装置、情報処理装置、管理方法、およびプログラム
JP2019164497A (ja) * 2018-03-19 2019-09-26 株式会社東芝 管理装置、情報処理装置、管理方法、およびプログラム

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US8762649B2 (en) * 2010-03-29 2014-06-24 Via Technologies, Inc. Bounding box prefetcher
US8645631B2 (en) * 2010-03-29 2014-02-04 Via Technologies, Inc. Combined L2 cache and L1D cache prefetcher
US8719510B2 (en) * 2010-03-29 2014-05-06 Via Technologies, Inc. Bounding box prefetcher with reduced warm-up penalty on memory block crossings
US8812788B2 (en) * 2010-11-09 2014-08-19 Lsi Corporation Virtual cache window headers for long term access history
US9201794B2 (en) * 2011-05-20 2015-12-01 International Business Machines Corporation Dynamic hierarchical memory cache awareness within a storage system
US9792218B2 (en) * 2011-05-20 2017-10-17 Arris Enterprises Llc Data storage methods and apparatuses for reducing the number of writes to flash-based storage
KR20160122278A (ko) 2012-08-18 2016-10-21 퀄컴 테크놀로지스, 인크. 프리페칭을 갖는 변환 색인 버퍼
US9128854B1 (en) * 2012-09-28 2015-09-08 Emc Corporation System and method for data prediction
WO2014111984A1 (ja) 2013-01-17 2014-07-24 株式会社ソニー・コンピュータエンタテインメント 情報処理装置およびファイル管理方法
US9483406B2 (en) 2013-03-11 2016-11-01 Via Technologies, Inc. Communicating prefetchers that throttle one another
US9251083B2 (en) 2013-03-11 2016-02-02 Via Technologies, Inc. Communicating prefetchers in a microprocessor
US9542309B2 (en) * 2013-08-21 2017-01-10 Sandisk Technologies Llc Relocating data based on matching address sequences
JP2015088146A (ja) * 2013-11-01 2015-05-07 株式会社ソニー・コンピュータエンタテインメント 情報処理装置
US9946654B2 (en) * 2016-09-09 2018-04-17 Cray Inc. High-bandwidth prefetcher for high-bandwidth memory
CN106484334A (zh) * 2016-10-20 2017-03-08 郑州云海信息技术有限公司 一种释放预读资源的方法及装置
CN107340978B (zh) * 2017-07-18 2020-05-26 苏州浪潮智能科技有限公司 一种存储预读方法、装置及存储系统
US10901778B2 (en) 2018-09-27 2021-01-26 International Business Machines Corporation Prefetch chaining for optimizing data read-ahead for workflow and analytics
CN109446111B (zh) * 2018-10-15 2021-01-26 上海兆芯集成电路有限公司 存储器集成电路及其预取地址决定方法

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5229383B2 (ja) * 2009-03-30 2013-07-03 富士通株式会社 プリフェッチ要求回路
US8856498B2 (en) 2009-03-30 2014-10-07 Fujitsu Limited Prefetch request circuit
CN104615548A (zh) * 2010-03-29 2015-05-13 威盛电子股份有限公司 数据预取方法以及微处理器
CN104615548B (zh) * 2010-03-29 2018-08-31 威盛电子股份有限公司 数据预取方法以及微处理器
JP2012079108A (ja) * 2010-10-01 2012-04-19 Fujitsu Semiconductor Ltd メモリアクセス判定回路、メモリアクセス判定方法、キャッシュ制御装置および電子機器
US9720600B2 (en) 2013-05-23 2017-08-01 Fujitsu Limited Apparatus and method for transferring data between storages having different access speeds
JP2017045153A (ja) * 2015-08-24 2017-03-02 富士通株式会社 演算処理装置及び演算処理装置の制御方法
JP2019164411A (ja) * 2018-03-19 2019-09-26 株式会社東芝 管理装置、情報処理装置、管理方法、およびプログラム
JP2019164497A (ja) * 2018-03-19 2019-09-26 株式会社東芝 管理装置、情報処理装置、管理方法、およびプログラム

Also Published As

Publication number Publication date
CN101689144B (zh) 2013-07-24
KR20100009635A (ko) 2010-01-28
JP4692678B2 (ja) 2011-06-01
CN101689144A (zh) 2010-03-31
KR101032050B1 (ko) 2011-05-02
US8225070B2 (en) 2012-07-17
EP2159699A4 (en) 2011-04-06
JPWO2008155815A1 (ja) 2010-08-26
EP2159699A1 (en) 2010-03-03
US20100095070A1 (en) 2010-04-15

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