TW200516711A - Method of forming metal line in semiconductor device - Google Patents
Method of forming metal line in semiconductor deviceInfo
- Publication number
- TW200516711A TW200516711A TW093119264A TW93119264A TW200516711A TW 200516711 A TW200516711 A TW 200516711A TW 093119264 A TW093119264 A TW 093119264A TW 93119264 A TW93119264 A TW 93119264A TW 200516711 A TW200516711 A TW 200516711A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- thin film
- metal line
- film
- forming metal
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 4
- 239000002184 metal Substances 0.000 title abstract 3
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 239000010409 thin film Substances 0.000 abstract 3
- 239000013078 crystal Substances 0.000 abstract 2
- 239000010408 film Substances 0.000 abstract 2
- 239000002245 particle Substances 0.000 abstract 2
- 230000004888 barrier function Effects 0.000 abstract 1
- 230000009977 dual effect Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0080034A KR100538633B1 (ko) | 2003-11-13 | 2003-11-13 | 반도체 소자의 금속 배선 형성 방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200516711A true TW200516711A (en) | 2005-05-16 |
Family
ID=34270772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093119264A TW200516711A (en) | 2003-11-13 | 2004-06-30 | Method of forming metal line in semiconductor device |
Country Status (5)
Country | Link |
---|---|
US (1) | US6869871B1 (zh) |
JP (1) | JP2005150690A (zh) |
KR (1) | KR100538633B1 (zh) |
CN (1) | CN1617322A (zh) |
TW (1) | TW200516711A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI392025B (zh) * | 2007-02-27 | 2013-04-01 | Ulvac Inc | 半導體裝置之製造方法及半導體裝置之製造裝置 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100564801B1 (ko) | 2003-12-30 | 2006-03-28 | 동부아남반도체 주식회사 | 반도체 제조 방법 |
KR100538444B1 (ko) * | 2003-12-31 | 2005-12-22 | 동부아남반도체 주식회사 | 비아 홀 및 트렌치 형성 방법 |
JP2006165115A (ja) * | 2004-12-03 | 2006-06-22 | Toshiba Corp | 半導体装置 |
US7287325B2 (en) * | 2005-05-10 | 2007-10-30 | International Business Machines Corporation | Method of forming interconnect structure or interconnect and via structures using post chemical mechanical polishing |
JP2010087094A (ja) * | 2008-09-30 | 2010-04-15 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
US8349724B2 (en) * | 2008-12-31 | 2013-01-08 | Applied Materials, Inc. | Method for improving electromigration lifetime of copper interconnection by extended post anneal |
EP2779224A3 (en) * | 2013-03-15 | 2014-12-31 | Applied Materials, Inc. | Methods for producing interconnects in semiconductor devices |
CN105336670B (zh) * | 2014-07-14 | 2018-07-10 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US10354969B2 (en) * | 2017-07-31 | 2019-07-16 | Advanced Semiconductor Engineering, Inc. | Substrate structure, semiconductor package including the same, and method for manufacturing the same |
US10390440B1 (en) * | 2018-02-01 | 2019-08-20 | Nxp B.V. | Solderless inter-component joints |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6184121B1 (en) * | 1997-07-10 | 2001-02-06 | International Business Machines Corporation | Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same |
US6303498B1 (en) * | 1999-08-20 | 2001-10-16 | Taiwan Semiconductor Manufacturing Company | Method for preventing seed layer oxidation for high aspect gap fill |
US6395632B1 (en) * | 2000-08-31 | 2002-05-28 | Micron Technology, Inc. | Etch stop in damascene interconnect structure and method of making |
-
2003
- 2003-11-13 KR KR10-2003-0080034A patent/KR100538633B1/ko not_active IP Right Cessation
- 2003-12-23 US US10/744,494 patent/US6869871B1/en not_active Expired - Fee Related
-
2004
- 2004-06-30 TW TW093119264A patent/TW200516711A/zh unknown
- 2004-08-10 CN CNA2004100565658A patent/CN1617322A/zh active Pending
- 2004-08-11 JP JP2004234089A patent/JP2005150690A/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI392025B (zh) * | 2007-02-27 | 2013-04-01 | Ulvac Inc | 半導體裝置之製造方法及半導體裝置之製造裝置 |
Also Published As
Publication number | Publication date |
---|---|
KR100538633B1 (ko) | 2005-12-22 |
JP2005150690A (ja) | 2005-06-09 |
CN1617322A (zh) | 2005-05-18 |
US6869871B1 (en) | 2005-03-22 |
KR20050046056A (ko) | 2005-05-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200701397A (en) | Selective copper alloy interconnections in semiconductor devices and methods of forming the same | |
TW200516711A (en) | Method of forming metal line in semiconductor device | |
TW200511493A (en) | Method for forming a dielectric barrier in an integrated circuit structure, interconnect structure and semiconductor device and methods for making the same | |
TWI256677B (en) | Barrier material and process for Cu interconnect | |
TW200514488A (en) | Method for fabricating a double-sided wiring glass substrate | |
WO2004053947A3 (en) | Titanium silicon nitride (tisin) barrier layer for copper diffusion | |
EP1376686A3 (en) | Method of plugging through-holes in silicon substrate | |
CN103125013A (zh) | 用于在穿孔中选择性沉积钨的系统和方法 | |
TW200607017A (en) | A method and apparatus for reducing aspect ratio dependent etching in time division multiplexed etch processes | |
WO2007084982A8 (en) | Dual-damascene process to fabricate thick wire structure | |
TW200729399A (en) | A structure for a semiconductor device and a method of manufacturing the same | |
TW200725707A (en) | Method for forming titanium silicide upon a semiconductor device with lower source/drain sheet resistance | |
TW200711038A (en) | Method of forming a semiconductor device having a diffusion barrier stack and structure thereof | |
TW200515534A (en) | Improved chemical planarization performance for copper/low-k interconnect structures | |
TW200638510A (en) | Method for fabricating semiconductor device with metal line | |
EP2202791A3 (en) | Semiconductor device having deep through vias | |
TW200618289A (en) | Integrated circuit and method for manufacturing | |
TW200503121A (en) | Interconnect structures incorporating low-k dielectric barrier films | |
JP2007150301A5 (zh) | ||
TW200631149A (en) | Method of forming metal line in semiconductor device | |
TWI256088B (en) | Method of forming different silicide portions on different silicon-containing regions in a semiconductor device | |
TW200612487A (en) | Method of providing contact via to a surface | |
TW200419778A (en) | Semiconductor device including interconnection and capacitor, and method of manufacturing the same | |
TW200504911A (en) | Methods of controlling properties and characteristics of a gate insulation layer based upon electrical test data, and system for performing same | |
TW200516712A (en) | Method for forming metal line in semiconductor device |