TW200513827A - Method and apparatus for fine tuning clock signals of an integrated circuit - Google Patents
Method and apparatus for fine tuning clock signals of an integrated circuitInfo
- Publication number
- TW200513827A TW200513827A TW093121987A TW93121987A TW200513827A TW 200513827 A TW200513827 A TW 200513827A TW 093121987 A TW093121987 A TW 093121987A TW 93121987 A TW93121987 A TW 93121987A TW 200513827 A TW200513827 A TW 200513827A
- Authority
- TW
- Taiwan
- Prior art keywords
- skew
- values
- programmable
- static
- external interface
- Prior art date
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
An IC including skew-programmable clock buffers, fixed skew logic, an external interface and a skew controller. Each skew-programmable clock buffer receives a distributed clock signal and provides a corresponding local clock signal having a programmed skew. The fixed skew logic enables permanent programming of static skew values and the external interface enables programming of dynamic skew values. The skew controller selects between the static and dynamic skew values and programs the skew-programmable clock buffers based on selected skew values. In one embodiment, the skew controller is operative to detect a skew over-ride command upon reset of the IC and to select between the static and dynamic skew values based on the skew over-ride command. The programmable memory may be integrated on the IC or externally coupled via the external interface. The fixed skew logic is implemented as any type of permanent programmable block, such as laser-blown ftises, and EPROM, etc.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/682,352 US7124314B2 (en) | 2002-11-05 | 2003-10-09 | Method and apparatus for fine tuning clock signals of an integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200513827A true TW200513827A (en) | 2005-04-16 |
TWI261160B TWI261160B (en) | 2006-09-01 |
Family
ID=34590634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW93121987A TWI261160B (en) | 2003-10-09 | 2004-07-23 | Method and apparatus for fine tuning clock signals of an integrated circuit |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN1322673C (en) |
TW (1) | TWI261160B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8706467B2 (en) * | 2008-04-02 | 2014-04-22 | Synopsys, Inc. | Compact circuit-simulation output |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6477659B1 (en) * | 1999-09-03 | 2002-11-05 | Sun Microsystems, Inc. | Measuring timing margins in digital systems by varying a programmable clock skew |
TW494293B (en) * | 2000-12-22 | 2002-07-11 | Faraday Tech Corp | Clock signal network structure |
US6693473B2 (en) * | 2002-03-19 | 2004-02-17 | Infineon Technologies Ag | Delay lock loop having a variable voltage regulator |
-
2004
- 2004-07-23 TW TW93121987A patent/TWI261160B/en active
- 2004-08-16 CN CNB2004100561002A patent/CN1322673C/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN1322673C (en) | 2007-06-20 |
TWI261160B (en) | 2006-09-01 |
CN1581691A (en) | 2005-02-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100593271B1 (en) | Semiconductor integrated circuit device | |
US6353561B1 (en) | Semiconductor integrated circuit and method for controlling the same | |
US4929854A (en) | Clock circuit having a clocked output buffer | |
KR100801032B1 (en) | Input circuit of a non-volatile semiconductor memory device and method of inputting data of the same | |
TW200608390A (en) | Charge pump clock for non-volatile memories and algorithm for adjusting the charge pump clock signal | |
EP1530219A3 (en) | Semiconductor memory with synchronous and asynchronous mode selection during power-down | |
EP1050882A3 (en) | Methods for operating semiconductor memory devices and semiconductor memory devices | |
TWI266478B (en) | Input buffer circuit | |
TW346540B (en) | Test method of integrated circuit devices by using a dual edge clock technique | |
US20180197588A1 (en) | Processing system and method for data strobe signal | |
TW359831B (en) | Buffer control circuit and method for semiconductor memory device with power saving function | |
TW200513827A (en) | Method and apparatus for fine tuning clock signals of an integrated circuit | |
ATE401608T1 (en) | DATA PROCESSING DEVICE | |
US7242636B2 (en) | Clock control circuit and semiconductor memory device including the same and input operation method of semiconductor memory device | |
US20040120178A1 (en) | Test mode circuit of semiconductor memory device | |
EP0952549A3 (en) | Edge transition detection disable circuit to alter memory device operating characteristics | |
WO2003005046A3 (en) | Apparatus with a test interface | |
EP0527015A2 (en) | Low power signaling using output impedance delay | |
KR101633860B1 (en) | Delay-locked loop circuit and semiconductor device having the same | |
KR100408893B1 (en) | Input buffer circuit having the characteristic of low power consumtion and quick responce | |
KR100897277B1 (en) | Delay Circuit of Semiconductor Memory Apparatus | |
US20070258299A1 (en) | Semiconductor memory apparatus having noise generating block and method of testing the same | |
KR20130139643A (en) | Integrated circuit and operation method of the same | |
KR100699811B1 (en) | DDR SDRAM semiconductor device generating internal reference voltage for testing the same | |
KR100546187B1 (en) | Buffer control device and method for semiconductor memory devices |