KR100408893B1 - Input buffer circuit having the characteristic of low power consumtion and quick responce - Google Patents

Abstract

An input buffer circuit with low power consumption and fast response speed is posted. The input buffer circuit of the present invention includes a high speed buffer unit, a low power buffer unit, and a control unit. The high speed buffer unit may buffer the mode control signal at a relatively high speed and at a high power. The low power buffer unit may buffer the mode control signal at a relatively low speed and low power. The control unit controls to enable the high speed buffer unit and disable the low power buffer unit in the predetermined first operation mode, and to enable the low power buffer unit and disable the high speed buffer unit in the predetermined second operation mode. According to the input buffer circuit of the present invention, the high speed buffer unit is enabled in the normal operation mode requiring high speed response, and the low power buffer unit is enabled in the power down mode requiring low power. Therefore, the input buffer circuit of the present invention can have a fast response speed in the normal operation mode while minimizing the power consumption in the power down mode.

Description

INPUT BUFFER CIRCUIT HAVING THE CHARACTERISTIC OF LOW POWER CONSUMTION AND QUICK RESPONCE}

The present invention relates to an input buffer circuit, and more particularly, to an input buffer circuit for buffering a mode control signal of a synchronous semiconductor memory device.

The synchronous semiconductor memory device receives signals input from an external system mainly at a TTL level voltage. However, internal circuits of a synchronous semiconductor memory device are designed to be suitable for signals having a voltage at the CMOS level. Therefore, in the synchronous semiconductor memory device, circuits for converting signals input at a TTL level voltage into signals at a CMOS level are embedded. One such circuit is an input buffer circuit.

Meanwhile, the direction of research on the synchronous semiconductor memory device is focused on minimizing current consumption and improving operation speed. One of the findings for minimizing current consumption is the adoption of a power down mode. The selection of the power down mode or the normal operation mode of the synchronous semiconductor memory device is performed by the mode control signal XCKE provided from an external system. Therefore, in the power down mode, most of the internal circuits except the input buffer circuit for the mode control signal XCKE are disabled.

One of the input buffer circuits buffering the conventional mode control signal is implemented with a differential amplifier. The input buffer circuit implemented with the differential amplifier has a fast response speed by amplifying the voltage level of the input signal compared to the reference voltage. However, input buffer circuits implemented with differential amplifiers have the disadvantage that significant power consumption occurs even in power down mode.

Another type of input buffer circuit for buffering conventional mode control signals is implemented with CMOS amplifiers. The input buffer implemented by the CMOS amplifier is a circuit that buffers an input signal based on an inverter and has a relatively low power consumption. However, an input buffer implemented with CMOS amplifiers has a disadvantage in that the response speed is slow.

One of the conventional input buffer circuits for buffering the mode control signal is a response in the normal operation mode if the input buffer circuit for buffering the mode control signal is implemented in the CMOS amplification type in order to reduce power consumption. It has the disadvantage of being slow.

Accordingly, an object of the present invention is to provide an input buffer circuit having a low power consumption in a power down mode and a fast response speed in a normal operation mode.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram schematically illustrating an input buffer circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating in detail the high speed buffer unit of FIG. 1.

FIG. 3 is a diagram illustrating in detail the low power buffer unit of FIG. 1.

4 is a diagram illustrating in detail the internal signal generator of FIG. 1.

5 is a diagram specifically illustrating a control signal generator of FIG. 1.

6 is a timing diagram of main signals of FIG. 1.

One aspect of the present invention for achieving the above technical problem relates to an input buffer circuit for buffering the mode control signal for controlling the operation mode of the synchronous semiconductor memory device in synchronization with a predetermined clock signal. The input buffer circuit of the present invention includes a high speed buffer unit, a low power buffer unit, and a control unit. The high speed buffer unit may buffer the mode control signal at a relatively high speed and at a high power. The low power buffer unit may buffer the mode control signal at a relatively low speed and low power. The control unit controls to enable the high speed buffer unit and disable the low power buffer unit in a predetermined first operation mode, and to enable the low power buffer unit and disable the high speed buffer unit in a predetermined second operation mode. To control.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

1 is a block diagram schematically illustrating an input buffer circuit according to an embodiment of the present invention. Referring to FIG. 1, an input buffer circuit of the present invention includes a high speed buffer unit 100, a low power buffer unit 200, and a controller 300.

The fast buffer unit 100 is enabled in the first operation mode of the synchronous semiconductor memory device to buffer the mode control signal XCKE input from an external system. Specifically, when the synchronous semiconductor memory device switches from the first operation mode to the second operation mode, the mode control signal XCKE input from an external system is buffered by the high speed buffer unit 100. The mode control signal XCKE buffered by the high speed buffer unit 100 is provided to the control unit 300 as a high speed buffering signal PCKE.

The low power buffer unit 200 is enabled in the second operation mode of the synchronous semiconductor memory device to buffer the mode control signal XCKE input from an external system. Specifically, when the synchronous semiconductor memory device switches from the second operation mode to the first operation mode, the mode control signal XCKE input from an external system is buffered by the high speed buffer unit 100. The mode control signal XCKE buffered by the low power buffer unit 200 is provided to the controller 300 as a low power buffering signal TCKE.

The high speed buffer unit 100 buffers the mode control signal XCKE at a relatively high speed and high power consumption compared to the low power buffer unit 200. The low power buffer unit 200 buffers the mode control signal XCKE at a relatively low speed and low power consumption compared to the high speed buffer unit 100.

In the present specification, a normal operation mode requiring high speed response may be the first operation mode, and a power down mode requiring minimization of current consumption may be the second operation mode. Therefore, in the normal operation mode, the fast buffer unit 100 is enabled to buffer the mode control signal PCKE at a high operating speed. In addition, in the power down mode, the low power buffer unit 200 is enabled to buffer the mode control signal TCKE while minimizing the consumption of current.

In the present specification, when the mode control signal XCKE transitions from "low" to "high", it is assumed that the synchronous semiconductor memory device enters the first operation mode. Further, when the mode control signal XCKE transitions from "high" to "low", it is assumed that the synchronous semiconductor memory device enters the second operation mode.

The controller 300 receives the high speed buffering signal PCKE and the low power buffering signal TCKE to generate a high speed control signal BUFB and a low power control signal CBUF. The fast control signal BUFB controls the fast buffer unit 100 to be enabled in the normal operation mode and to be disabled in the power down mode. The low power control signal CBUF controls the low power buffer 200 to be enabled in the power down mode and disabled in the normal operation mode.

Preferably, the controller 300 includes an internal signal generator 400 and a control signal generator 500. The internal signal generator 400 logically operates the high speed buffering signal PCKE and the low power buffering signal TCKE to generate an internal control signal ICKE and a delay control signal DCKE. The internal control signal ICKE is a signal tracked to have the same phase as the mode control signal XCKE. The delay control signal DCKE is a signal for delaying the internal control signal ICKE by a half cycle or more of the clock signal CLKA. In the present specification, the clock signal CLKA is a signal in which an external clock signal provided from the system is buffered. A synchronous semiconductor memory device to which the input buffer circuit of the present invention is applied is synchronized with the clock signal CLKA.

The control signal generator 500 generates the high speed control signal BUFB and the low power control signal CBUF in response to the delay control signal DCKE.

FIG. 2 is a diagram illustrating the high speed buffer unit 100 of FIG. 1 in detail. Referring to FIG. 2, the fast buffer unit 100 includes a differential amplifier 110. The differential amplifier 110 is implemented with two PMOS transistors 111 and 113 and two NMOS transistors 115 and 117. The PMOS transistors 111 and 113 and the NMOS transistors 115 and 117 have the same electrical characteristics. When the PMOS transistor 120 is in the "turn-on" state, that is, when the fast control signal BUFB is activated "low", the differential amplifier 110 is enabled. The enabled differential amplifier 110 senses the voltage of the mode control signal XCKE with respect to a predetermined reference voltage VREF and inverts and amplifies it.

The signal inverted and amplified by the differential amplifier 110 is inverted by the inverter 140 and output as the high speed buffering signal PCKE. Therefore, when the mode control signal XCKE transitions from "high" to "low" when the high speed control signal BUFB is activated to "low", the high speed buffering signal PCKE is also Transition from "high" to "low" (see t1 in FIG. 6).

On the other hand, in the state where the fast control signal BUFB is deactivated to "high", the differential amplifier 110 is disabled. In this case, the PMOS transistor 130 is "turned on", and the input signal N139 of the inverter 140 is held "high". In addition, the fast buffering signal PCKE is held at " low ", as shown in FIG.

The high speed buffer unit 100 has the advantage of buffering the mode control signal XCKE at high speed in the enabled state, and minimizing current consumption in the disabled state.

3 is a view illustrating the low power buffer unit 200 of FIG. 1 in detail. Referring to FIG. 3, the low power buffer unit 200 includes a CMOS amplifier 210. The CMOS amplifier 110 is enabled when the low power control signal CBUF is activated to " high. &Quot; At this time, when the mode control signal XCKE transitions from "low" to "high", the low power buffering signal TCKE also transitions from "low" to "high" (see t2 in FIG. 6).

On the other hand, in the state where the low power control signal CBUF is deactivated to "low", the CMOS amplifier 210 is disabled. At this time, the PMOS transistor 230 is "turned on", and the input signal N239 of the inverter 240 is held "high". The low power buffering signal TCKE is held at " low ", as shown in FIG.

The high speed buffer unit 100 illustrated in FIG. 3 has an advantage of buffering the mode control signal XCKE while consuming relatively little current in the enabled state.

4 is a diagram illustrating in detail the internal signal generator 400 of FIG. 1. Referring to FIG. 4, the internal signal generator 400 includes a logic sum gate 410 and a delay means 430. The OR gate 410 generates an internal control signal ICKE by ORing the high speed buffering signal PCKE and the low power buffering signal TCKE. Thus, the internal control signal ICKE has approximately the same phase as the mode control signal XCKE. The delay means 430 delays the internal control signal ICKE to generate the delay control signal DCKE. Preferably, the delay means 430 is implemented as a flip-flop controlled by the clock signal CLKA. The delay means 430 holds the internal control signal ICKE, which is input when the clock signal CLKA is "low". When the transition from the "low" to "high" and the "low" transition of the clock signal CLKA occurs, the internal control signal ICKE held by the delay means 430 is the delay control signal. Output to (DCKE). Accordingly, the delay control signal DCKE is delayed by at least 1/2 of the clock signal CLKA with respect to the internal control signal ICKE.

The delay time secured by the delay means 430 may normally complete the normal operation in progress even if a power down mode entry command is input from an external system.

5 is a diagram illustrating in detail the control signal generator 500 of FIG. 1. Referring to FIG. 5, the control signal generator 500 is implemented by a delay means 510, a first calculation means 520, and a second calculation means 530.

The delay means 510 delays the delay control signal DCKE by a predetermined time. The first calculating means 520 inverts the delay control signal DCKE and the output signal N512 of the delay means 510 to generate the low power control signal CBUF. When the internal control signal ICKE is "low", the second calculating means 520 is enabled. In this case, the second calculating means 530 inverts the OR of the delay control signal DCKE and the output signal N512 of the delay means 510 to generate the fast control signal BUFB.

Therefore, when transitioning from "high" to "low" of the delay control signal DCKE, the low power control signal CBUF is directly transitioned from "low" to "high", whereas the high speed control signal BUFB ) Transitions from "low" to "high" after a delay of d1 (see t3 in FIG. 6).

On the other hand, when the transition from the "low" to "high" of the delay control signal DCKE, the fast control signal BUFB immediately transitions from "high" to "low", while the low power control signal CBUF ) Transitions from "high" to "low" after a delay of d2 (see t4 in FIG. 6). In the present embodiment, the low power control signal CBUF and the high speed control signal BUFB are both active during the delay times of d1 and d2. That is, during the delay times of d1 and d2, both the fast buffer unit 100 (see FIG. 1) and the low power buffer unit 200 (see FIG. 1) are enabled. This is to prevent the high speed buffer unit 100 and the low power buffer unit 200 from being disabled at the same time.

In this embodiment, the high speed control signal BUFB serves as a signal for controlling the high speed buffer unit 100, and the low power control signal CBUF serves as a signal for controlling the low power buffer unit 200. . In addition, the fast control signal BUFB may serve as a control signal for minimizing current consumption by disabling an input buffer circuit and an internal circuit for an external input signal in a power down mode.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the input buffer circuit of the present invention as described above, the high speed buffer unit is enabled in the normal operation mode requiring high speed response, and the low power buffer unit is enabled in the power down mode requiring low power. Therefore, the input buffer circuit of the present invention can have a fast response speed in the normal operation mode while minimizing the power consumption in the power down mode.

Claims (9)

An input buffer circuit for buffering a mode control signal for controlling an operation mode of a synchronous semiconductor memory device in synchronization with a predetermined clock signal, A high speed buffer unit capable of buffering the mode control signal at a relatively high speed and at a high power; A low power buffer unit capable of buffering the mode control signal at a relatively low speed and low power; And A control unit to enable the high speed buffer unit and to disable the low power buffer unit in a predetermined first operation mode, and to control the low power buffer unit to be enabled and to disable the high speed buffer unit in a predetermined second operation mode. Input buffer circuit comprising a. The method of claim 1, wherein the control unit Providing a high speed control signal for controlling the high speed buffer unit and a low power control signal for controlling the low power buffer unit, The high speed control signal is Activated in response to the mode control signal buffered by the low power buffer unit to enable the high speed buffer unit, and in response to the mode control signal buffered by the high speed buffer unit to disable the low power buffer unit Is deactivated by The low power control signal is Activated in response to the mode control signal buffered by the high speed buffer portion to enable the low power buffer portion, and responsive to the mode control signal buffered by the low power buffer portion to disable the high speed buffer portion Being deactivated Input buffer circuit, characterized in that. The method of claim 2, wherein the control unit An internal control signal that tracks the mode control signal by performing a logical operation on an output signal of the high speed buffer unit and an output signal of the low power response unit, and a delay delayed by at least 1/2 cycle of the clock signal with respect to the internal control signal. The internal signal generator for generating a control signal; And And a control signal generator for generating the high speed control signal and the low power control signal in response to the delay control signal. The method of claim 3, wherein the control signal generator Delay means for delaying the delay control signal to a predetermined time; First calculating means for performing a logic operation on the delay control signal and an output signal of the delay unit to provide the low power control signal; And And second calculating means for performing a logic operation on the delay control signal and the output signal of the delay unit to provide the high speed control signal. The method according to any one of claims 1 to 4, The high speed response unit and the low power response unit An input buffer circuit comprising a section which is simultaneously enabled. The method of claim 5, The first operation mode is a normal operation mode, and the second operation mode is a power down mode. The method according to any one of claims 1 to 4, The fast response unit And a differential amplifier for sensing and amplifying a voltage of the mode control signal with respect to a predetermined reference voltage. The low power response unit And a CMOS amplifier which amplifies the mode control signal to a CMOS level. The method of claim 7, wherein The first operation mode is a normal operation mode, and the second operation mode is a power down mode. The method according to any one of claims 1 to 4, The first operation mode is a normal operation mode, and the second operation mode is a power down mode.