EP1050882A3 - Methods for operating semiconductor memory devices and semiconductor memory devices - Google Patents

Methods for operating semiconductor memory devices and semiconductor memory devices Download PDF

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Publication number
EP1050882A3
EP1050882A3 EP00303775A EP00303775A EP1050882A3 EP 1050882 A3 EP1050882 A3 EP 1050882A3 EP 00303775 A EP00303775 A EP 00303775A EP 00303775 A EP00303775 A EP 00303775A EP 1050882 A3 EP1050882 A3 EP 1050882A3
Authority
EP
European Patent Office
Prior art keywords
semiconductor memory
command
memory devices
operating modes
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP00303775A
Other languages
German (de)
French (fr)
Other versions
EP1050882B1 (en
EP1050882A2 (en
Inventor
Takaaki c/o Fujitsu Limited Suzuki
Toshiya C/O Fujitsu Limited Uchida
Kotoku c/o Fujitsu Limited Sato
Yoshimasa c/o Fujitsu Limited Yagishita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP1050882A2 publication Critical patent/EP1050882A2/en
Publication of EP1050882A3 publication Critical patent/EP1050882A3/en
Application granted granted Critical
Publication of EP1050882B1 publication Critical patent/EP1050882B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

A semiconductor memory device having a plurality of operating modes for controlling an internal circuit comprises a command controlling circuit which accepts signals supplied to predetermined terminals as commands at a plurality of times. The number of operating modes is sequentially narrowed down based on each command and the internal circuit is controlled according to the narrowed operating modes. One such command controlling circuit comprises a plurality of accepting circuits (94a). Each of the accepting circuits (94a) respectively accepts signals, supplied at a plurality of times, each time. In other words, in accordance with the timing of the signal supplement, a different accepting circuit (94a) is respectively operated and the internal circuit is controlled. Accordingly, a command controlling circuit may be readily designed even in the semiconductor memory device having a complicated command combination. Consequently, it is able to facilitate the verification of the design.
Since the information necessary for determining an operating mode is accepted at a plurality of times, the number of terminals necessary for inputting commands can be reduced. In particular, in case of inputting commands at a dedicated terminal, its input pads, input circuits, or the like are no longer be required so that the chip size can be reduced. The reduction is accomplished by reducing the number of terminals, which gives limits to the package size.
EP00303775A 1999-05-07 2000-05-05 Methods for operating semiconductor memory devices and semiconductor memory devices Expired - Lifetime EP1050882B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP12671699 1999-05-07
JP12671699 1999-05-07
JP2000076045A JP4034923B2 (en) 1999-05-07 2000-03-17 Semiconductor memory device operation control method and semiconductor memory device
JP2000076045 2000-03-17

Publications (3)

Publication Number Publication Date
EP1050882A2 EP1050882A2 (en) 2000-11-08
EP1050882A3 true EP1050882A3 (en) 2001-08-16
EP1050882B1 EP1050882B1 (en) 2003-07-30

Family

ID=26462846

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00303775A Expired - Lifetime EP1050882B1 (en) 1999-05-07 2000-05-05 Methods for operating semiconductor memory devices and semiconductor memory devices

Country Status (6)

Country Link
US (1) US6629224B1 (en)
EP (1) EP1050882B1 (en)
JP (1) JP4034923B2 (en)
KR (1) KR100617334B1 (en)
DE (1) DE60004124T2 (en)
TW (1) TW454337B (en)

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JP2001035153A (en) * 1999-07-23 2001-02-09 Fujitsu Ltd Semiconductor memory
JP2002245778A (en) * 2001-02-16 2002-08-30 Fujitsu Ltd Semiconductor device
US7003643B1 (en) 2001-04-16 2006-02-21 Micron Technology, Inc. Burst counter controller and method in a memory device operable in a 2-bit prefetch mode
JP2002352576A (en) * 2001-05-24 2002-12-06 Nec Corp Semiconductor memory
JP2002358231A (en) * 2001-05-31 2002-12-13 Fujitsu Ltd Memory control system
JP4731730B2 (en) 2001-06-04 2011-07-27 ルネサスエレクトロニクス株式会社 Semiconductor memory device
JP4768163B2 (en) * 2001-08-03 2011-09-07 富士通セミコンダクター株式会社 Semiconductor memory
DE10392198T5 (en) * 2002-01-11 2005-01-13 Hynix Semiconductor Inc., Ichon Increase a refresh period in a semiconductor memory device
US6671212B2 (en) 2002-02-08 2003-12-30 Ati Technologies Inc. Method and apparatus for data inversion in memory device
US6728150B2 (en) 2002-02-11 2004-04-27 Micron Technology, Inc. Method and apparatus for supplementary command bus
JP3792602B2 (en) * 2002-05-29 2006-07-05 エルピーダメモリ株式会社 Semiconductor memory device
JP4077295B2 (en) * 2002-10-23 2008-04-16 株式会社東芝 Synchronous semiconductor memory device and operation method thereof
US7042777B2 (en) * 2004-01-28 2006-05-09 Infineon Technologies Ag Memory device with non-variable write latency
JP4615896B2 (en) 2004-05-25 2011-01-19 富士通セミコンダクター株式会社 Semiconductor memory device and control method of semiconductor memory device
JP2006059046A (en) 2004-08-19 2006-03-02 Nec Computertechno Ltd Memory control method and memory control circuit
CN101111900B (en) * 2005-01-27 2011-02-16 斯班逊有限公司 Semi-conductor device, address assignment method
US7757061B2 (en) 2005-05-03 2010-07-13 Micron Technology, Inc. System and method for decoding commands based on command signals and operating state
KR100732241B1 (en) * 2006-01-24 2007-06-27 삼성전자주식회사 Semiconductor memory device having high test efficiency, test system having the same, and method of testing the same
US8296497B2 (en) * 2006-03-14 2012-10-23 Stmicroelectronics Pvt. Ltd. Self-updating memory controller
JP4267006B2 (en) * 2006-07-24 2009-05-27 エルピーダメモリ株式会社 Semiconductor memory device
JP2008097663A (en) 2006-10-06 2008-04-24 Sony Corp Semiconductor storage device
US7405992B2 (en) * 2006-10-25 2008-07-29 Qimonda North America Corp. Method and apparatus for communicating command and address signals
KR100909965B1 (en) * 2007-05-23 2009-07-29 삼성전자주식회사 A semiconductor memory system having a volatile memory and a nonvolatile memory sharing a bus and a method of controlling the operation of the nonvolatile memory
US20090021995A1 (en) * 2007-07-19 2009-01-22 Jong-Hoon Oh Early Write Method and Apparatus
JP2012038377A (en) * 2010-08-05 2012-02-23 Elpida Memory Inc Semiconductor device and its test method
US8775725B2 (en) * 2010-12-06 2014-07-08 Intel Corporation Memory device refresh commands on the fly
KR101198141B1 (en) * 2010-12-21 2012-11-12 에스케이하이닉스 주식회사 Semiconductor memory apparatus
KR101915073B1 (en) 2011-12-20 2018-11-06 인텔 코포레이션 Dynamic partial power down of memory-side cache in a 2-level memory hierarchy
KR101980162B1 (en) * 2012-06-28 2019-08-28 에스케이하이닉스 주식회사 Memrory
US9740485B2 (en) * 2012-10-26 2017-08-22 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies
US9754648B2 (en) 2012-10-26 2017-09-05 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies
US9734097B2 (en) * 2013-03-15 2017-08-15 Micron Technology, Inc. Apparatuses and methods for variable latency memory operations
US9727493B2 (en) 2013-08-14 2017-08-08 Micron Technology, Inc. Apparatuses and methods for providing data to a configurable storage area
US9563565B2 (en) 2013-08-14 2017-02-07 Micron Technology, Inc. Apparatuses and methods for providing data from a buffer
US10365835B2 (en) 2014-05-28 2019-07-30 Micron Technology, Inc. Apparatuses and methods for performing write count threshold wear leveling operations
KR102561095B1 (en) * 2016-04-14 2023-07-31 에스케이하이닉스 주식회사 Operating method of semiconductor memory device

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US5053990A (en) * 1988-02-17 1991-10-01 Intel Corporation Program/erase selection for flash memory
US5749086A (en) * 1996-02-29 1998-05-05 Micron Technology, Inc. Simplified clocked DRAM with a fast command input

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JP4017248B2 (en) * 1998-04-10 2007-12-05 株式会社日立製作所 Semiconductor device
JP4226686B2 (en) * 1998-05-07 2009-02-18 株式会社東芝 Semiconductor memory system, semiconductor memory access control method, and semiconductor memory
US6295231B1 (en) * 1998-07-17 2001-09-25 Kabushiki Kaisha Toshiba High-speed cycle clock-synchronous memory device
JP4260247B2 (en) * 1998-09-02 2009-04-30 富士通マイクロエレクトロニクス株式会社 Semiconductor memory device
JP2000100156A (en) * 1998-09-25 2000-04-07 Fujitsu Ltd Cell information writing method for semiconductor storage device and semiconductor storage device
JP2000163961A (en) * 1998-11-26 2000-06-16 Mitsubishi Electric Corp Synchronous semiconductor integrated circuit device
JP2002093167A (en) * 2000-09-08 2002-03-29 Mitsubishi Electric Corp Semiconductor memory

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US5053990A (en) * 1988-02-17 1991-10-01 Intel Corporation Program/erase selection for flash memory
US5749086A (en) * 1996-02-29 1998-05-05 Micron Technology, Inc. Simplified clocked DRAM with a fast command input

Also Published As

Publication number Publication date
TW454337B (en) 2001-09-11
JP2001028190A (en) 2001-01-30
DE60004124T2 (en) 2004-03-11
KR20010020813A (en) 2001-03-15
EP1050882B1 (en) 2003-07-30
KR100617334B1 (en) 2006-08-31
JP4034923B2 (en) 2008-01-16
EP1050882A2 (en) 2000-11-08
US6629224B1 (en) 2003-09-30
DE60004124D1 (en) 2003-09-04

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