1261160 九、發明說明： 【相關申請案】 [0001] 本申明案優先權之申請係根據美國專利申請， 號·· 10/682,352，申請曰：10/09/2003。 、^ [0002] 本申請案與下列同在申請中之中華民國專利申請 關，其申凊日與本案相同，且具有相同的申請人與發明人。” 台灣申請 申請曰 DOCKET 案號 NUMBER 92135105 92/12/12 CNTR.2120 1 i ] ίΜΛΜ —-—___ 積體電路時序除錯裝置及 方法 microprocessor1261160 IX. INSTRUCTIONS: [RELATED APPLICATIONS] [0001] The priority application of this application is based on U.S. Patent Application Serial No. 10/682,352, filed on Sep. 10/2003. ^ [0002] This application is the same as the following application in the Republic of China patent application, the application date is the same as the case, and has the same applicant and inventor. "Application for Taiwan 曰 DOCKET Case No. NUMBER 92135105 92/12/12 CNTR.2120 1 i ] ίΜΛΜ —-—___ Integrated circuit timing debugging device and method
VARIATION rus AND method 【發明所屬之技術領域】VARIATION rus AND method [Technical field to which the invention pertains]
[0003]本發明係有積體電路上連續邏輯方塊的時脈， 尤指在除錯及測試程序中完成關鍵時序路徑㈣ieal timing P 的方法及裝置。 識及分析之後，驗微微永遠財控辦脈職之她差桃㈣ 【先前技術】 [0004]顏電路設計者已使用模擬及/或測試，來辨識、區 及分析晶片上的時序問題，通常這些問題在最好的情況下，二 使晶片不能以目標時脈速絲執行，但最壞哺糊會導致晶 1261160 在大量製造之前，必須進行設計上的修改。通常，合利用a片上 每個邏輯方塊内的暫存賴輯，將資料傳送職續^邏輯^段， 或從先前的邏輯階段接收資料。若-邏輯方塊峨行之運算具有 相關之關鍵延遲路徑(critical delay path)，且其使得有效資料^特 定時脈速度下，直到下-賴隨之時脈邊緣產线，、才被送至 用來栓鎖(latch)此資料之下一邏輯階段，則此時會發生 題。而若該邏輯方塊將有效f料送至下—邏輯方塊，但此資料在 用來栓鎖此資料之下-邏輯方塊產生—時脈邊緣前，就變成無 效’則此時會發生維持時關題。在準備時間問題的情形，對有 效資料的傳送而言’下個邏輯階段的栓猶脈邊緣產生得太早。 在維持時關題的情形’則是下個邏輯階段的栓鎖時脈邊緣產生 得太晚。 [0005] 圖1A係繪示一電路100的簡化方塊圖，該電路1〇〇具 有二個代表性的連續邏輯方塊1G1及1G3，可接收時脈訊號。第二 邏輯方塊101(邏輯方塊1)接收第一時脈訊號ECLK1，並將資料訊 號DATA送到第二邏輯方塊103(邏輯方塊2)，其會接收第二時脈 訊號ECLK2。圖1B係對照顯示電路1〇〇在同步化之時脈與具相 位差(skewed)之時脈下運作的時序圖。該時序圖繪示了 eclk 1、 ECLK2及DATA訊號相對於時間的波型(Trace)。特定時間點顯示 於其中，依序為Ή、T2、T3、T4及T5。 [0006] 圖1Β中，前二個波型係顯示ECLK1及ECLK2時脈訊 5虎為同步的情況，以解說準備時間問題。例如，如圖所示，ECLK1 及ECLK2訊號具有同步邊緣，包括在時間T1，實質上同時產生 的下降緣，以及在時間T3，實質上同時產生的上升緣。第三個波 型則顯不來自於第一邏輯方塊101的DATA訊號之相對時序，其 中DATA訊號在時間Τ4(其在時間乃後），會切換而變為有效。同 1261160 步時脈的情況係用來說明準備時間的問題，其令第—邏輯方塊⑼ 具有-關鍵延遲路徑，以致於直到時間T3的 嶋訊號在時間Τ4產生之有效資料才會被送到邏輯 由於邏輯方塊⑽t的工作延觀—時脈職的 ECLK2在_Τ3產生上親時，無效:細嫩 ^ _7]，时’如及第五__^clk2訊號相對於 ECLK1纟仏虎具有相位差的情況。特別是，第四波型中^幻訊 號的變化情形與第-波型之ECLK1峨相似。第五 相 [0008]迄今，设計者已提出硬體接線(—ed)邏輯可使送 到連續邏财塊的時脈具有她差，萌決_雜及維持時間 的問題。但是’這樣的解決方式所提供的時脈相位差，在實作 即改t：，除非修改晶片的設計。再者，參考前述的例子，一 般熟習此項技術者即可瞭解到，只有在第二邏輯方塊⑴3有可 行延遲的娜時，找輯ECIm麟方式為，將前一 邏輯方塊〇邏輯雜10他鎖私資騎_時前，以使其 留有更多時間進行卫作。然而，這轉決方式並不總是可行，^ 可能導致新的不可預見之時序問題。 # [0009]實際上，將―晶片設計做成產品之前，設計者會分析及 擬積體電路巾的複雜邏輯路彳纟。但是熟習此項技術者都瞭解， 時脈相位差巾的些微差異並無法足夠精確地進行模擬，且產品製 對於ECLK丨，具有她差的ECLK2，其t eclk降緣'= 生於時間T1後之時間T2，而咖2之後續上升緣 =後之綱T5。具她差之時脈的情況魏赌由將虹幻^ 對於ECLK1進行延遲’可消轉備時齡掩。侧是，虹幻 的上升緣倾延遲，直到DATA訊號變成有效，因此可使來自於 第-邏輯方塊10!的資料有效地轉移到第二邏輯方塊他。 1261160 ，的變化也無法精確地_化。·，所製造的频電路 、，-些不可預_關鍵時序路徑，而迫使設計者需在 二 進仃處理。因此’在晶片已製成且時脈相位差已確立之後，、= 準備__ ’只能藉由降低元件的時脈速度來消除 更糟的是’此時若發生維持時間問題’將使晶片完全益法運作 3是哪-種情況，都需要在設計上㈣顯的修改(通常包括 遮罩’電子光束分析等）’祕正這些麵的問題。 【發明内容】 [0010]本發明之一實施例提供一種IC，其包括複數個可 時脈相位差緩衝H、—固定相位差邏輯、—外部介面及—相位1 控制器。每—可程式時脈相位差缓衝器均用以接收—分佈時脈$ 號以提供-對應之内含-程式相位差的區域時脈訊號。該固定相 位差邏輯顧以致能靜態相位差量的永久性程式化。該外部介面 則用以致能動態相位差量的程式化。該相位差控制㈣擇一使用 該些靜態她差量或是雜相位差量雜式控繼些可程式時脈 相位差緩衝器。 [0011] 在另一實施例中，該相位差控制器更可在重置(reset)該 1C日守’同時偵測一相位差置換命令(skew 〇ver ride 肪d)，並 且根據相位差置換命令選擇使用該靜態相位差量或是該動態相位 差量。該可程式控制記憶體可以直接整合於該IC上，亦可經由該 外部介面耦接於該1C上。該相位差控制器可以是任一種永久性^ 私式控制£塊’例如雷射增壓溶線(laser—blown也奶)及可程式唯古矣 記憶體(EPROM)等。 ’ [0012] 本發明之又一實施例提供一種調整一積體電路時脈相 位差的方法，其包括由該積體電路在重置的同時，決定是否提供 1261160 相位差置換πρ令，若決定不提供該相位差置換命令時，則從整 j摘體電路上之固定她差邏輯選取複數個她差量；若決 疋提t摘位差_命令時，則從—相位差記憶體選取複數個相 位差里根據所選取的该些相位差量，程式化至少一個整合在該 ，體電路上之可程式控制延遲區塊H每—可程式控制延遲 區塊各自接收-分佈時脈訊號，並根據—所選取的相位差量以提 供至少-個含有-相位差之區域時脈訊號。 [0013] 在-實施例巾，本方法包括整合該她差記憶體在該 積體電路上，_位差記憶體係做為記憶體，並且經由一 外士I面’以私式化該相位差記憶體。該方法更包括程式化在該 積體電路上之—相位差置換位元，並且在該積體電路重置時，讀 取該相位差置換位元。該方法更包括在程式化該她差記憶體及 该相位差置換位元時，將該積體電路保留在重置狀態。該方法更 包括測試該積體電路，並且該積體電路係以該些_相位差量進 行程式化，重複該測試與程式化以決定一組最佳相位差量；並且， 使用該組最佳相位差量對該固定相位差邏輯進行程式化。 [0014] 本發明之再一實施例提供一種藉調整一積體電路時脈 訊號的系統，其包括：一永久可程式控制區塊，該永久可程式控 制區塊係用以永久性的程式化至少一個固定相位差量；可程式控 制邏輯，該可程式控制邏輯係用以儲存至少一個動態相位差量； 至少一個時脈緩衝器；以及，一相位差控制器，該相位差控制器 係用以在該固定相位差量與該動態相位差量之間擇一，並用該選 擇之相位差里對遠時脈緩衝器進行程式化。每一時脈緩衝器均包 括可私式控制延遲邏輯，該可程式控制延遲邏輯根據一選擇之相 位差量，用以延遲一時脈訊號。 1261160 【實施方式】 [0021] 以下的說明’係在特定實施例及其必要條件的脈絡下 而&供，可使一般热習此項技術者能夠利用本發明。铁而，各種 對實施例所作的修改，對熟習此項技術者而言乃係顯而易見，並 且，在此所討論的-般原理，亦可應用至其他實施例。因此，本 發明並不限於此處所展示與敘述之特定實施例，而是具有盘此處 所揭露之原理與新穎特徵相符之最大範圍。 〃 [0022] 本發明提供給積體電路(IC)設計者一種裝置及方法，該 裝置及方法係用以在對-積體電路進行測試及除錯時，動態的控 制其區域時脈，並且將最佳之時脈相位差程式化到一組合元件 中。據此，本發明開發出-種在一組合元件上之微調積體電路時 脈訊號之裝置及方法，可永久性的建立最佳之雜她差，使得 速率可達最大值，並可對所有珊之外關題有—補償作用，如 下文配合圖二_圖四做進一步說明。 [0023] 本發賴供-難置及綠，該裝置及方法係用以在 對η積體電路進行測試及除錯時，動態的控制其區域時脈，並且 將最佳之時脈她差喊侧—組合元件巾。在沒有該程式化相 位差的情況下’在起動時，該組合元件將經由—岐相位差邏輯 方塊使用時脈她差，賴定她差邏輯方塊可祕線及可程式 唯讀記，lt_PRGM)等，並且該些雜她差喊化到該晶 =本身中。測试用之時脈相位差係儲存在一相位差記憶體中，而 w重置時，-整合於該晶片上之相位差控制器則被指令去使用存 於該相位差記憶_她差。該她差記㈣可為一整合於該晶 片上之動叙紐’並可經由—外部界面鋪人。軸位差的延 ，可以依照預定的幅度遞增，但不超過—最大值。當侧到一组 取佳之時脈相位差時，相位差值即永久的被儲存在該固定相位差 1261160 =:糟峨用_可程式控繼域時脈 值，並可騎奸肖=3達最大 =(:\說-特定部份)即可被最佳化=二= ”且件(或w特定部份)可重行運作，並被最佳化。 [0024]圖二係根據本發明之一示範實施例緣示之包含 調整线之積體電路(IC)勘的方顧。在崎示 =1二。广為微處理器，然而要瞭_的是’本發明可應用 方建=日日片上之任何型式的電路或魏。該1C 2GG包括-時脈 ^ 20卜該時脈產生器、2〇1係用以產生一原始時脈訊號，即 CLK及CORE CLK訊號會被送到時脈分佈網路203。時 ，刀佈網路203會提供多個分佈副本或版本之該c〇RE clk訊 唬，分別表示為訊號EEE CLK卜EEE CLK2，_，ΕΈ£ OJCN， 其中Ν為大於〇的整數。每一 EEECLKx訊號(其中X為一選自工 至N的任一整數)均分別被送至内建在該1C 200上之多數邏輯方塊 205的某一者。該些邏輯方塊2〇5可分別表示為邏輯方塊丨，邏輯 方塊2，··· ’邏輯方塊]^，其中該邏輯方塊2〇5的數量，即整數值 =，係取決於整合於該IC 2⑻上之特別功能。一般而言，該些邏 輯方塊105係代表實施於該1C 200之元件的主要邏輯方塊。 [0025]每一邏輯方塊205若不是包括即是連接至一對應的區 域相位差控制器207,該些區域相位差控制器207分別表示為 LOCAL CTRL 1，LOCAL CTRL 2，…，LOCAL CTRL N。每一 區域相位差控制器207均各自接收一對應的EE CLKx訊號，並提 供對應的一組時脈訊號，該組時脈訊號可包括一或多個區域或，，E level”時脈訊號，該些區域或”E levd，，時脈訊號係以e CLKSx代 表’每一時脈組則分別表示ECLKS1，ECLKS2，…，ECLKSN。 12 1261160 每- ECLKSx代表—組時脈訊號，且該組時脈訊號可包括一或多 個區域時脈訊號，詳如下述。該些E CLKSx訊號為大體上同步的， 即大體上具有同時邊緣㈣祕伽以㈣，雖然其個別的時序可依 其過程變化及f物理因素的不同而不同’例如CLKx訊號在晶片 上之位置電谷輕合、汛號跡特性等。該些區域相位差控制器肅 程式化她差插人到每—組ECLKSx中之每—區域時脈訊號 中’使得其姆之時序均取決於該錄式化相位差。 [0026] 1C 200包括一相位差控制器2〇9，該相位差控制器謝 可在，遲值汛號線(deiay value signal㈣上輸出一或多個延遲 ，而每區域相位差控制器2〇7均分別與一延遲值訊號線連結。 本發明之-具體實施例中，該些延遲鶴為—串列之二進位編 碼，遲位元流。該1C 2〇〇更包括一固定相位差邏輯方塊2ιι，該 ^疋相位差邏輯方塊21 i、經由一或多條固定相位差值訊號線你^ skew。_es signal㈣以輸出固定相位差值(至該相位差控制器 + ± /11亥IC 200上之一測試邏輯213係與該相位差控制器209 :^並經由該1C 2〇0上之外部測試4 215與外界聯通。測試 = 可經由1C 200所提供之外部介面或外部測試埠215，從 1 卜部進行存取。職蟑215可包括1C 上任意數目的外部接腳， 4外部接腳可以是測試接腳會是雙功接腳(dual觸⑽㈣， 2如-，習此項技術者所已知的。晶片测試器217係經由測試 (/、可作為晶片測試器21γ與測試邏輯213之間的傳輸介 面），而耦接至1C 200。 陶7]測試邏輯213及測試璋215可根據如 t 卿’聯合測試動作群組)來實作，其中測試邏輯213包 類似在標準測試架構中，晶片峨器217包括插槽或 、物(未扣)，用以連接1C 200。晶片測試器217能控制冗2〇〇 13 1261160 的外指腳，包括-重雖ST)接腳，其_ 典型的JTAG架構中，例如，力斜ΤΓ7Λη、ρ 況就Κ在 曰u，丄 ㈣例如在對IC 200進行組態用以測試時， :=試器2Π會啟動IC細的電源，並且經由確認該訊號r將 ，、保持於重置狀態。在職域_，軸IC 保持於重置狀 態，但是晶片測試器217能經由測試槔215，來存取測試邏輯213， 並且设定選取暫存H巾的值或位元，或甚域人測試資料及/或用 於測試及除錯用途之-或多種測試或除錯常式。賴，當並視及 控制1C 200的運作時，晶片測試器217會釋出該訊號r以使IC 2〇〇 離開重置狀態。[0003] The present invention is a clock of continuous logic blocks on an integrated circuit, and more particularly, a method and apparatus for completing a critical timing path (4) ieal timing P in a debug and test procedure. After knowing and analyzing, I will test the micro-forever financial control office. (Previous technology] [0004] The color circuit designer has used simulation and/or testing to identify, analyze and analyze the timing problems on the wafer, usually In the best case of these problems, the second is that the wafer cannot be executed at the target clock speed, but the worst case will cause the crystal 1261160 to be modified in design before mass production. Usually, the data is transferred to the logical segment by using the temporary storage in each logical block on the slice, or the data is received from the previous logical phase. If the operation of the logic block has an associated critical delay path, and the valid data is at a specific clock speed, until the next-dependent clock edge production line is sent to To latch a logical phase under this data, the problem will occur at this time. And if the logic block sends the valid material to the lower logic block, but the data is used to latch the data - the logic block is generated - before the clock edge, it becomes invalid ' then the maintenance time will occur question. In the case of preparation time issues, the transmission of valid data is too early for the next logical phase. In the case of maintaining the title, the latching clock edge of the next logical phase is generated too late. 1A is a simplified block diagram of a circuit 100 having two representative continuous logic blocks 1G1 and 1G3 for receiving clock signals. The second logic block 101 (logic block 1) receives the first clock signal ECLK1 and sends the data signal DATA to the second logic block 103 (logic block 2), which receives the second clock signal ECLK2. Fig. 1B is a timing chart showing the operation of the display circuit 1 in synchronizing with the clock and the clocked phase. This timing diagram shows the waveform of eclk 1, ECLK2, and DATA signals with respect to time. The specific time points are displayed, in order, Ή, T2, T3, T4 and T5. [0006] In FIG. 1 , the first two waveforms show that the ECLK1 and ECLK2 are synchronized, so as to explain the preparation time problem. For example, as shown, the ECLK1 and ECLK2 signals have synchronous edges, including a falling edge that is substantially simultaneously generated at time T1, and a rising edge that is substantially simultaneously generated at time T3. The third mode is not derived from the relative timing of the DATA signal of the first logic block 101, wherein the DATA signal is switched to become active at time Τ4 (which is after time). The same situation as the 1261160 step clock is used to illustrate the problem of preparation time, which causes the first logical block (9) to have a -critical delay path, so that the valid data generated by the chirp signal at time T3 until time T3 is sent to the logic. Due to the work of the logic block (10)t, the ECLK2 of the clock is invalid when _Τ3 is generated, and is invalid: _7], when the fifth __^clk2 signal has a phase difference with respect to ECLK1 Happening. In particular, the variation of the sinusoidal signal in the fourth mode is similar to that of the first mode of ECLK1峨. The fifth phase [0008] So far, the designer has proposed that the hardware-wired (-ed) logic can make the clock sent to the continuous logic block have the problem of her poor, messy and maintenance time. However, the clock phase difference provided by such a solution is changed in practice: unless the design of the wafer is modified. Furthermore, referring to the foregoing example, those skilled in the art can understand that only when the second logical block (1) 3 has a feasible delay, the ECIm lining method is to find the previous logical block 〇 logical 10 Lock the private ride _ before the time, so that it leaves more time for the guard. However, this method of transfer is not always feasible, and ^ may lead to new unforeseen timing problems. # [0009] In fact, before the “wafer design” is made into a product, the designer will analyze and formulate the complex logic path of the integrated circuit towel. However, those skilled in the art understand that the slight difference in the clock phase difference is not accurate enough to simulate, and the product system has ECLK2 for ECLK丨, and its t eclk falling edge '= is born after time T1. The time T2, and the subsequent rising edge of the coffee 2 = the later T5. In the case of her poor clock, the Wei gambling will delay the ECLK1. On the side, the rising edge of the rainbow is delayed until the DATA signal becomes active, so that the data from the first logical block 10! can be effectively transferred to the second logical square. 1261160, the changes can not be accurately _. · The frequency circuit being fabricated, and some unpredictable _ critical timing paths, forcing the designer to process in binary. Therefore, 'after the wafer has been fabricated and the clock phase difference has been established, = ready __ ' can only be eliminated by reducing the clock speed of the component. Even worse, 'when the occurrence of the sustain time problem' will cause the wafer The full benefit of the operation of the 3 is the case, both of which need to be modified in the design (four) (usually including the mask 'electron beam analysis, etc.') to correct these problems. SUMMARY OF THE INVENTION [0010] An embodiment of the present invention provides an IC including a plurality of clockable phase difference buffers H, a fixed phase difference logic, an external interface, and a phase 1 controller. Each of the programmable clock phase difference buffers is configured to receive a -distributed clock $ sign to provide a corresponding regional clock signal with a programmed phase difference. The fixed phase difference logic takes care of the permanent stylization of the static phase difference. This external interface is used to enable the stylization of dynamic phase differences. The phase difference control (4) alternatively uses the static her or the differential phase difference to control the programmable clock phase difference buffer. [0011] In another embodiment, the phase difference controller can further detect a phase difference replacement command (skew 〇ver ride fat d) while resetting the 1C day guard and replace the phase difference according to the phase difference. The command chooses to use the static phase difference or the dynamic phase difference. The programmable memory can be directly integrated on the IC or can be coupled to the 1C via the external interface. The phase difference controller can be any type of permanent control, such as laser blasting (laser-blown milk) and programmable memory (EPROM). [0012] Yet another embodiment of the present invention provides a method for adjusting a clock phase difference of an integrated circuit, which includes determining, by the integrated circuit, whether to provide a 1261160 phase difference replacement πρ command while resetting, if determined When the phase difference replacement command is not provided, a plurality of her differences are selected from the fixed her difference logic on the whole j-splitting circuit; if the t-differential difference command is used, the complex number is selected from the phase difference memory. And selecting, according to the selected phase difference amounts, at least one programmable control delay block H integrated on the body circuit, each of the programmable delay blocks receives and distributes the clock signal, and According to the selected phase difference amount, at least one regional clock signal having a phase difference is provided. [0013] In the embodiment, the method includes integrating the her memory to the integrated circuit, the _-spot memory system as a memory, and privately arranging the phase difference via a foreigner's face Memory. The method further includes staging the phase difference permutation bit on the integrated circuit and reading the phase difference permutation bit when the integrated circuit is reset. The method further includes retaining the integrated circuit in a reset state when the her and the difference memory are programmed. The method further includes testing the integrated circuit, and the integrated circuit is programmed with the _phase difference amount, repeating the test and programming to determine a set of optimal phase difference amounts; and, using the best set of the group The phase difference amount programs the fixed phase difference logic. [0014] Still another embodiment of the present invention provides a system for adjusting a clock signal of an integrated circuit, comprising: a permanent programmable control block, the permanent programmable control block being used for permanent stylization At least one fixed phase difference amount; programmable control logic for storing at least one dynamic phase difference amount; at least one clock buffer; and, a phase difference controller, the phase difference controller is used The one of the fixed phase difference and the dynamic phase difference is selected, and the far clock buffer is programmed with the selected phase difference. Each of the clock buffers includes private control delay logic that delays a clock signal based on a selected phase difference. 1261160 [Embodiment] [0021] The following description is made in the context of a specific embodiment and its essential conditions, and can be utilized by those skilled in the art. Various modifications to the embodiments are obvious to those skilled in the art, and the general principles discussed herein may be applied to other embodiments. Therefore, the invention is not limited to the specific embodiments shown and described herein, but rather, the scope of the invention disclosed herein. [0022] The present invention provides an apparatus and method for an integrated circuit (IC) designer to dynamically control its regional clock when testing and debugging a pair-integrated circuit, and The optimal clock phase difference is programmed into a composite component. Accordingly, the present invention has developed a device and method for fine-tuning an integrated circuit clock signal on a combined component, which can permanently establish an optimum mismatch, so that the rate can reach a maximum value and can be used for all The other topic of Shan has the compensation function, as explained in the following article with Figure 2_Figure 4. [0023] The present invention is for providing hard-to-reach and green, and the device and method are used to dynamically control the regional clock when testing and debugging the η integrated circuit, and to scream the best clock. Side - combination component towel. In the absence of the stylized phase difference, 'when starting, the combined component will use the clock difference between the 岐 phase difference logic block, depending on her difference logic block secret line and programmable read only, lt_PRGM) Wait, and the miscellaneous she screamed into the crystal = itself. The clock phase difference for the test is stored in a phase difference memory, and when w is reset, the phase difference controller integrated on the wafer is instructed to use the phase difference memory. The her (3) can be a dynamic link integrated on the wafer and can be laid out via an external interface. The extension of the axial difference can be increased by a predetermined amplitude, but not exceeding the maximum value. When the side-to-group clock phase difference is good, the phase difference value is permanently stored in the fixed phase difference 1261160 =: 峨 峨 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The maximum = (: \ say - specific part) can be optimized = two = "and the part (or w specific part) can be re-operated and optimized. [0024] Figure 2 is in accordance with the present invention An exemplary embodiment includes an integrated circuit (IC) survey including an adjustment line. It is widely used as a microprocessor. However, it is required that the invention can be applied. Any type of circuit or chip on the chip. The 1C 2GG includes a clock generator, and the clock generator generates a raw clock signal, that is, the CLK and CORE CLK signals are sent. When the network is distributed 203, the cloth network 203 provides a plurality of distributed copies or versions of the c〇RE clk signals, which are respectively represented as signals EEE CLK, EEE CLK2, _, O£ OJCN, where Ν is greater than 〇 An integer. Each EEECLKx signal (where X is an integer selected from work to N) is sent to one of the majority of logic blocks 205 built into the 1C 200, respectively. The logical blocks 2〇5 can be represented as logical blocks 逻辑, logical blocks 2, . . . , and the number of the logical blocks 2〇5, ie, the integer value=, depends on the integration Special functions on IC 2 (8). In general, the logic blocks 105 represent the main logic blocks implemented in the elements of the 1C 200. [0025] Each logic block 205 is connected to a corresponding regional phase if not included The difference controller 207, the regional phase difference controllers 207 are respectively represented as LOCAL CTRL 1, LOCAL CTRL 2, ..., LOCAL CTRL N. Each of the regional phase difference controllers 207 receives a corresponding EE CLKx signal and provides Corresponding set of clock signals, the set of clock signals may include one or more regions or, E level "clock signals, the regions or "E levd," the clock signal is represented by e CLKSx 'every time The pulse group respectively represents ECLKS1, ECLKS2, ..., ECLKSN. 12 1261160 Each - ECLKSx represents a group clock signal, and the group of clock signals may include one or more regional clock signals, as described below. The E CLKSx Signal is substantially the same That is, it has substantially the same edge (four) secret gamma (4), although its individual timing can be different according to its process variation and f physical factors. For example, the position of the CLKx signal on the wafer is light and light, and the trace characteristic Etc. The regional phase difference controllers are programmed to insert each of them into each of the ECLKSx---the regional clock signals, so that the timing of each of them depends on the recorded phase difference. [0026] The 1C 200 includes a phase difference controller 2〇9, which can output one or more delays on a deiay value signal (four), and a phase difference controller per area. 7 is respectively coupled to a delay value signal line. In the embodiment of the present invention, the delayed crane is a serial-to-serial binary coded, late bit stream. The 1C 2〇〇 further includes a fixed phase difference logic. Block 2, the phase difference logic block 21 i, via one or more fixed phase difference signal lines, you skew. _es signal (four) to output a fixed phase difference value (to the phase difference controller + ± / 11 Hai IC 200 The upper test logic 213 is in communication with the phase difference controller 209 and via the external test 4 215 on the 1C 2〇0. Test = external interface or external test 215 provided via the 1C 200, Access from 1 Bu. Job 215 can include any number of external pins on 1C, 4 external pins can be test pins and will be dual-function pins (dual touch (10) (four), 2 such as -, learn from this technology Known. Wafer tester 217 is tested (/, can be used as a wafer) The test interface between the tester 21γ and the test logic 213 is coupled to the 1C 200. The test logic 213 and the test file 215 can be implemented according to a group of joint test actions, such as the test group. The 213 package is similar to the standard test architecture, and the chip slicer 217 includes a slot or an object (not buckled) for connecting the 1C 200. The wafer tester 217 can control the external finger of the redundant 2, 13 1261160, including - weight Although the ST) pin, in the typical JTAG architecture, for example, the force ramp 7Λη, ρ condition is 曰u, 丄 (4), for example, when configuring the IC 200 for testing, := tester 2Π will start The IC has a fine power supply and is held in a reset state by confirming the signal r. In the job domain, the axis IC remains in the reset state, but the wafer tester 217 can access the test logic 213 via the test port 215. And set the value or bit of the temporary H towel, or the test data of Shih and/or the test or debug routine for testing and debugging purposes. Lay, when viewing and controlling 1C 200 During operation, the wafer tester 217 will release the signal r to cause the IC 2 to exit the reset state. state.
[0028]在本發明之-具體實施例中，當將動態時脈相位差值 經由1C 200内之動態相位差值(DSV)訊號線載入至一與相位差控 制器209耦接之相位差記憶體221時，晶片測試器217會將ic 2⑽ 保持於重置狀態。該她差記舰221可岐任何^或揮發性 記憶體元件，亦可以是任何在IC 200起動時，仍可維持其狀態之 可程式控制邏輯。如其組態所示，測試邏輯213致能相位差記憶 體221可以經由相位差控制器209被外界存取。顯而易見的，若 相位差記憶體221是整合在1C 200上，則該記憶體221可位於IC 200之任何位置，並且可以方便被外界存取，例如該相位差記憶體 221可以直接與測試邏輯213耦接，或是内建有該測試邏輯213。 在圖二中，可見有一重置訊號(RESET)被送至相位差控制器2〇9， 當1C 200係為重置狀態時’該重置訊號可將相位差控制器209保 持於閒置狀態。當晶片測試器217釋出訊號r以使ic 200離開重 置狀態時，該相位差控制器209係被組態為偵測是否有一相位差 置換命令存在，若存在，則取還儲存在相位差記憶體221之動態 相位差值。相位差控制器209利用該些動態相位差值以產生延遲 值，並將該延遲值經由延遲值訊號線送至區域相位差控制器207， 14 1261160 以將該區域相位差控制器207程式化。以此方式，為達測試及/或 除錯之目的，設計者可將任意相位差程式化到任意在IC 2〇〇上之 相位差可程控區域時脈緩衝器。 [0029]當在沒有來自測試邏輯213之訊號的情形下起動或重 置時，例如沒有提供相位差置換命令時，該相位差控制器2⑻從 固定相位差邏輯211取還固定相位差值，以程式化區域相位差控 制器207。該固定相位差邏輯211可以任何適宜之方式實施，例如 複數個可程控熔線，或是任何在不供電給晶片之情形下，仍可維 持其^狀態之永久性可程控區塊。該複數個可程觀線的一起 始組態為使用非增壓之熔線，使用該些非增壓熔線將導致在每一 組E CLKSx訊號之每一區域時脈訊號均為零相位差延遲。相對 的，將一部份熔線增壓可提供些微相位差。在一使用EpR〇M之 具體實施射，該EPROM在起鱗即將㈣程式化於其中，例 如與零/些微相位差相關之資料。 ▲ [0030]在起動或重置時，相位差控制$ 2〇9係組態為可镇測 該相位差置換命令是紳在。若沒有提供她差置換命令，則該 相位差控制器209會選取儲蓄在固定相位差邏輯211之固定相^ 差值’否則，則會選取儲存在相位差記憶體221之動態相位差值。 在；上述任-情形下’雜選取之她差值均會被肋產生在 值訊號線上傳送之延雜。本發财_於任何合適的相位 與其對應之輯。在本㈣之—具體實關巾 健延遲值為_數值，在輯形下，則依序的存取該些 =侃，並將之直接依序由相位差控制器·轉移到賴值訊 1261160 (SOC)位元223的形式程式化在相位差記憶體221中。在此情形 下，该相位差控制器209係組態為讀取SOC位元223以偵測動態 相位差值是否存在，若存在，則從相位差記憶體221取還該動態 相位差值，而非從固定相位差邏輯211取還固定相位差值。在一 實施例中，可應用内含一程式S0C位元之測試邏輯2B來設定相 位差置換命令。在另一實施例中，則可應用一位於IC 2〇〇的任一 可程式控制暫存器之S0C位元來實施該相位差置換命令。舉例來 說，一微處理器晶片可包括數個用以實施相位差置換命令之多功 能暫存器。 [0032] 在本發明之另一具體實施例中，在重置過程中，晶片測 試器217經由外部測試埠215來設定相位差置換命令。在此情形 下’相位差控制器209係組態為可直接或間接經由測試邏輯213 來監測外部測試埠215。在本發明之另一具體實施例中，如圖二之 虛線部份所示，相位差記憶體221係存於該晶片測試器217中， 而非整合在該1C 200上。上述之具體實施例可將IC 200上記憶體 所佔的空間減到最少。在上述之相位差記憶體並非整合在該Ic 200的組態中，當脫離重置狀態時，該相位差控制器209係組態為 從測試邏輯213取還該動態相位差值，而該測試邏輯213則從晶 片測試器217取還該動態相位差值。如前所述，相位差置換命令 或S 0 C位元可應用於晶片上或非晶片上之任何型式的電路或功能 來實施。 [0033] 在測試或重置過程，測試邏輯213可利用晶片測試器 217將時脈相位差或延遲程式化於每一組E CLKSx中之每一區域 時脈訊號中。在此情形下，在測試1C 200以識別其關鍵時序路徑 時’没计者可以動悲的改變其區域時脈延遲’因此得以分析時序 問題，及/或決定一組最佳區域時脈相位差，該組最佳區域時脈相 1261160 =差可以使IC2GG_最快速率’或致使該lc 的廢棄之功能 付以重仃勒。趟:¾佳區域她差係永久性的財化於該扣 勘’例如程式(或於重新程式)於固定相位差邏輯叫。因此，告 起動或重置1C 200時，該相位差控制器勘利用程式於固定相ς 至邏輯211之該組最佳區域相位差對區域相位差控彻2〇 程式化。 [〇〇34]值得注意的是，根據固定相位差邏輯2ιι組態的不同， 當需要將-__位差延遲值進行程式化時，此固定相位差邏 輯211可以被再-次重新程式化。但是，此種重新程式化不適用 於-次性耕，例如雷射增魏線。同時，當沒有連接晶片測試 器217時’不論是否有__於測試及/或除錯之動態相位差記 憶體’每-次起動或重置1C 200 ’相位差控制器2G9會取還程式 化於固定相位差邏輯211之固定延遲值，並據以對區域相位差控 制器207進行程式化。 [0035] 圖三係區域相位差控制器2G7的一範例實施例之更詳 細的方塊圖。該延遲值訊號線係連結至延遲中止邏輯3〇1之一輸 入端’同_延遲值訊絲亦連結至任何隨後之區域相位差控制 器207。該延遲中止邏輯301提供M、组編碼延遲位元(enc〇ded制吵 bits)至一區域時脈緩衝器陣列303，該陣列3〇3輸出M個不同之 區域時脈訊號’即E CLK0、E CLK1、...、e CLKM。該數值「M」 可以任何合宜之整數，其代表為特定之一區域相位差控制器2〇7 所產生之區域時脈訊號的數量。 [0036] 在本發明之一具體實施例中，每一組編碼延遲位元均 包括3個真值位元CAPO、CAP1及CAP2，與對應的3個互補位 元CAPB0、CAPB1及CAPB2 ’附加於訊號名稱後的「B」係代表 互補邏輯位元。如圖三所示，該些真值位元，即CAp()、CApi及 1261160 ^AP2^係聚為—組’而該些互補位元亦另行聚為—組 止璉輯301得以提供位元組CAp2jIn a specific embodiment of the invention, the dynamic clock phase difference value is loaded to a phase difference coupled to the phase difference controller 209 via a dynamic phase difference (DSV) signal line in the 1C 200. At the time of memory 221, wafer tester 217 will hold ic 2(10) in the reset state. The heritorary 221 can carry any or volatile memory component, or any programmable control logic that maintains its state when the IC 200 is started. As shown in its configuration, the test logic 213 enabled phase difference memory 221 can be externally accessed via the phase difference controller 209. Obviously, if the phase difference memory 221 is integrated on the 1C 200, the memory 221 can be located at any position of the IC 200 and can be conveniently accessed by the outside. For example, the phase difference memory 221 can directly be connected to the test logic 213. The test logic 213 is coupled or built in. In Fig. 2, it can be seen that a reset signal (RESET) is sent to the phase difference controller 2〇9. When the 1C 200 is in the reset state, the reset signal can maintain the phase difference controller 209 in an idle state. When the wafer tester 217 releases the signal r to cause the ic 200 to leave the reset state, the phase difference controller 209 is configured to detect whether a phase difference replacement command exists, and if so, the return is stored in the phase difference. The dynamic phase difference value of the memory 221 . The phase difference controller 209 uses the dynamic phase difference values to generate a delay value, and sends the delay value to the regional phase difference controller 207, 14 1261160 via the delay value signal line to program the regional phase difference controller 207. In this way, the designer can program any phase difference to any phase difference programmable area clock buffer on IC 2〇〇 for testing and/or debugging purposes. [0029] When starting or resetting without a signal from test logic 213, such as when a phase difference replacement command is not provided, the phase difference controller 2 (8) takes the fixed phase difference value from the fixed phase difference logic 211 to Stylized area phase difference controller 207. The fixed phase difference logic 211 can be implemented in any suitable manner, such as a plurality of programmable fuses, or any permanently programmable block that maintains its state without powering the chip. The initial configuration of the plurality of programmable lines of view is to use a non-pressurized fuse, and the use of the non-pressurized fuses will result in a zero phase difference in each of the E CLKSx signals of each group. delay. In contrast, boosting a portion of the fuse can provide some microphase difference. In a specific implementation using EpR〇M, the EPROM is programmed in the grading (4), for example, data related to zero/slight phase difference. ▲ [0030] When starting or resetting, the phase difference control $2〇9 is configured to be calibrated. The phase difference replacement command is now available. If the differential replacement command is not provided, the phase difference controller 209 selects the fixed phase difference value saved in the fixed phase difference logic 211. Otherwise, the dynamic phase difference value stored in the phase difference memory 221 is selected. In the above-mentioned circumstances, the difference between her choices will be delayed by the ribs transmitted on the value signal line. This Fortune _ is in any suitable phase and its corresponding series. In this (4) - the actual actual delay value of the towel is _ value, in the form of the sequence, the access = 侃, and directly transferred from the phase difference controller to the value of 1261160 The form of the (SOC) bit 223 is programmed in the phase difference memory 221. In this case, the phase difference controller 209 is configured to read the SOC bit 223 to detect the presence of a dynamic phase difference value, and if so, to retrieve the dynamic phase difference value from the phase difference memory 221, and The fixed phase difference value is not taken from the fixed phase difference logic 211. In one embodiment, the phase difference replacement command can be set using test logic 2B containing a program SOC bit. In another embodiment, the phase difference replacement command can be implemented by applying a SOC bit located in any programmable control register of IC 2〇〇. For example, a microprocessor die can include a plurality of multi-function registers for implementing phase difference replacement commands. In another embodiment of the invention, during the reset process, the wafer tester 217 sets the phase difference replacement command via the external test port 215. In this case, the 'phase difference controller 209 is configured to monitor the external test port 215 directly or indirectly via the test logic 213. In another embodiment of the present invention, as shown by the dashed line in FIG. 2, the phase difference memory 221 is stored in the wafer tester 217 instead of being integrated on the 1C 200. The above specific embodiment minimizes the space occupied by the memory on the IC 200. In the above configuration, the phase difference memory is not integrated in the configuration of the Ic 200. When the reset state is released, the phase difference controller 209 is configured to retrieve the dynamic phase difference value from the test logic 213, and the test Logic 213 then retrieves the dynamic phase difference value from wafer tester 217. As previously mentioned, the phase difference replacement command or S0 C bit can be applied to any type of circuit or function on or off the wafer. [0033] During the test or reset process, test logic 213 may utilize wafer tester 217 to program the clock phase difference or delay into each of the sets of E CLKSx clock signals. In this case, when testing 1C 200 to identify its critical timing path, 'no one can sorrowfully change its regional clock delay' so that the timing problem can be analyzed and/or a set of optimal regional clock phase differences can be determined. The best regional clock phase of the group 1261160 = difference can make the IC2GG_ fastest rate ' or the function of causing the lc to be discarded.趟: 3⁄4 good area, she is a permanent financialization of the deduction, such as the program (or reprogramming) in a fixed phase difference logic called. Therefore, when the 1C 200 is started or reset, the phase difference controller uses the set of optimum phase phase differences from the stationary phase 逻辑 to the logic 211 to control the phase difference of the region. [〇〇34] It is worth noting that, depending on the configuration of the fixed phase difference logic 2, the fixed phase difference logic 211 can be re-programmed again when the -__ difference delay value needs to be programmed. . However, this reprogramming does not apply to sub-cultivation, such as laser-enhanced lines. At the same time, when the wafer tester 217 is not connected, 'Whether or not there is a dynamic phase difference memory for testing and/or debugging', the 1C 200' phase difference controller 2G9 will be reprogrammed every time. The fixed delay value of the fixed phase difference logic 211 is used to program the regional phase difference controller 207. [0035] FIG. 3 is a more detailed block diagram of an exemplary embodiment of a regional phase difference controller 2G7. The delay value signal line is coupled to one of the delay abort logics 〇1's input terminal' and the _delay value signal is also coupled to any subsequent zone phase difference controller 207. The delay abort logic 301 provides M, group code delay bits (enc〇ded noisy bits) to an area clock buffer array 303, and the array 3〇3 outputs M different regions of the clock signal 'ie E CLK0, E CLK1, ..., e CLKM. The value "M" can be any convenient integer representing the number of regional clock signals generated by a particular one of the regional phase difference controllers 2〇7. [0036] In an embodiment of the invention, each set of code delay bits includes three true bit positions CAPO, CAP1, and CAP2, and the corresponding three complementary bits CAPB0, CAPB1, and CAPB2' are attached to The "B" after the signal name represents a complementary logical bit. As shown in FIG. 3, the true value bits, that is, CAp(), CApi, and 1261160^AP2^ are grouped into a group, and the complementary bits are also aggregated into a group to provide a bit. Group CAp2j
⑽―_及互補位元組CAPB2陶、CApm H 訊[^]至一區域時脈緩衝器陣列303。同時亦提供該些EE X » k之一對應说號至該區域時脈緩衝器陣列3〇3。 [〇〇3η用來輸送延遲值到每一區域相位差控制器2〇7之 二：=的延遲值訊辦以有不定數量的位元。在圖示的 209^出遲他絲為單位元峨線，且該她差控制器 209輸出-串狀二軸編雜元餘縣—舰域時脈鮮£ CLKy ’其中「y」係代表範圍為〇至Μ的整數。舉例來說，^ 發明之-具體實施例中，若Ν=1〇 ’即有1〇個邏輯方塊2〇5，並且 ，每-區域相位差控制器2〇7之Μ均等於5，則總共會有％個區 域，脈訊號。若每個延遲值均為3位元，則該相位差控制器勘 須提供一串列之至少15G位元之位元流以對每—個區域時脈訊號 ^丁程式化。每-延遲中止邏輯3〇1係組態為可從該延遲值流取 得「對應之15個位元’即該延遲中止邏輯中的5個區域時脈 汛號各自均有3個編碼位元。每一延遲中止邏輯3〇1更被組態為 以CAPiJM:0]及CAPBiJM:0]的形式輸出該些取得之延遲位^至 其區域時脈緩衝器陣列303。以上述之3位元為例，若Dv=〇〇ib， 其中附加於數字後的小寫字母「b」係表示二進位記號，則該延遲 位元包括一延遲位元為〇〇lb之真值位元組及一延遲位元為u〇b 的互補位元組。 [0038]圖四係區域時脈緩衝器4〇〇之一示範實施例概圖，其 可被應用於圖三中的區域時脈緩衝器陣列303之每一區域時脈訊 號E CLKy°EE CLKx訊號會送到一反相器/緩衝器4〇1的輸入端， 而反相器/緩衝器401會在其輸出端設定一訊號IN〇，送到另一反 1261160 相器/緩衝器403的輸入端。反相器/緩衝器403會在其輪出端机— 一訊號IN 1 ’而輕接到另一反相器/緩衝器405的輸入端。反相界/ 緩衝器405會在其輸出端設定一對應區域時脈訊號ECLKy。要^ 意的是，在圖示的實施例中，由於反相器的數量為奇數，Eclk 訊號會反相於對應的EE CLKx訊號。額外的反相器/緩衝器(未^ 示)可用來使時脈吼號再次反相，而若有需要，可將反相器人緩衝= 401、403或405中的任一個組態為緩衝器。 [0039] CAPO節點係耦接至二個N通道元件m及N2的 而CAPB0節點係输至二個p通道元件ρι及p2的閉極。 節點係祕至-對N通道元件N3及N4(合起來標 ^並祕以-對N通料件m魏(合妓標示為N6= 的閘極。CAPB1節點_接至—對p通道 來) :為附3则極，並输至另—對p通道元件p5及== ΙΪ7Ρ6Γ則極。CAP2節點軸接至―_的喃N通道 ^ 8、N9及N10(合起來標示為N10:N7)的閘極，並耦接 至另-陣列的四個_道元件Nu、N12、N 、’，接 示為Ν14··Ν11)的閘極。CApB2節 U起來標 元件P7、P8、P9及漸人如+ 4係相接至一陣列的四個P通道 rs W及p10(合起來標 另一陣通道元_、pi2\ Ρ14··Ρ11)的閘極。 及Ρ14(合起來標示為 [0040] Ν通道元养w丨、 通道元件PI、Ρ3、Ρ4與Ρ7_ρω〜4與Ν7·議的跡，以及ρ 衝的輸出端。Ν通道元件Ν Μ，及5均會_至反相器/緩衝器 及Ρ通道元件ρ2、ΓΡίΓΡ、Ν6與Νη侧的汲極，以 緩衝器彻的輸出端 ；;的沒極均會福接至反相器/ 浮接(浮接源極），所以在m道轉及p通道元件之的源極會 所以在喊轉態期間’從反相 19 1261160 403的輸出端，會看到每個所耦接之元件的通道及源極電容。 [0041] 所示範的局部時脈緩衝器4〇〇係使用具有一或多個中 間節點之循序耦接(seqUentially_coupled)緩衝器，以及耦接至一或 多個中間節點之二元分佈N通道及P通道陣列來實施，以達成可 數位控制的相位差。特別是，N通道元件N卜N4:N3及N10:N7 會構成二元分佈的N通道陣列，而p通道元件P1、P4:P3及p1〇:F7 . 會構成對應之互補—元分佈的P通道陣列。以類似的方式，n 通道元件N2、N6:N5及N14:N11會構成另一個二元分佈的N通 道陣列’而P通道元件P2、Ρ6··Ρ5及P14:P11會構成另一個對應鲁 之互補且二元分佈的P通道陣列。在圖示的實施例中，從EECLKx 訊號到E CLKy訊號之間會提供二階段的延遲，以補償p通道及N 通道元件之不同的導通及關閉特性。例如，第二階段(取〇到以丨） 中的N通道元件關閉特性會補償第一階段(EE CLKx到取〇)中的p 通道元件導通特性。每個時脈緩衝器的特定架構僅是範例，而一 般熟習此項技術者皆能明瞭，此處亦可使用任何其他型式的數位 可程式延遲邏輯。 [0042] CAP0/CAPB0節點係用以控制一組n及p通道元件 (N1/P1及N2/P2)，CAP1/CAPB1節點係用以控制二個陣列之類似 · N 及 P 元件(N4:N3/P4:P3 及 N6:N5/P6:P5)，而 ACAP2/ACAPB2 節點則用以控制四個陣列的N及P元件(n1〇:N7/P10:P7及 N14:N11/P14:P11)。以此方式，設定CAP2節點所導致之EECLKx ’ 訊號的延遲，為設定CAPO節點所導致EE CLKx訊號延遲的四 - 倍。在一實施例中，每對P及N通道元件會匹配，以提供實質上· _ 相同的電阻/電容(RC)特性，使得該3位元編碼訊號每遞增一次， 即能多延遲一相當固定的延遲單位。在一示範實施例中，每個延 遲單位約為6微微秒(ps)。因此，當CAp0節點設定為高準位(邏輯 20 1261160 1) ’而CAPB0節點設定為低準位(邏輯〇)時，在ee CLJ^訊號與 ^CLKy訊號之間’會增加6ps的延遲。以類似的方式，當⑽1 節點設找高準位，* CAPB1節點設定為鮮辦，會增加 而田CAP2 #點设定為高準位’而CApB2節點設定為低 準位時，會增加24PS的延遲。例如，CAp2:CAp〇 = 〇Ub的值即相 當於通過局部«緩衝器會產生約咖的鱗脈延遲等。她 之^吏用3位元延遲ACAP2:ACAp〇節點，可使延遲在〇到鄉: 的粑圍内以6Ps為單位增加。熟f此項技術者將瞭解到，設定cApx 及CAPBx峨之所以可產生如前叙延遲，是由於通道至雛電 容的形成’此種電容係對應元件在其相關CAPx & CApBx訊號被響 設定時’從閘極所看到的。例如，—N通道元件會看到一通^至 閘極電容’此因當其赚為高準辦，從其祕到祕會軸一 ^轉通道’㈣紐過Nit道元狀祕所看狀通道至閑極電 容。若該N通道元件的難為鮮位，則不會形献轉。例如， 考慮元件N1(忽視寄生電容）’若CAp〇為高準位，則訊號胸會 看到N1的閘極電容、源極電容及沒極電容。但若CAp〇為低準位曰， 則訊號ΙΝ0只會看到N1駿極電容。如圖四所組態之p通道元件 在其對應的ACAPBx峨被設為鮮㈣，亦會產生_細遲。⑩ [0043]根據本發明的實施例’本發明之—項優點是可以在 測試-元斜，侧出該元件之最佳區域時脈她差，使得該該. 元件達其最大時脈速率。另-項優點為，可提供-種用於除錯=， 鍵路徑問題及偵測區域時脈相位差的裝置，此裝置可消除可能合-— 導致某些部件損壞關題。第三項優點為提供—種技術，其^ 於導致晶片佈局需要修改之複雜技術(如電子光束分析），而可藉由 簡單的測試分析技術(如〗TAG技術)，量化地·及補償製程^化 所產生的效應。可峨能該元件或是使元件達到其最大時脈速率 21 1261160 =最佳區域時脈她差可雜餘何合錄式化錢*被永久的 私式化於^巾，該合錄狀裝置可為HEpR⑽或其他類 似裝置。 八 、 [0044]雖然本發明及其目的、特徵與優點已詳細敛述，盆它 實施例亦可包含在本發明之錢内。例如，料要的話，可增設 頟外的陣列式N通道及p通道元件階段或層級，以提供更多的延 遲、。此外，軸本揭露㈣考慮錄半導體_财式元件(包括 互補MOS及類似元件，如NM〇s及pM〇s電晶體)方面之應用， =是本發明以類似方式，亦可應用於類比型式的技術及組態，如 雙載子元件及類似元件。 [0045]總之，以上所述者，僅為本發明之較佳實施例而已當 不能以之限定本發騎實施之顧。大凡依本發日种請專利範圍 所作之均等變化。與修飾，皆應仍屬於本發明專利涵蓋之範圍内， 谨請貴審查委員明鑑，並祈惠准，是所至禱。 【圖式簡單說明】 一[0015]本發明之效益、特徵及優點，在配合下舰明及所附 圖示後，將可獲得更好的理解，其中： [0016] 圖一 A係繪不一電路的簡化方塊圖，該電路具有二個 代表性的連續邏輯方塊，可接收對躺時脈訊號； [0017] 圖一B係對照顯示圖认之電路在同步化之時脈傲且相 位差之時脈下運作的時序圖； _8]圖二係根據本發明之一示範實施例输示之包含一時脈 相位差調整系統之積體電路(Ic)的方塊圖； 器的一範例實施例 [0019]圖三係圖二中的一區域相位差控制 之更詳細的方塊圖； 22 1261160 [0020]圖四係區域時脈緩衝器之一示範實施例概圖，其可被 應用於圖三中的區域時脈緩衝器陣列。 圖式標示說明: 100 :電路 101，103 :邏輯方塊 200 :積體電路(1C) 201 :時脈產生器 203 :時脈分佈網路 205 :邏輯區塊 207 :區域相位差控制器 209 :相位差控制器 211 :固定相位差邏輯 213 :測試邏輯 215 :外部測試埠 217 :晶片測試器 219 :重置針腳(RST) 221 :相位差記憶體 223 :相位差置換命令(SOC)位元 23(10) ― and the complementary byte CAPB2, CApm H [[]] to an area clock buffer array 303. At the same time, one of the EE X » k is also provided to correspond to the region of the clock buffer array 3〇3. [〇〇3η is used to convey the delay value to the phase difference controller 2〇7 of each area. The delay value of == has an indefinite number of bits. In the figure 209, the late wire is the unit element line, and the difference controller 209 outputs - the string-shaped two-axis coded element Yuxian - the ship's clock is fresh £ CLKy 'where "y" is the representative range An integer from 〇 to Μ. For example, in the embodiment of the invention, if Ν=1〇', there are 1 logical blocks 2〇5, and after each-area phase difference controller 2〇7 is equal to 5, then a total There will be % area, pulse signal. If each delay value is 3 bits, the phase difference controller is required to provide a series of bit streams of at least 15 Gbits to program each of the regional clock signals. The per-delay abort logic 3〇1 is configured to obtain "corresponding 15 bits" from the delay value stream, that is, 5 regions in the delay abort logic each having 3 coded bits. Each delay abort logic 〇1 is further configured to output the obtained delay bits to its regional clock buffer array 303 in the form of CAPiJM:0] and CAPBiJM:0]. The above three bits are For example, if Dv=〇〇ib, where the lowercase letter “b” appended to the number indicates a binary mark, the delay bit includes a true value byte with a delay bit of 〇〇lb and a delay bit. The element is the complementary byte of u〇b. [0038] FIG. 4 is an exemplary embodiment of an exemplary regional clock buffer 4, which can be applied to each region of the regional clock buffer array 303 in FIG. 3, clock signal E CLKy ° EE CLKx The signal is sent to the input of an inverter/buffer 4〇1, and the inverter/buffer 401 sets a signal IN at its output to another counter 1261160/buffer 403. Input. The inverter/buffer 403 is lightly coupled to the input of another inverter/buffer 405 at its turn-out terminal, a signal IN 1 '. The reverse phase/buffer 405 sets a corresponding regional clock signal ECLKy at its output. It is to be understood that in the illustrated embodiment, since the number of inverters is odd, the Eclk signal is inverted to the corresponding EE CLKx signal. An additional inverter/buffer (not shown) can be used to invert the clock nick again, and if necessary, configure the inverter buffer = 401, 403 or 405 as a buffer. Device. [0039] The CAPO node is coupled to the two N-channel components m and N2 and the CAPB0 node is coupled to the closed poles of the two p-channel components ρι and p2. The node system is secret-to-N-channel components N3 and N4 (combined with the standard and the same as - for the N-pass material m Wei (collectively labeled as N6= gate. CAPB1 node_ connected to - for p-channel) : For the 3 poles, and to the other - for the p-channel components p5 and == ΙΪ7Ρ6Γ, the CAP2 node is connected to the _ _ N channel ^ 8, N9 and N10 (collected as N10: N7) The gate is coupled to the gate of the four-channel elements Nu, N12, N, ', which are shown as Ν14··Ν11). The CApB2 section U is used to mark the components P7, P8, P9 and the gradual + 4 series connected to an array of four P channels rs W and p10 (combined with another array of channel elements _, pi2 \ Ρ 14 · · Ρ 11) Gate. And Ρ14 (collected together as [0040] Ν channel element raising w丨, channel elements PI, Ρ3, Ρ4 and Ρ7_ρω~4 and Ν7·, and the output of ρ 冲.Ν channel elements Ν Μ, and 5 Both will be _ to the inverter / buffer and Ρ channel elements ρ2, ΓΡ ΓΡ ΓΡ, Ν 6 and the Ν n side of the drain, to the buffer of the output;; the poles will be connected to the inverter / floating ( Floating source), so the source of the m-channel and p-channel components will be in the shouting state. From the output of the inverting 19 1261160 403, the channel and source of each coupled component will be seen. [0041] The exemplary local clock buffer 4 uses a sequential coupled (seqUentially_coupled) buffer with one or more intermediate nodes, and a binary distribution coupled to one or more intermediate nodes. The N-channel and P-channel arrays are implemented to achieve a digitally controllable phase difference. In particular, the N-channel components Nb N4:N3 and N10:N7 form a binary-distributed N-channel array, while the p-channel components P1, P4 :P3 and p1〇:F7. will form a corresponding complementary-meta-distributed P-channel array. In a similar manner, n-pass The channel elements N2, N6: N5 and N14: N11 will form another binary distribution of the N-channel array ' while the P-channel elements P2, Ρ6···5 and P14: P11 will constitute another complementary and binary distribution. P-channel array. In the illustrated embodiment, a two-stage delay is provided between the EECLKx signal and the E CLKy signal to compensate for the different turn-on and turn-off characteristics of the p-channel and N-channel components. For example, the second phase ( The N-channel component turn-off feature in 丨) compensates for the p-channel component turn-on characteristics in the first phase (EE CLKx to 〇). The specific architecture of each clock buffer is only an example, and is generally familiar with this. It will be apparent to those skilled in the art that any other type of digital programmable delay logic can be used herein. [0042] The CAP0/CAPB0 node is used to control a set of n and p channel elements (N1/P1 and N2/P2). The CAP1/CAPB1 node is used to control the similar array of N and P components (N4:N3/P4:P3 and N6:N5/P6:P5), while the ACAP2/ACAPB2 node is used to control the N of the four arrays. And P components (n1〇: N7/P10: P7 and N14: N11/P14: P11). In this way, set the EECL caused by the CAP2 node. The delay of the Kx 'signal is four times the delay of the EE CLKx signal caused by setting the CAPO node. In one embodiment, each pair of P and N channel components will match to provide substantially the same resistance/capacitance (RC) The feature is such that each increment of the 3-bit encoded signal can delay a relatively fixed delay unit. In an exemplary embodiment, each delay unit is approximately 6 picoseconds (ps). Therefore, when the CAp0 node is set to the high level (logic 20 1261160 1)' and the CAPB0 node is set to the low level (logic 〇), a delay of 6 ps is added between the ee CLJ^ signal and the ^CLKy signal. In a similar manner, when the (10)1 node is set to find the high level, the *CAPB1 node is set to be fresh, and the field CAP2 #point is set to the high level', and when the CApB2 node is set to the low level, the 24PS is added. delay. For example, the value of CAp2:CAp〇 = 〇Ub is equivalent to the scalar delay of the coffee generated by the local «buffer. Her 延迟 delays the ACAP2:ACAp〇 node with 3 bits, which can increase the delay by 6Ps within the range of 〇 to 乡: Those skilled in the art will understand that setting cApx and CAPBx峨 can produce a delay as described above due to the formation of the channel-to-the-capacity capacitor. The corresponding component of the capacitor is set in its associated CAPx & CApBx signal. When the time is seen from the gate. For example, the -N channel component will see a pass to the gate capacitance 'this is because its profit is high, from its secret to the secret axis, a turn channel' (four) New Nit road metamorphosis To the idle capacitor. If the N-channel component is difficult to be fresh, it will not be transformed. For example, consider component N1 (ignoring parasitic capacitance). If CAp〇 is high, the signal chest will see N1's gate capacitance, source capacitance, and no-pole capacitance. However, if CAp〇 is low-level, then the signal ΙΝ0 will only see the N1 capacitor. The p-channel component configured as shown in Figure 4 will also be set to _ fine delay when its corresponding ACAPBx is set to fresh (4). [0043] According to an embodiment of the present invention, an advantage of the present invention is that the test element can be tilted to the side of the optimum region of the component, so that the component reaches its maximum clock rate. Another advantage is that it provides a means for debugging, key path problems, and phase difference in the detection area. This device eliminates the possibility of causing damage to certain components. The third advantage is the provision of techniques that result in complex techniques that require wafer layout modifications (such as electron beam analysis), but can be quantified and compensated by simple test analysis techniques such as TAG technology. The effect produced by the chemical. Can enable the component or enable the component to reach its maximum clock rate 21 1261160 = the best region, the time difference, the difference between the clock, the amount of money, and the permanent registration of the money * is permanently privateized in the wipe, the record device can be HEpR (10) or other similar device. VIII. [0044] While the invention and its objects, features and advantages have been described in detail, the embodiments of the invention may be included in the invention. For example, if necessary, additional arrayed N-channel and p-channel component stages or levels can be added to provide more delay. In addition, the present disclosure (4) considers the application of semiconductor-based components (including complementary MOS and similar components, such as NM〇s and pM〇s transistors), = is the invention in a similar manner, can also be applied to analog versions Technology and configuration, such as dual carrier components and similar components. [0045] In summary, the above description is only for the preferred embodiment of the present invention and has not been limited to the implementation of the present invention. The average change of the patent scope is based on the date of this issue. And the modification should still fall within the scope covered by the patent of the present invention. I would like to ask your review committee to give a clear understanding and pray for it. It is the prayer. BRIEF DESCRIPTION OF THE DRAWINGS [0015] The benefits, features and advantages of the present invention will be better understood in conjunction with the following and the accompanying drawings, wherein: [0016] Figure 1A is not painted A simplified block diagram of a circuit having two representative continuous logic blocks for receiving a lying clock signal; [0017] Figure 1B is a comparison of the display circuit and the phase difference of the synchronized circuit FIG. 2 is a block diagram of an integrated circuit (Ic) including a clock phase difference adjustment system according to an exemplary embodiment of the present invention; an exemplary embodiment of the device [ Figure 3 is a more detailed block diagram of a region phase difference control in Figure 2; 22 1261160 [0020] Figure 4 is an exemplary embodiment of an exemplary regional clock buffer, which can be applied to Figure 3 The area clock buffer array. Schematic description: 100: Circuit 101, 103: Logic block 200: Integrated circuit (1C) 201: Clock generator 203: Clock distribution network 205: Logic block 207: Area phase difference controller 209: Phase Difference controller 211: fixed phase difference logic 213: test logic 215: external test 埠 217: wafer tester 219: reset pin (RST) 221: phase difference memory 223: phase difference replacement command (SOC) bit 23