WO2003005046A3 - Apparatus with a test interface - Google Patents

Apparatus with a test interface Download PDF

Info

Publication number
WO2003005046A3
WO2003005046A3 PCT/IB2002/002443 IB0202443W WO03005046A3 WO 2003005046 A3 WO2003005046 A3 WO 2003005046A3 IB 0202443 W IB0202443 W IB 0202443W WO 03005046 A3 WO03005046 A3 WO 03005046A3
Authority
WO
WIPO (PCT)
Prior art keywords
test
state machine
processor
states
successive
Prior art date
Application number
PCT/IB2002/002443
Other languages
French (fr)
Other versions
WO2003005046A2 (en
Inventor
Alexander S Biewenga
Thomas F Waayers
Original Assignee
Koninkl Philips Electronics Nv
Alexander S Biewenga
Thomas F Waayers
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Alexander S Biewenga, Thomas F Waayers filed Critical Koninkl Philips Electronics Nv
Priority to EP02733172A priority Critical patent/EP1407281A2/en
Priority to US10/482,015 priority patent/US20040177300A1/en
Priority to JP2003510970A priority patent/JP3974110B2/en
Priority to KR10-2003-7003217A priority patent/KR20030033047A/en
Publication of WO2003005046A2 publication Critical patent/WO2003005046A2/en
Publication of WO2003005046A3 publication Critical patent/WO2003005046A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2736—Tester hardware, i.e. output processing circuits using a dedicated service processor for test
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Boundary scan test circuits are controlled by a test state machine capable of assuming respective test states successively in successive test clock cycles. A single input of the test signal is normally used to control selection of successive states assumed by the test state machine. The test state machine has a standard state diagram of possible states. Further the test circuit contains a shift register to transport test data. A co-processor state machine is provided, capable of assuming respective co-processor states successively in successive cycles of the test clock. The co-processor state machine, when enabled, starts making transitions from a start state in response to assumption of a predetermined one of the test states by the test state machine. The co-processor states assumed by the co-processor following the start state control successive steps of an operation that uses data output from the scan chain under control of the test state machine and/or produce results read into the scan chain under control of the test state machine following the predetermined state. In an embodiment the co-processor supplies successive control signals to program a non-volatile memory in respective ones of the co-processor states. Programmed data is read from the scan chain in test clock cycles determined by the co-processor state machine.
PCT/IB2002/002443 2001-07-05 2002-06-20 Apparatus with a test interface WO2003005046A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP02733172A EP1407281A2 (en) 2001-07-05 2002-06-20 Apparatus with a test interface
US10/482,015 US20040177300A1 (en) 2001-07-05 2002-06-20 Apparatus with a test interface
JP2003510970A JP3974110B2 (en) 2001-07-05 2002-06-20 Device with test interface
KR10-2003-7003217A KR20030033047A (en) 2001-07-05 2002-06-20 Apparatus with a test interface

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP01202594.6 2001-07-05
EP01202594 2001-07-05

Publications (2)

Publication Number Publication Date
WO2003005046A2 WO2003005046A2 (en) 2003-01-16
WO2003005046A3 true WO2003005046A3 (en) 2003-06-05

Family

ID=8180601

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2002/002443 WO2003005046A2 (en) 2001-07-05 2002-06-20 Apparatus with a test interface

Country Status (6)

Country Link
US (1) US20040177300A1 (en)
EP (1) EP1407281A2 (en)
JP (1) JP3974110B2 (en)
KR (1) KR20030033047A (en)
TW (1) TWI224196B (en)
WO (1) WO2003005046A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7308629B2 (en) 2004-12-07 2007-12-11 Texas Instruments Incorporated Addressable tap domain selection circuit with TDI/TDO external terminal
US7328387B2 (en) * 2004-12-10 2008-02-05 Texas Instruments Incorporated Addressable tap domain selection circuit with selectable ⅗ pin interface
US7421633B2 (en) * 2005-03-21 2008-09-02 Texas Instruments Incorporated Controller receiving combined TMS/TDI and suppyling separate TMS and TDI
US7159083B2 (en) * 2002-12-13 2007-01-02 Texas Instruments Incorporated Programmable transition state machine
GB0301956D0 (en) * 2003-01-28 2003-02-26 Analog Devices Inc Scan controller and integrated circuit including such a controller
US7707467B2 (en) * 2007-02-23 2010-04-27 Micron Technology, Inc. Input/output compression and pin reduction in an integrated circuit
US10473720B2 (en) * 2015-10-27 2019-11-12 Nvidia Corporation Dynamic independent test partition clock
CN112825063B (en) * 2019-11-20 2024-08-06 瑞昱半导体股份有限公司 Combined test work group transmission system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0636976A1 (en) * 1993-07-28 1995-02-01 Koninklijke Philips Electronics N.V. Microcontroller provided with hardware for supporting debugging as based on boundary scan standard-type extensions
EP0862116A2 (en) * 1997-02-28 1998-09-02 Vlsi Technology, Inc. A smart debug interface circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6594802B1 (en) * 2000-03-23 2003-07-15 Intellitech Corporation Method and apparatus for providing optimized access to circuits for debug, programming, and test

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0636976A1 (en) * 1993-07-28 1995-02-01 Koninklijke Philips Electronics N.V. Microcontroller provided with hardware for supporting debugging as based on boundary scan standard-type extensions
EP0862116A2 (en) * 1997-02-28 1998-09-02 Vlsi Technology, Inc. A smart debug interface circuit

Also Published As

Publication number Publication date
JP3974110B2 (en) 2007-09-12
EP1407281A2 (en) 2004-04-14
TWI224196B (en) 2004-11-21
KR20030033047A (en) 2003-04-26
JP2004521363A (en) 2004-07-15
WO2003005046A2 (en) 2003-01-16
US20040177300A1 (en) 2004-09-09

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