TW200507240A - Semiconductor device and semiconductor memory device - Google Patents
Semiconductor device and semiconductor memory deviceInfo
- Publication number
- TW200507240A TW200507240A TW093122856A TW93122856A TW200507240A TW 200507240 A TW200507240 A TW 200507240A TW 093122856 A TW093122856 A TW 093122856A TW 93122856 A TW93122856 A TW 93122856A TW 200507240 A TW200507240 A TW 200507240A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor
- memory cells
- transistors
- mos transistors
- adjacent
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003290639A JP4398195B2 (ja) | 2003-08-08 | 2003-08-08 | 半導体記憶装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW200507240A true TW200507240A (en) | 2005-02-16 |
Family
ID=34190950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW093122856A TW200507240A (en) | 2003-08-08 | 2004-07-30 | Semiconductor device and semiconductor memory device |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6920079B2 (zh) |
| JP (1) | JP4398195B2 (zh) |
| CN (1) | CN1288757C (zh) |
| TW (1) | TW200507240A (zh) |
Families Citing this family (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006059481A (ja) * | 2004-08-23 | 2006-03-02 | Renesas Technology Corp | 半導体記憶装置 |
| JP4832823B2 (ja) * | 2005-07-21 | 2011-12-07 | パナソニック株式会社 | 半導体記憶装置およびｒｏｍデータパターンの発生方法 |
| US7259393B2 (en) * | 2005-07-26 | 2007-08-21 | Taiwan Semiconductor Manufacturing Co. | Device structures for reducing device mismatch due to shallow trench isolation induced oxides stresses |
| CN101313365B (zh) * | 2005-11-25 | 2011-11-09 | 株式会社半导体能源研究所 | 半导体器件及其操作方法 |
| JP4373986B2 (ja) * | 2006-02-16 | 2009-11-25 | 株式会社東芝 | 半導体記憶装置 |
| US7675124B2 (en) * | 2006-02-24 | 2010-03-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory array structure with strapping cells |
| US8247846B2 (en) | 2006-03-09 | 2012-08-21 | Tela Innovations, Inc. | Oversized contacts and vias in semiconductor chip defined by linearly constrained topology |
| US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
| US8245180B2 (en) | 2006-03-09 | 2012-08-14 | Tela Innovations, Inc. | Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same |
| US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
| US8225261B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining contact grid in dynamic array architecture |
| US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
| US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
| US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
| US8225239B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining and utilizing sub-resolution features in linear topology |
| US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
| US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
| US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
| US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
| US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
| US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
| US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
| JP5063912B2 (ja) * | 2006-03-31 | 2012-10-31 | パナソニック株式会社 | 半導体記憶装置 |
| JP2007293933A (ja) * | 2006-04-21 | 2007-11-08 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| JP4984759B2 (ja) * | 2006-09-05 | 2012-07-25 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
| JP2008124052A (ja) * | 2006-11-08 | 2008-05-29 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| US8286107B2 (en) | 2007-02-20 | 2012-10-09 | Tela Innovations, Inc. | Methods and systems for process compensation technique acceleration |
| US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
| US7888705B2 (en) | 2007-08-02 | 2011-02-15 | Tela Innovations, Inc. | Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same |
| US7596035B2 (en) * | 2007-06-29 | 2009-09-29 | Micron Technology, Inc. | Memory device bit line sensing system and method that compensates for bit line resistance variations |
| JP5127435B2 (ja) * | 2007-11-01 | 2013-01-23 | パナソニック株式会社 | 半導体記憶装置 |
| JPWO2009078069A1 (ja) | 2007-12-14 | 2011-04-28 | 富士通株式会社 | 半導体装置 |
| US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
| US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
| MY152456A (en) | 2008-07-16 | 2014-09-30 | Tela Innovations Inc | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
| US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
| US20100127333A1 (en) * | 2008-11-21 | 2010-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | novel layout architecture for performance enhancement |
| US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
| US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
| US8982651B2 (en) * | 2013-03-28 | 2015-03-17 | Stmicroelectronics International N.V. | Memory with an assist determination controller and associated methods |
| EP3404697A4 (en) | 2016-01-13 | 2019-12-25 | Toshiba Memory Corporation | SEMICONDUCTOR STORAGE DEVICE |
| KR20180064820A (ko) | 2016-12-06 | 2018-06-15 | 삼성전자주식회사 | 반도체 장치 |
| US11925027B2 (en) * | 2021-12-27 | 2024-03-05 | Sandisk Technologies Llc | Three-dimensional memory device including sense amplifiers having a common width and separation |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834820A (en) | 1995-10-13 | 1998-11-10 | Micron Technology, Inc. | Circuit for providing isolation of integrated circuit active areas |
| JPH11260054A (ja) * | 1998-01-08 | 1999-09-24 | Mitsubishi Electric Corp | ダイナミック型半導体記憶装置 |
| JP3606567B2 (ja) | 2000-03-31 | 2005-01-05 | 松下電器産業株式会社 | Ｓｒａｍ装置 |
| JP3749101B2 (ja) * | 2000-09-14 | 2006-02-22 | 株式会社ルネサステクノロジ | 半導体装置 |
-
2003
- 2003-08-08 JP JP2003290639A patent/JP4398195B2/ja not_active Expired - Fee Related
-
2004
- 2004-07-30 TW TW093122856A patent/TW200507240A/zh unknown
- 2004-07-30 US US10/902,133 patent/US6920079B2/en active Active
- 2004-08-05 CN CN200410056231.0A patent/CN1288757C/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1581490A (zh) | 2005-02-16 |
| JP2005064141A (ja) | 2005-03-10 |
| CN1288757C (zh) | 2006-12-06 |
| JP4398195B2 (ja) | 2010-01-13 |
| US6920079B2 (en) | 2005-07-19 |
| US20050041499A1 (en) | 2005-02-24 |
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