TW200427386A - Manufacturing method of multi-layered printed circuit and the interlayer conduction structure formed by the same - Google Patents

Abstract

The present invention relates to a manufacturing method of multi-layered printed circuit, which comprises forming at least a conductive through hole for conducting each layer of circuit pattern in the substrate, then overlapping at least a build-up board onto the substrate, and forming at least a conductive blind via on the build-up board, wherein the interior of conductive through hole and conductive blind via are filled with insulation material respectively, the bottom of the conductive blind via on the build-up board is overlapped on the hole lid of the conductive through hole of the substrate, and the bottom of the conductive blind via of the n-th build-up board is overlapped on the hole lid of the conductive blind hole of the (n-1)th build-up board. A tested result shows that the interlayer conduction structure of the present invention has reliable conduction quality, and since no costly conductive paste and interlayer alignment equipment are required, it has the effect of greatly reducing the manufacturing cost.

Description

200427386 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to the design of printed circuit boards. This particularly refers to a method for manufacturing a multilayer printed circuit board and the formed interlayer conduction structure, especially the interlayer conduction structure. It is composed of a conductive through hole and at least one conductive blind hole. [Description of the prior art] In the conventional multilayer printed circuit board, a plurality of layers of circuit patterns are formed on the surface and the inside of the insulating substrate ', and each layer of the circuit patterns is electrically connected through the plate by using a power ore through hole (PTH). · However, under some considerations, there are also cases where plated through-holes are not used, such as the ALVH process and B2 it process using conductive paste, and the S S P process using blind hole keypad filling technology. Although these processes have the advantage of not using plated through holes, they all need to use expensive inter-level alignment equipment to overcome the problem of inter-level alignment. Furthermore, a large amount of expensive conductive paste is required in the A l V Η process and the B 2 i t process, resulting in a high overall manufacturing cost. In addition, 'the biggest problem of this SSP process is that the quality of the plated and filled holes is not stable'. The problem that the blind holes cannot be plated often occurs, which makes the thickness of the conductor layer formed uneven. When the line level reaches 3/3 As a result, fine lines cannot be etched away, which affects the overall process yield. [Summary of the Invention] ^ A first object of the present invention is to provide a new interlayer conduction structure for electrically conducting the circuit patterns of each layer of a multilayer printed circuit board. Specifically, the multilayer printed circuit board is formed by stacking a substrate and at least one build-up board. The substrate has at least one conductive via, and the conductive via

Page 4 V. Description of the invention (2) With-conductive blind 1: = is filled with insulating material. The build-up board is at least filled with insulating material. 2 The electric blind hole also has a hole cover, and the inner part is also superposed on the substrate: the bottom of the conductive blind hole on the bottom plate of the conductive blind hole on the u build-up board; == on the hole cover, and " On the hole 盍 of the build-up hole. The conductive blind quality of this build-up door η 1-layer build-up board 'and because it does not need the' 2 r structured test system, it has a reliable conduction preparation, so it has a significant drop: ::: ί The electric paste and the expensive inter-layer alignment are set to the effect of the first-low cost of the present invention. The manufacturing method 'This method is used to produce new multi-layer printed circuit boards for the purpose of the first purpose; [Embodiment] "conducting structure" of the present invention is formed in the board. Xingyi will further explain the present invention in the following description. The best example of Miao Niu, and it is known graphically, this is only for convenience ^ Anyone who is familiar with this technology can use it for A month, but it is not limited to this. . It is called 彡 Reader 1 to 10, which reveals the manufacturing method of the wide-brush circuit board. 1 ~ 禋 扪 The present day of the month, the layering Λ L * It includes the following steps a to f: a) Provide a substrate (1): The 忒 substrate (1) is as shown in Fig. ~, And it has a top surface and a bottom surface for forming a first conductor ^ 贝 甶 and 廿 成 古 石 丨 ^ ¥ body layer (11), and the substrate (; [) And has at least one conductive via (1. I 丄 conducts the two first conductor layers (workers). /, ^ Earth plate (1) ground b) implement a first plug hole procedure: specifically 'Department first A first insulating material by screen printing

200427386 V. Description of the invention (3) The material (2) is filled in the conductive via (12,), as shown in the second figure A. Then, the air bubbles existing in the first insulating material (2) (that is, the vacuum defoaming process) are evacuated, and the insulating material (2) is cured by heating, and then the conductive via (1) will overflow. 2) The first insulating material (2) is brushed and flattened, as shown in the second figure B. Wherein, if the process of filling the conductive via (12) with the first insulating material (2) is performed in a vacuum environment, it is not necessary to perform a vacuum defoaming process. c) forming two second conductor layers (1 3) by plating to cover both ends of the two first conductor layers (1 1) and the conductive via (12), as shown in the third figure. d) Implementing a first circuit shape to form a procedure: Specifically, a first plating resist layer (14) having a first hollow pattern (1 4 1) is formed on the second conductor layer (1 3), respectively. ), Such as sticking a dry film, as shown in the fourth figure A. Then, a first circuit layer (15) is plated in the first hollow pattern (141), as shown in FIG. 4B. Next, the first circuit layer (15) is powered with a first etched resist layer (16) (e.g., an electroplated layer), as shown in the fourth figure C. Then, as shown in the fourth figures D to F, the first plating resist layer (1 4) is sequentially removed, a first etching process is performed, and the first etching resist layer (16) is removed, and then on the substrate. (1) The top surface and the bottom surface respectively form a first circuit pattern (17). Wherein, the first circuit pattern (1 7) corresponds to the conductive through hole (12), and a first hole cover (1 7 1) is formed for covering the conductive through hole (1 2). In short, the first hole cover (1 7 1) is like the conductive via (1 2

200427386 Ming Gai said hole I 5} 3 / ν 'The plate is increased by 1st-the stacking is as small as the sequence of the plate stack 1) \ e / As shown in the picture, the first five of the five must be T— ^ Taking the cocoa case as shown in Figure 3, the circuit C} electric board C, the first layer C, one of the first R, the first board C, the foil C, and the copper base in the copper board. Attached to the cover is a cover for the general display of the first N, the current display of the plate A foil map copper six grease tree as shown in appendix 1! Is the system 1.) 3 3 (〇C window sequence plate copper process layer 1 Kong Zengcheng wears one form and one formula, and the square is real.) The last name f should be 2 rims, 3 cuts, C holes, and micro holes. One 3 through C through plate. The six holes in the hole B in the display are repeated. The electric hole C is slightly different. Hai Hai = ° = 0. It is placed on the edge of the continuous system. The 2 to 3 are connected to the C straight hole. Fang that hole, wearing He ί α body Shi Lei on the matter. 1. Time 2 pieces 3 cases b0 3 cases Figure 3 Figure Road Kui Road Kongdian Electricity Institute Blind one picture Electricity seventh guide The first one is like. A square stack is pressed, and β, Nl / it port / ^ N r—I 〇〇 the bottom is' 7 3 1 () 1 c hole 3 c cover micro 3 cover hole 7) The 7 1— <.

r-H shows the edge of the material. The first will be printed by a square brush. The version of the sequence is plugged with holes first, and the mouth is actually applied. The place where the gas is displayed A) Figure 4 Eight C materials are the same as the material, absolutely) 2 3 The 3 C holes are in the blind storage and the electricity is removed. The formula is filled in and the true 4 is drawn C) 4 4 (C material The edge of the material must be the second, the second, the N, the 3, the 3, and the C (hole, blind) electrical sequence lead, the bubble will be removed in addition to the empty space, then Cran. 200427386 Five Ming instructions f issued to Leveling 5) Grinding / IV brushing must be the second most important one. Figure B. Eighth as in the middle of the circle, the space really passes. The sequence is 3 to 3 bubbles C. The hole is removed. The blind and true electric wires are imported. The re-entry needs to be filled. 4. The C material is fed into the cover and covered for 4 3 (; In a shape, the formula / ^ square 3 plated 3 electric C with holes Λ-/. Blind. 1 conductance = 0 first real first 1 in 5 first 3 J / (V statement and the figure is hollow with cutout. Second order The first step is to form a shape all the way to form an electric shape. 2) The 4th Γν layer body 3 5 3 The second I-νΰ layer is completely resisted. Plating Institute 2A Figure 12 of the electric circuit as in Example 6 3 layers The road is like 1 figure, the ten-layered case layer r—I-1, 5 on 3

It was shown that B was plated one after the other one by one, and the film was dried in the film 7 after the third layer was completely removed. The engraved image is shown in the figure 02. The eleventh is plated, such as the electric one, the RW gas 3 tin C layer is electroplated all the way. As shown in the example, the picture is applied immediately, XJ Nly 5 7 3 3 Γ \ / {V Absolutely resistive engraving and engraving electric name 22nd first Haihai = mouth = ΰ to remove the division order, and sequentially engraving Fli to second Dth \) y oo 8 3 3 (C hole case blind circuit The conductive one-to-one should be the first to the first) into the figure of the 8-shaped 3 plane C} Road 3 The second layer of the C board should increase, and the first one should be the first. • ~ 3 ^ 巴 孑 Θ is not conductive blindly, this guide should be closed as soon as possible 1—_ 8 Nly 0〇1 ('8 cover 3 holes C two cover first hole. Second, cover first 11口 之 成 简} Shape. 3 Departments} 3 places 3 C 3 holes j C blind

Hole Borrow} Tongbei 1 Electricity C Guide} Board 7 bases by 1 You should borrow {知 系 得} Easy 7 Qing 1 45 — Take C as the first case, map the middle and check the electricity, watch the first guide The top surface of F is composed of ten planes and the bottom plane} is formed by two planes. ^ —_ Top C Case map path ^ ¾ Upper hole} Pass 3 layers of the electrical C guide plate, and add one ^ one by one. It leads to} to form 3 structures 3) (8 holes and 3 blind C electric case maps.

200427386 It is necessary to increase the number of steps on the surface to increase the conductive continuity of the conductive η layer using a complex number of patterns. The conductors according to the present invention can be shown in the tenth step, corresponding to the tenth figure. Many discussions about how to increase the layer are based on the characteristics of the blind L of the layer of the blind L. The conductive layer is the second, the second, and the second. More south. (Indicated by the base) ° Not only shows the substrate, but also covers the η-conducting junction circuit diagram of the circuit pattern (the structure of the build-up board (5), the sub-board executed only once by the above e-layer uses two examples, the substrate Shows each layer of a substrate stacked on the build-up board, and the first build-up board structure, and it is the case that the case is' 5. Explanation of the invention (6) (12) and the conductive blind hole (33 printed circuit) The circuit pattern of each layer of the board. In the example shown in the eleventh figure 3 8), a third circuit pattern (a third circuit pattern (5 ~ F) is formed on the combined first-layer board (the structure shown in FIG. 5 to F is obtained.) Similarly, The circuit pattern F and the double panel shown in Fig. 11 are formed thereon. However, there are many circuit patterns in the layer. In the structure of each board described above, the conductive through-hole through the bottom is superimposed on the bottom of the conductive blind hole. The holes are covered by the base plate and the multi-layer boards. The electrical vias and conductive holes disclosed in the previous technology use a resin or non-conductive system to conduct a multilayer through the board. ) Λ in 1), which restates the number of layers e to j based on FIG ply twelfth example (example 6, to the sheet thickness based conductive vias turning process and the layers laminated between the layer structure of the sample, in particular the present invention is only apertured hole wall is plated side 々 ^

ImL · y t ^ N 7T ^ Filled with edge materials, these insulating materials are pastes, no matter what kind of insulation is used

200427386 V. Description of the invention (7) The edge materials are much cheaper than the conductive paste. Compared with copper paste, the price of plug-hole resin is only about 1/6 ~ 1/8 of copper paste, and the price of non-conductive copper paste is only about 1/3 ~ 1/4 of copper paste. 2. The holes of the conductive vias and conductive blind holes are completely filled with insulating material, and there is no depression of the openings. Therefore, the circuit pattern of each layer covers the conductive vias or conductive blind holes and other parts. It is as flat as possible to ensure the formation quality of the next layer of circuit patterns. 3. In the process of performing steps a to j above, the technical threshold for inter-level alignment is relatively low without the need to invest in expensive inter-level alignment equipment. 4. Since the conductive paste is not used, the hot-pressing conditions when stacking the build-up boards are not critical. '' V. This kind of special interlayer conduction structure is stacked on the conductive vias with at least one conductive blind hole, and the conductive vias and conductive blind holes are filled with insulating material. After reliability tests such as thermal oil and thermal shock, , Its resistance change rate is less than 10% of the soil, and its interlayer conduction quality is obviously quite reliable. In summary, when it is known that the present invention has industrial applicability and advancement, and no similar or similar ones have been disclosed in similar products before, it is fully novel, so it has met the application requirements for invention patents. Apply according to law

Page 10 200427386 Brief description of the drawings The first to tenth drawings are shown in the form of cross-sectional schematic diagrams' to show the execution process of steps a to j of the method of the present invention. Fig. 11 is a schematic sectional view of still another preferred embodiment of the present invention. Fig. 12 is a schematic sectional view of another preferred embodiment of the present invention. Mingtuo Tujidi No.1, No.3, No.3, No.3, No.2, and No.7 Multi-Board \ 1 / ^ —o \) y 00 4 3 6 3 ((3 (Case C Case C) Case C Case Layers Drawing board 2 material layers picture body edge empty road layer 3 edge empty road circuit to increase the electrical conductivity of the electrical insulation and increase the electrical insulation of the electrical insulation 1 1 1 1 1 hole 2 22 2) 4) 2 15 7 4 6 \) y 1 1) 3 ((2 1 层层 1 {绝 绝 C layer resistance. The barrier body is plated and etched with conductive residual electricity to conduct the first cover hole 7 3 5 () plate 6 layer C increase plate 2 layer 5 T \) y xly 3 3 ^ —_) 4 ((15 3 3 layers 00 c) 3 C absolutely 3 cases 1 C layer resistance C Figure 3 hole body plating engraved road, c blind conductive rice hole electric one window electric three two 22nd, 3rd, 2nd, 3rd, 2nd

Page

Claims (1)

200427386 VI. Scope of patent application 1. A method for manufacturing a multilayer printed circuit board, a) A substrate is provided, the substrate has a top surface and a bottom surface for forming a first conductor layer, and the substrate has at least one conductive path. Holes for conducting the two first conductor layers through the substrate; b) performing a first plug-in procedure to fill the conductive via with a first insulating material, c) forming two second conductors by electroplating Layer for covering the two first conductor layers and both ends of the conductive via d) implement a first circuit forming process to form a first circuit pattern on the top and bottom surfaces of the substrate, and the first circuit The patterns correspond to the conductive vias, and a first hole cover is formed for covering the conductive vias iL; e) implementing a stacking board procedure to stack at least a first build-up board for covering the substrate; A first circuit pattern; f) performing a perforation procedure to penetrate a micro-hole corresponding to the first build-up plate opposite to the first hole cover; g) forming a conductive blind hole in the micro-hole by electroplating, The bottom of the conductive blind hole is closely attached On the first hole cover of the first circuit pattern; h) implementing a second plugging procedure to fill a conductive blind hole with a second insulating material, 1) forming a third conductor layer for covering by electroplating The conductive blind iL; j) implementing a second circuit forming procedure to form a second circuit pattern on the first and second build-up boards, the second circuit pattern corresponding to the conductive blind Page 12 200427386 6. Scope of patent application 1 The hole is formed with a second hole cover for covering the conductive blind hole. 2. The method for manufacturing a multilayer printed circuit board according to item 1 of the scope of patent application, wherein the first plug-in procedure of step b includes: b 1) filling the first insulating material into the conductive via via screen printing; b 2) vacuuming the air bubbles existing in the first insulating material; b 3) curing the insulating material; b 4) brushing and flattening the first insulating material overflowing the conductive through hole. : 3. The method for manufacturing a multilayer printed circuit board according to item 1 of the scope of patent application, wherein the first circuit forming process of the d step includes: d 1) forming a first plating resist layer on the second conductor layer, respectively; The first plating resist layer has a first hollow pattern, and the first bell pattern covers the conductive through hole, d 2) electrically bonds a first circuit layer in the first hollow pattern; d 3) in the first D 4) removing the first plating resist layer on a circuit layer; d 5) implementing a first etching process to form the first circuit pattern on the top surface and the bottom surface of the substrate; d 6) removing the first remaining resist layer. 4. The method for manufacturing a multilayer printed circuit board according to item 1 of the scope of patent application, wherein the first build-up board is an insulating sheet, and the perforation procedure of step f is to directly form the micro-holes by laser perforation. Page 13 200427386 Fangzao board road with many printed layers IX No. Fan Li Zhuan Zhongzhong such as Λ- 巳 ί, Li Zhuan 5 Please apply for six and thunder, in order to C, C window R copper C a The plate is formed into a copper foil with a copper shape. The etching process is based on the sequence of the plate and the range is increased. A hole is passed through the middle of the step. The 1st-shaped enclosure window_He Tongzhuan Xuanzhuyue- ^ 二 口-&quot; MO Yushen's style such as square, hole 6 penetrates the radio conductivity into the filler material: the edge encloses the second order of the hole The second step of the plug-type second-brush printing step net h is 1-I in the}, and the material edge of the hole hole blindness is the second one, and the pumping square is empty. \) Y 2 h gas-filled grinding and brushing to presuppose the edge of the material; second; the blind insulation of the hole edge of the second material should be the first out of the overflow and solidification of the material \) / 3 4 hh square circuit board: Steps to print the sequence of the multi-pass printed items, please refer to the steps of the 1st, 2nd, and 2nd Fandili. In the case, the first layer of the first layer is insulated and the second layer is plated, and the first one is plated. The first layer is hollow and the second layer is provided with three body guides. The first hole is blind to the insulation layer. j 电 盖 二 涵 第 系 2 3 4 5 •, layer-by-layer absolute resistance electric engraving more than twenty-second first plating one electroplating OJ. ^ VH case upper layer empty circuit engraving second twenty-first Hai-θ = σ Yu Yu The sheet layer of the watch is increased-the first seventy-one mouthful of the •, the, the layer, the non-sequential resistance range plating lithography, the second one to remove the solid layer absolute resistance. The first picture of the etching case should be divided into two parts: / ^ The 6 into a j-shaped surface. Page 14 200427386 6. Application for patent scope 8. An interlayer conduction structure of a multilayer printed circuit board, the multilayer printed circuit board consists of a substrate And at least one build-up board, and the top and bottom surfaces of the substrate each have a first circuit pattern, and the surface of the build-up board has a second circuit pattern; and the interlayer conduction structure includes: At least one conductive via is used to conduct the two first circuit patterns through the substrate, and the conductive via is filled with an insulating material inside; two first hole covers are formed on the first circuit pattern to correspond to the conductive vias. A hole, and the first hole cover is conductively covered with the conductive through hole; at least one conductive blind hole is formed in the build-up board, and the inside of the conductive blind hole is filled with insulating material; The second hole cover is formed at the place where the second circuit pattern corresponds to the conductive blind hole, and the second hole cover is conductively covered with the conductive blind hole; and the bottom of the conductive blind hole on the build-up board Superimposed on the substrate A first aperture cover of electrical vias, and [eta] bottom of the first layer of conductive vias increase lamina is superimposed on the first tie η - 1 layer of the second hole conductive vias increase the cap ply. 9. The interlayer conducting structure of the multilayer printed circuit board according to item 8 of the scope of the patent application, wherein the insulating material includes a plug hole resin. 10. The interlayer conducting structure of the multilayer printed circuit board as described in item 8 of the scope of the patent application, wherein the insulating material includes a non-conductive copper paste. Page 15