TW200419748A - Under bump metallurgy and flip chip - Google Patents
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- TW200419748A TW200419748A TW092106131A TW92106131A TW200419748A TW 200419748 A TW200419748 A TW 200419748A TW 092106131 A TW092106131 A TW 092106131A TW 92106131 A TW92106131 A TW 92106131A TW 200419748 A TW200419748 A TW 200419748A
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Description
【發明所屬之技術領域】 200419748 本餐月疋有關於一種球底金屬層(Under Bump llurgy ’UBM )及覆晶晶片(ρπρ Chip,F/C )結 ^ t $別疋有關於一種能有效改善晶片之鮮塾與凸塊間 之接。施力的球底金屬層及應用此球底金屬層之覆晶晶片 【先前技術】 、在呵度貢訊化社會的今曰,多媒體應用的市場不斷地 急速擴張著。積體電路封裝技術亦需配合電子裝置的數位 化、、網路化、區域連接化以及使用人性化的趨勢發展。為 ^成上述的要求,必須強化電子元件的高速處理化、多功 月^化、積集化、小型輕量化及低價化等多方面的要求,於 疋積體電路封裝技術也跟著朝向微型化、高密度化發展。 其中’球格陣列式構裝(Ball Grid Array,BGA )、晶片 尺寸構裝(Chip-Scale Package,CSP )、覆晶晶片構裝( Flip Chip,F/C )以及多晶片模組(Multi—Chip Module ’ MCM )等高密度積體電路封裝技術也應運而生。 承上所述’覆晶晶片構裝(F / C )之覆晶接合技術( Flip Chip Interconnect Technology )主要係將晶片( die )之夕個I亍塾(pad ) ’利用面陣列(area array )的 排列方式’配置於晶片之主動表面(aCtiVe surface ) 上,並在各個銲墊上分別依序形成球底金屬層(Under Bump Metallurgy,UBM )及凸塊(bump ),例如銲料凸塊 (solder bump ),接著將晶片翻面(flip)之後,再利用
10545twf.ptd 第7頁 200419748 五、發明說明(2) 一 凸塊來連接至基板(substrate )或印刷電路板(pcb )之 表面的接點。值得注意的是,由於覆晶接合技術係可適用 於高接腳數(High Pin Count )之晶片封裝結構,並具有 縮小封裝面積及縮短訊號傳輪路徑等優點,使得覆晶接合 技術已被廣泛地應用在晶片封裝結構,且特別是高腳位之 晶片封裝結構。 △第1圖繪示為習知一種覆晶晶片結構的剖面示意圖。 請參閱第1圖所示,覆晶晶片結構1 〇 〇係由一晶片J i 〇、一 球底金屬層120及多個凸塊13〇(圖中僅繪示其一)所構成。 其中’晶片110具有一主動表面U2、一保護層114( passivation )及多個銲墊116(圖中僅繪示其一)。上述之 主動表面112係泛指晶片11〇之具有主動元件(active device )的一面,而保護層114及銲墊116均配置於此主動 表面1 1 2上,且保護層11 4係暴露出銲墊11 6。此外,球底 金屬層120係配置於銲墊116與凸塊130之間,用以作為銲 墊11 6及凸塊1 3 0之間的接合介面。值得注意的是,由於錫 或錫-鉛合金具有較佳之焊接特性,所以,凸塊丨3 〇之材質 經常採用錫或錫-錯合金。而錫—錯合金中之錯對於自然環 士兄的影響甚鉅’故又有無錯銲料(lead free solder)之誕 生,但是不論上述含鉛或無鉛之銲料其組成成分中皆包括 有錫金屬。 請繼續參閱第1圖,習知之球底金屬層120主要包括一 黏者層(adhesion layer)122、*阻障層(barrier layer) 124及一沾錫層(wetting layer)126。其中,黏著層122係
200419748 五、發明說明(3) 用以增加銲墊1 1 6及阻障層1 2 4之間的接合強度,其材質例 如為鈦金屬。此外,阻障層1 2 4係用以阻障凸塊1 3 0之擴散 (di f fusion)反應,其常用材質例如為鎳-釩合金。另外, 沾錫層1 2 6係用以增加球底金屬層1 2 0對於凸塊1 3 0之沾附 能力,其常用材質例如是銅金屬。故由上述可得知,習知 之球底金屬層一般採用鈦/鎳-釩合金/銅之三層結構。
值得注意的是,當上述之球底金屬層丨2 〇的沾錫層1 2 6 的組成成分為銅時,在高溫反應下,由於銅層會與凸塊 1 3 0中之錫以及快速度反應生成錫銅介金屬化合物 (Inter-Metal lie Compound,IMC),故錫可容易再擴散至 阻障層124 (即鎳-釩層)中,並與鎳—釩合金反應產生錫 鎳介金屬化合物,其為不連續塊狀結構,當黏著層為鋁 時,由於此錫鎳介金屬化合物與鋁層接合甚差,凸塊丨3 〇 易於從此介面脫落。 【發明内容】 、、因此,本發明的目的就是在提供一種球底金屬層,其 能減緩介金屬化合物之生長速度。 = 一目的就是在提供一種覆晶晶片結構,其 月b有放改善曰S片之銲墊與凸塊之間的接合能力。 基於本發明之上述目的,本發明提 層,適於改善晶片之銲墊及凸塊之間的接合能力&且此凸 ί ί ί成f分t包括錫。本發明之球底金屬層主要係由- ;層:己置:ίί:以及一沾附—阻障層所構成。其中,黏 者曰配置於!于墊上,阻障層配置於黏著層上,而沾附一阻
200419748 五、發明說明(4) 障層則配置於卩日# @ 成成分例如為:::及凸塊之間,且此沾附-阻障層之組 結構,此覆曰f二士述目的’本發明再提出-種覆晶晶片 及-凸塊所構成。”,二球底金屬層以 及多個鲜,,保護層及這護層 保護層係異兩1、 千!白配置於主動表面上,且 層、-阻障:以銲墊。球彡金屬層主要係由-黏著 配置於銲塾2 ,立沾附—阻障層所構成。其中,黏著層 則配置於阻障厗=障層配置於黏著層上,而沾附-阻障層 分例如為鎳金』=塊之間,且此沾附'阻障層之組成成 組成成分包括‘塊配置於沾附—阻障層上,且凸塊之 成分♦n明的較佳實施例所述,上述之黏著層之組成 紹或銅等:Γί?1合金、鉻、氮化鈦、氮化組、麵、 分例如為當銲塾為紹銲塾,黏著層之組成成 等金屬,A Α 鎢合金、鉻、氮化鈦、氮化鈕、钽或鋁 鈦、鈦〜被人§銲墊為銅銲墊,黏著層之組成成分例如為 此外 、、、σ金、鉻、氮化鈦、氮化鈕、鈕或鋼等金屬。 此外仿上述阻障層之組成成分例如是鎳-飢合金。 可配晉11 ΐ明的較佳實施例所述,沾附—阻障層上例如 几氧化層,而此抗氧化層之組成成分例如為金。 塊ft明因選用鎳金屬層與含錫凸塊接合,用以減緩凸 可長睡pg 1擴散反應,以降低介金屬化合物生長速度,故 a +維持凸塊與銲墊之間的接合強度,進而提高覆
200419748 五、發明說明(5) 晶晶片結構的使用壽命。 翻旦2讓本發明之上述和其他目的、特徵、和優點能更明 ”、、f懂,下文特舉一較佳實施例,並配合所附圖式,作詳 細况明如下: 【實施方式】 苐^圖^會示依照本發明一較佳實施例之覆晶晶片結構 j,面不意圖。請參閱第2圖,覆晶晶片結構2 00主要係由 二晶片21〇、一球底金屬層220及多個凸塊2 3〇(圖中僅繪示 =)所構成。其中,晶片21〇具有一主動表面212、一保 濩層214及多個銲墊216(圖中僅繪示其一)。上述晶片以^ 之,動表面212係泛指晶片210之具有主動元件的一面,而 保護層214及銲墊216均配置於此主動表面212上,且保護 層214係暴露出銲墊216。值得注意的是,晶片21〇之組成 成分可包括矽、鍺、矽鍺、鎵砷、鎵磷、銦砷、銦磷等半 導體材料,而保護層2 1 4之組成成分可包括無機化合物, 例如為氧化矽(silicon oxide)、氮化矽(siiic〇n ni tride)、磷矽玻璃(phosphosi licate glass,PSG)等。 當f ’保護層214亦可以是由上述之無機化合物材質所交 互疊合而成之複合層。此外,銲墊216例如為鋁銲墊、銅 銲墊或鋁-銅合金銲墊等。另外,球底金屬層22()係配置於 在f*墊216與鋒料凸塊230之間,用以作為鋅墊216及凸塊230 之間的接合介面。 承上所述,凸塊230之材質可例如是錫或錫-鉛合金。 當然,凸塊230之材質亦可為無鉛材質,例如是錫-銅合
200419748
金#人錫八銻合金、锡—鉍合金、錫—銦合金、錫-辞合金、錫 -銀5孟u—銀合金、錫n弟合金、锡-絲―辞合 ί :=曰鉍—銦合金或錫—銀—銅合金等。值得注意的是,本 I 疋針對含錫之凸塊23〇而提供對應之球底金屬層 220,用以減緩介金屬化合物之生長速度。 =黯續參閱第2圖所示,球底金屬;22〇主要係由一黏 者層222,一阻障層224及一沾錫—阻障層(㈣^丨叫一 barrier layer)226所構成。黏著層222配置於銲墊216
^,且黏著層222之組成成分可包括鈦、鈦—鎢合金、鉻、 =化鈦、氮化鈕、鈕、鋁、銅或甚至可以由上述材料所組 b而成之複合層。其中,當銲墊216為鋁銲墊,黏著層222 之組成成分則例如是鈦、鈦—鎢合金、鉻、氮化鈦、氮化 =、钽或鋁,而當銲墊216為銅銲墊,黏著層222之組成成 分例如,鈦、鈦—鎢合金、鉻、氮化鈦、氮化鈕、鈕或 銅黏著層222之主要作用乃是提供球底金屬層220與銲墊 216間具有較佳的接合性,其可利用濺鍍(3叫1^6^叫)或 是電鍵/無電電鍍的方式形成於晶片21()之銲墊216上。
阻障層2 2 4係配置於黏著層2 2 2上,且阻障層2 2 4之組 成f分例如是鎳—釩合金。此外,阻障層224亦可利用濺鍍 或是電艘/無電電鍍的方式形成於黏著層222上。 沾錫-阻障層226係配置於阻障層224與凸塊230之間, 其主要作用係在於提供球底金屬層220與凸塊230之間較佳 的接合性’而沾錫—阻障層2 2 6之組成成分包括錦,並同樣 可利用丨賤鑛或是電鍍/無電電鍍的方式,將沾錫—阻障層
200419748
226形成於阻障層224上。 故彳足上可得知,本發明 鎳-飢合金/鎳、鈦—鶴合金/ /鎳、氮化鈦/鎳-釩合金/鎳 鎳-釩合金/鎳、鋁/鎳—釩合 層結構。 ° 之球底金屬層2 2 0可例如為 錄-飢合金/錄、絡/錄-銳合金 、氮化纽/錄-鈒合金/鎳、组/ 金/錄、銅/錄-凱合金/鎳的二 、明繼績芩閱第2圖所示,由於沾錫—阻障層2 2 6之組成 f分包$鎳(即採用一鎳層),其與凸塊23〇中之錫反應 k,除能保持球底金屬層22〇對於凸塊23〇之間的沾附效果 外,並能有效減緩凸塊230中之錫的擴散現象,換言之, 沾錫-阻障層2 2 6即兼具了沾附及阻障之雙重效果。藉此, 可提南凸塊230與銲墊216之間的接合強度,進而提高覆晶 晶片2 0 0結構的使用壽命。 第3圖為本發明之另一較佳實施例之覆晶晶片結構的 剖面示意圖。請參閱第3圖所示,其中此覆晶晶片結構2 〇 〇 中之晶片210與凸塊230皆與第2圖相同,已詳細說明於上 文,故在此即不再多作贅述,而其不同處為球底金屬層 2 2 0增加配置一抗氧化層2 2 6,係配置於沾錫—阻障層2 2 6 上,其組成成分例如為金,藉由此抗氧化層2 2 6與外界隔 絕,係可避免球底金屬層2 2 0在與凸塊2 3 0焊接之前,球底 金屬層220之沾錫—阻障層226上產生一原生氧化層(native oxide),而需要額外增加一道去除此氧化層之步驟,故可 縮短覆晶晶片在凸塊製程進行時所耗費的時間。 綜上所述,本發明之球底金屬層及覆晶晶片結構,至
10545twf.ptd 第13頁 200419748 五、發明說明(8) 少具有下列優點: 1. 由於本發明之沾錫-阻障層採用鎳層,其與凸塊中 之錫反應慢,除能保持對於凸塊之間的沾附效果外,並能 有效減緩介金屬化合物之生長速度,且兼具阻障的效果。 2. 由於本發明之沾錫-阻障層上配置有一抗氧化層, 可避免球底金屬層上產生原生氧化層,故不需要額外增加 一道去除原生氧化層之步驟,可進一步縮短覆晶晶片製程 的時間。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 _ 神和範圍内,當可作些許之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。
10545twf.ptd 第14頁 200419748 圖式簡單說明 第1圖為習知一種覆晶晶片結構的剖面示意圖; 第2圖為本發明之較佳實施例之覆晶晶片結構的剖面 示意圖;以及 第3圖為本發明之另一較佳實施例之覆晶晶片結構的 剖面示意圖。 【圖式標示說明】 1 0 0、2 0 0 :覆晶晶片結構 1 1 0 、2 1 0 :晶片 112、212:主動表面 1 1 4、2 1 4 :保護層 1 1 6、2 1 6 :銲墊 120、220 :球底金屬層 122、222 :黏著層 1 2 4、2 2 4 :阻障層 1 2 6 :沾錫層 1 3 0、2 3 0 :凸塊 2 2 6 :沾錫-阻障層 2 2 8 :抗氧化層
10545twf.ptd 第15頁
Claims (1)
- 200419748 六、申請專利範圍 ' " ""----- 1 種球底金屬層,適於改善一晶片之一銲墊及一凸 塊之間的接合能力,其中該凸塊之組成成分包括锡,該球 底金屬層包括: 一黏著層,配置於該銲墊上; 一阻障層,配置於該黏著層上;以及 一沾附-阻障層,配置於該阻障層及該凸塊之間,且 該沾附—阻障層之組成成分包括鎳。 2 ·如申請專利範圍第1項所述之球底金屬層,其中該 黏著層之組成成分包括鈦、鈦—鎢合金、鉻、氮化鈦、氮 化组、、|呂及銅其中之一。 _ 3 ·如申請專利範圍第1項所述之球底金屬層,其中該 該銲墊為鋁銲墊,且該黏著層之組成成分包括鈦、鈦—鎢 合金、鉻、氮化鈦、氮化鈕、钽及鋁其中之一。 4·如申請專利範圍第1項所述之球底金屬層,其中該 5亥麵*墊為銅銲墊,且該黏著層之組成成分包括鈦、鈦〜鶏 合金、鉻、氮化鈦、氮化鈕、鋁及銅其中之一。 5 ·如申請專利範圍第1項所述之球底金屬層,其中該 阻障層之組成成分包括鎳—釩合金。 6 ·如申請專利範圍第1項戶斤述之球底金屬層,更包括 一抗氧化層,該抗氧化層配置於該沾附-阻障層及該凸塊 · 之間。 曰 7 ·如申請專利範圍第6項所述之球底金屬層,其中該 抗氧化層之組成成分包括金。 8. —種覆晶晶片結構,包拍r :200419748六、申請專利範圍 一晶片,具有一主動表面、一保護層及複數個銲墊, 其中该保護層及该些銲墊配置於該主動表面上,且該保護 層係暴露出該些銲墊; 一球底金屬層,包括. 一黏著層,配置於該些銲墊上; 一阻障層,配置於該黏著層上; 一沾附-阻障層,配置於該限障層上,且該沾附-阻 障層之組成成分包括錄;以&一凸塊,配置於該沾附〜障障層上,且該凸塊之組成 成分包括錫。 9 ·如申請專利範圍第8項所述之覆晶晶片結構,其中 該黏著層之組成成分包括敎、I太—鶬合金、鉻、氮化鈦、 氮化钽、钽、鋁及銅其中之一。 1 0 ·如申請專利範圍第8項戶斤述之覆晶晶片結構’其中 該銲墊為鋁銲墊,且該黏著層之組成成分包括鈦、鈦一鎢 合金、鉻、氮化鈦、氮化紐、銀及錫其中之一。1 1 ·如申請專利範圍第8項所述之覆晶晶片結構,其中 該銲墊為銅銲墊,且該黏著層之組成成分包括鈦、鈦一鎢 合金、鉻、氮化鈦、氮化鈕、鋥及銅其中之一。 1 2 ·如申請專利範圍第8項戶斤述之覆日日日日片結構,其中 該阻障層之組成成分包括鎳-釩合金。 1 3 ·如申請專利範圍第8項所述之覆晶晶片結構,更包 括一抗氧化層,該抗氧化層配f於該沾附_阻障層及該凸 塊之間。200419748 六、申請專利範圍 1 4.如申請專利範圍第1 3項所述之覆晶晶片結構,其 中該抗氧化層之組成成分包括金。10545twf.ptd 第18頁
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TWI278946B (en) * | 2004-07-23 | 2007-04-11 | Advanced Semiconductor Eng | Structure and formation method for conductive bump |
CN100428414C (zh) * | 2005-04-15 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | 形成低应力多层金属化结构和无铅焊料端电极的方法 |
WO2007008171A2 (en) * | 2005-07-09 | 2007-01-18 | Gautham Viswanadam | Integrated circuit device and method of manufacturing thereof |
US7323780B2 (en) * | 2005-11-10 | 2008-01-29 | International Business Machines Corporation | Electrical interconnection structure formation |
US20080251916A1 (en) * | 2007-04-12 | 2008-10-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | UBM structure for strengthening solder bumps |
CN101565160A (zh) * | 2008-04-21 | 2009-10-28 | 鸿富锦精密工业(深圳)有限公司 | 微机电系统及其封装方法 |
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US5234153A (en) * | 1992-08-28 | 1993-08-10 | At&T Bell Laboratories | Permanent metallic bonding method |
US6076723A (en) * | 1998-08-19 | 2000-06-20 | Hewlett-Packard Company | Metal jet deposition system |
FR2799337B1 (fr) * | 1999-10-05 | 2002-01-11 | St Microelectronics Sa | Procede de realisation de connexions electriques sur la surface d'un boitier semi-conducteur a gouttes de connexion electrique |
FR2799578B1 (fr) * | 1999-10-08 | 2003-07-18 | St Microelectronics Sa | Procede de realisation de connexions electriques sur un boitier semi-conducteur et boitier semi-conducteur |
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US20020086520A1 (en) * | 2001-01-02 | 2002-07-04 | Advanced Semiconductor Engineering Inc. | Semiconductor device having bump electrode |
US6818545B2 (en) * | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
JP2003031576A (ja) * | 2001-07-17 | 2003-01-31 | Nec Corp | 半導体素子及びその製造方法 |
TW526337B (en) * | 2001-11-16 | 2003-04-01 | Advanced Semiconductor Eng | Device for testing the electrical characteristics of chip |
TW521406B (en) * | 2002-01-07 | 2003-02-21 | Advanced Semiconductor Eng | Method for forming bump |
TW530402B (en) * | 2002-03-01 | 2003-05-01 | Advanced Semiconductor Eng | Bump process |
TW558821B (en) * | 2002-05-29 | 2003-10-21 | Via Tech Inc | Under bump buffer metallurgy structure |
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- 2003-03-20 TW TW092106131A patent/TW583759B/zh not_active IP Right Cessation
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2004
- 2004-03-18 US US10/708,664 patent/US20040183195A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20040183195A1 (en) | 2004-09-23 |
TW583759B (en) | 2004-04-11 |
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