TWI258195B - Bumped wafer structure - Google Patents

Bumped wafer structure Download PDF

Info

Publication number
TWI258195B
TWI258195B TW094100565A TW94100565A TWI258195B TW I258195 B TWI258195 B TW I258195B TW 094100565 A TW094100565 A TW 094100565A TW 94100565 A TW94100565 A TW 94100565A TW I258195 B TWI258195 B TW I258195B
Authority
TW
Taiwan
Prior art keywords
layer
wafer
titanium
copper
copper alloy
Prior art date
Application number
TW094100565A
Other languages
Chinese (zh)
Other versions
TW200625481A (en
Inventor
Min-Lung Huang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW094100565A priority Critical patent/TWI258195B/en
Application granted granted Critical
Publication of TWI258195B publication Critical patent/TWI258195B/en
Publication of TW200625481A publication Critical patent/TW200625481A/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A bumped wafer structure mainly comprises a passivation layer and a plurality of bonding pads exposed out of an opening of the passivation layer. Therein, the bumped wafer structure further comprises a plurality of under bump metallurgy layers formed on the bonding pads respectively and each under bump metallurgy layer at least comprises an aluminum layer, a titanium-copper alloy layer and a copper layer in sequence formed on the corresponding bonding pad.

Description

1258195 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種具有凸塊之晶圓結構,且特別是有 關於一種能改善設置於晶圓銲墊與銲料凸塊間之球底金 屬層之接合強度之晶圓結構。 【先前技術】 在高度資訊化社會的今日,多媒體應用市場不斷地急 速擴張,積體電路封裝技術也隨之朝電子裝置的數位化、 網路化、區域連接化以及使用人性化的趨勢發展。為達成 上述的要求’電子元件必須配合高速處理化、多功能化、 積集化、小型輕量化及低價化等多方面之要求,也因此積 體電路封裝技術也跟著朝向微型化、高密度化發展。其中 球格陣列式構裝(Ball Grid Array,BGA ),晶片尺寸構裝 (Chip-Scale Package,CSP ),覆晶構裝(Flip Chip,F/C ), 多晶片模組(Multi-Chip Module,MCM )等高密度積體電 路封裝技術也因應而生。 其中覆晶構裝技術(Flip Chip Packaging Technology) 主要是利用面陣列(area array)的排列方式,將多個晶片銲 塾(bonding pad)配置於晶片(die)之主動表面(active surface) ’並在各個晶片銲墊上形成凸塊(bump),接著再將 晶片翻面(flip)之後,利用晶片銲墊上的凸塊分別電性 (electrically)及機械(mechanically)連接至基板(substrate)或 印刷電路板(PCB)之表面所對應的接合塾加⑽价丨叩pad)。 1258195 再者,由於覆晶接合技術係可應用於高接腳數(High Pin =unt)之晶片封裝結構’並同時具有缩小封裂面積及縮短 訊號傳輸路徑等多項優點,所以覆晶接合技術目前已經廣 泛地應用在晶片封裝領域。 〃 而所謂的晶圓凸塊製程,則常見於覆晶技術(flip chip) 中主要係在形成有多個晶片的晶圓上對外的接點(通常是 金屬銲墊;亦即為晶圓銲墊)上形成球底金屬層(UBM, φ Under Bump Metallurgy Layer),接著於球底金屬層之上形 成凸塊或植入銲球以作為後續晶片與基板(substrate)電性 導通之連接介面。 明參照圖1,係為習知之具有凸塊之晶圓結構剖面示 意圖。晶圓100之主動表面101上係具有保護層102及複 數個暴i各出保護層102之晶圓鮮墊1 〇4,另外於晶圓銲墊 上104形成有一球底金屬層1〇6,且球底金屬層1〇6上形 成有一銲料凸塊108。其中,球底金屬層1〇6係配置於晶 • 圓銲墊104與銲料凸塊1〇8之間,用以作為晶圓銲墊104 及在于料凸塊1 〇 8間之接合介面。 請再參考圖1,習知之球底金屬層1〇6主要包括黏著 層(adhesion layer) 106a、阻障層(barrier layer) 106b 及 潤濕層(wettable layer) 106c。黏著層i〇6a係用以增加晶 圓鮮墊104與阻障層l〇6b間之接合強度,其材質例如為 鋁或鈦等金屬。而阻障層l〇6b係用以防止阻障層i〇6b之 上下兩側的金屬發生擴散(diffusion)的現象,其常用材 質例如為鎳釩合金、鎳銅合金及鎳等金屬。另外,潤濕層 1258195 H)6C係用以增加球底金屬層1〇6對於鲜料凸塊⑽之沾附 力(wetability),其常用材質包括銅等金屬。 值付注意的是如圖i所示,當球底金屬層1〇6之潤濕 層106c的組成成分包括銅時,在迴銲(RefJ〇w)過程期間, 由於紅料凸塊108之錫極易與潤濕層1〇6c之銅發生反應, 而生成介金屬化合物(inter_Metallic c〇mp()und,IMC), 即CuAn5 ’進而在潤濕層1〇6c及銲料凸塊1〇8間反應生 • 成一介金屬化合物層(IMC layer)。此外,當球底金屬層 106之阻障層106b的組成成分主要包括鎳釩合金、鎳銅合 金及鎳金屬時,在迴銲過程期間,銲料凸塊1〇8之錫將先 與潤濕層106c之銅反應生成介金屬化合物,即Cu6Sn5, 接著銲料凸塊108之錫將再與阻障層1〇6b之鎳金屬粒子 反應生成另一種介金屬化合物,即Nig%4。值得注意的是, 由於銲料凸塊108之錫與阻障層106b之鎳於較長時間反 應下,所產生的介金屬化合物(即Nijn4)係為不連續之 • 塊狀結構,如此將使得銲料凸塊108易於從此處脫落(即黏 著層106a與阻障層10仉之介面處 因此,如何提供解決上述問題,實為本發明之重要課 題。 【發明内容】 有鑑於此,本發明之目的係在於提出一種具有適於配 置在晶圓銲墊與銲料凸塊間之球底金屬層之晶圓結構,以 使銲料凸塊中之錫金屬粒子與球底金屬層之反應速率變 1258195 緩並降低介金屬化合物(即Ni3Sn4)之生成速率減緩,以 解決銲料凸塊易於脫落之問題,故可長時間地維持銲料凸 塊與晶圓銲墊間之接合強度,進而提高具有凸塊之晶圓結 構及晶片封裝結構之使用壽命。 緣是,為達上述目的,本發明係提出一種具有適於配 置在晶圓銲墊與銲料凸塊間之球底金屬層之具有凸塊之 晶圓結構,其中銲料凸塊之材質係包含錫,且球底金屬層 至少具有:一黏著層,配置於晶圓銲墊上;一鈦銅合金層, 配置於黏著層上;一潤濕層,配置於鈦銅合金層上。其中, 鈦銅合金層可繼續與銲料凸塊中未與潤濕層完全反應之 錫金屬粒子反應,而形成Cu6Sn5介金屬化合物 (Inter-Metallic Compound,IMC)。由於此介金屬化合物 係為一連續面,故可避免銲料凸塊與球底金屬層在此破壞 脆裂(crack)。再者,由於鈦銅合金層亦會抑制銅與錫金屬 粒子之反應速率,故Cu6Sn5介金屬化合物之生成亦較為緩 φ 慢。 綜前所述,由於鈦銅合金層係用以取代原先之含鎳金 屬之鎳合金層,故可避免阻障層(即鈦銅合金層)與黏著層 之界面處反應生成不連續塊狀結構之介金屬化合物(即 Ni3Sn4) 〇如此,可提升晶圓結構於後續封裝製程及工作運 算時之可靠度。 【實施方式】 以下將參照相關圖式,說明依本發明較佳實施例之具 1258195 有凸塊之晶圓結構。 請參考圖2,其顯示根據本發明之較佳實施例之具有 凸塊之晶圓結構的剖面示意圖。 晶圓200係具有保護層2〇2及晶圓銲墊204,且晶圓 銲墊204上係形成有一球底金屬層2〇6。其中,保護層2的 係配置於晶圓主動表面201上,用以保護晶圓200表面並 具有一開口使晶圓銲墊204暴露出;而球底金屬層則主要 瞻係由黏著層206a、阻障層206b及潤濕層206c所組成。當 晶圓銲墊204為鋁銲墊時,黏著層/阻障層/潤濕層較佳地 可為鋁/鈦銅合金/銅三層結構。而當晶圓銲墊2〇4為鋼銲 墊時,黏著層/阻障層/潤濕層較佳地可為鈦/鋁/鈦銅合金/ 銅四層結構。惟不論其黏著層、阻障層、潤濕層是由何材 料所組成,一般而言,黏著層之材質係選自於由鈦、鎢、 鈦鎢合金、鈦铭合金、鉻、銘所組成族群中之一種材質或 其組合;阻障層之材質係為鈦銅合金;而潤濕層之材質係選 φ 自於銅、鉻銅及銅合金所組成族群或其組合。其中,黏著 層、阻卩早層及潤濕層可利用減鍍之方式或電鑛之方式形成 之,保護層之材質可包含聚亞醯胺(polyimideji)或苯併 環丁稀(Benzocyclobutene,BCB)。 承上所述,由於銲料凸塊208係形成於潤濕層206c 上’即是所謂的銅、鉻銅或銅合金上,故銲料凸塊208迴 銲時,銲料凸塊208中之錫係先與潤濕層206c中之銅互相 反應,之後再往較下層之阻障層(即鈦銅合金層)2〇6b反 應。由於鈦銅合金層可繼續與銲料凸塊2〇8中未與潤濕層 1258195 206c完全反應之錫金屬粒子反應,而形成Cu6Sn5介金屬 化合物(Inter-Metallic Compound,IMC)。由於此介金屬 化合物係為一連續面,故可避免銲料凸塊與球底金屬層在 此破壞脆裂(crack)。再者,由於鈦銅合金層亦會抑制銅與 錫金屬粒子之反應速率,故Cu6Sn5介金屬化合物之生成亦 較為緩慢。 再者,由於鈦銅合金層係用以取代原先之含鎳金屬之 鎳合金層,故可避免阻障層(即鈦銅合金層)與黏著層之界 •面處反應生成不連續塊狀結構之介金屬化合物(即 Ni3Sn4) 〇如此,可提升晶圓結構於後續封裝製程及工作運 算時之可靠度。 由上可知,本發明之主要特徵係為形成一含鈦銅合金 之材質於與銲料凸塊相接合之球底金屬層中,以取代原先 之鎳釩合金層,故不會使銲料凸塊中之錫與球底金屬層於 較長時間反應下,在球底金屬層之其他下層結構中形成不 φ 連續之塊狀結構之介金屬化合物(即生成Ni3Sn4),而降低 銲料凸塊與球底金屬層之接合強度。 於本實施例之詳細說明中所提出之具體的實施例僅 為了易於說明本發明之技術内容,而並非將本發明狹義地 限制於實施例,因此,在不超出本發明之精神及以下申請 專利範圍之情況,可作種種變化實施。 【圖式簡單說明】 圖1為習知之具有凸塊之晶圓結構剖面示意圖。 1258195 圖2為依照本發明較佳實施例之具有凸塊之晶圓結構 剖面示意圖。 元件符號說明: 100 ·晶圓 101:主動表面 102 :保護層 104 :晶圓銲墊 _ 106 :球底金屬層 106a:黏著層 106b:阻障層 106c:潤濕層 108 :銲料凸塊 200 ·晶囫 201:主動表面 _ 202 :保護層 204 :晶圓銲墊 206 :球底金屬層 206a:黏著層 206b:阻障層 206c:潤濕層 208 :銲料凸塊 111258195 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer structure having bumps, and more particularly to a ball-metal layer disposed between a wafer pad and a solder bump The bonding strength of the wafer structure. [Prior Art] In today's highly information society, the multimedia application market continues to expand rapidly, and the integrated circuit packaging technology has also evolved toward the digitalization, networking, regional connectivity, and user-friendliness of electronic devices. In order to achieve the above requirements, electronic components must meet the requirements of high-speed processing, multi-function, integration, small size, light weight, and low cost. Therefore, integrated circuit packaging technology is also moving toward miniaturization and high density. Development. Among them, Ball Grid Array (BGA), Chip-Scale Package (CSP), Flip Chip (F/C), Multi-Chip Module , MCM) and other high-density integrated circuit packaging technology also came into being. Among them, Flip Chip Packaging Technology mainly uses an array of area arrays to arrange a plurality of wafer bonding pads on the active surface of the die. Forming a bump on each of the wafer pads, and then flipping the wafers, respectively, electrically and mechanically connected to the substrate or printed circuit using the bumps on the wafer pads The joint corresponding to the surface of the board (PCB) is (10) 丨叩 pad). 1258195 Furthermore, since the flip chip bonding technology can be applied to a chip package structure with a high pin count (High Pin = unt) and at the same time has many advantages such as reducing the cracking area and shortening the signal transmission path, the flip chip bonding technology is currently It has been widely used in the field of chip packaging. 〃 The so-called wafer bump process is common in flip chips, which are mainly external contacts (usually metal pads; that is, wafer soldering) on a wafer on which multiple wafers are formed. A pad metal layer (UBM, φ Under Bump Metallurgy Layer) is formed on the pad, and then a bump or a solder ball is formed on the ball metal layer to serve as a connection interface between the subsequent wafer and the substrate. Referring to Figure 1, there is shown a cross-sectional view of a conventional wafer structure having bumps. The active surface 101 of the wafer 100 has a protective layer 102 and a plurality of wafer fresh pads 1 〇 4 of the protective layer 102, and a ball bottom metal layer 1 〇 6 is formed on the wafer pad 104, and A solder bump 108 is formed on the ball metal layer 1〇6. The ball-metal layer 1〇6 is disposed between the wafer-shaped solder pad 104 and the solder bumps 1〇8, and serves as a bonding interface between the wafer pad 104 and the bumps 1 and 8 . Referring again to FIG. 1, the conventional ball metal layer 1〇6 mainly includes an adhesion layer 106a, a barrier layer 106b, and a wettable layer 106c. The adhesive layer i6a is used to increase the bonding strength between the crystal fresh pad 104 and the barrier layer 16b, and is made of a metal such as aluminum or titanium. The barrier layer 16b is used to prevent diffusion of metal on the upper and lower sides of the barrier layer i〇6b, and the commonly used materials are, for example, a metal such as a nickel vanadium alloy, a nickel-copper alloy, or a nickel. In addition, the wetting layer 1258195 H) 6C is used to increase the wettability of the ball bottom metal layer 1〇6 to the fresh material bumps (10), and the commonly used materials include metals such as copper. It is noted that, as shown in FIG. i, when the composition of the wetting layer 106c of the ball bottom metal layer 1〇6 includes copper, during the reflow process (RefJ〇w), due to the tin of the red bump 108 It is easy to react with the copper of the wetting layer 1〇6c to form a intermetallic compound (inter_Metallic c〇mp()und, IMC), ie CuAn5' and further between the wetting layer 1〇6c and the solder bumps 1〇8 Reactive • Form a metal compound layer (IMC layer). In addition, when the composition of the barrier layer 106b of the bottom metal layer 106 mainly includes a nickel vanadium alloy, a nickel copper alloy, and a nickel metal, the tin of the solder bump 1〇8 will first be wetted with the wetting layer during the reflow process. The copper of 106c reacts to form a metal intermetallic compound, namely Cu6Sn5, and then the tin of the solder bump 108 will again react with the nickel metal particles of the barrier layer 1〇6b to form another intermetallic compound, Nig%4. It is worth noting that since the tin of the solder bump 108 reacts with the nickel of the barrier layer 106b for a long time, the resulting intermetallic compound (ie, Nijn4) is discontinuous • a bulk structure, which will make the solder The bumps 108 are easily detached therefrom (that is, the interface between the adhesive layer 106a and the barrier layer 10A. Therefore, how to solve the above problems is an important subject of the present invention. [Invention] In view of the above, the object of the present invention is A wafer structure having a ball-bottom metal layer disposed between a wafer pad and a solder bump is proposed to reduce the reaction rate of the tin metal particles and the ball metal layer in the solder bump by 1258195. The formation rate of the intermetallic compound (ie, Ni3Sn4) is slowed down to solve the problem that the solder bumps are easily detached, so that the bonding strength between the solder bumps and the pad pads can be maintained for a long time, thereby improving the wafer structure with bumps. And the service life of the chip package structure. For the above purpose, the present invention provides a tool having a ball-bottom metal layer suitable for being disposed between a wafer pad and a solder bump. a bump structure, wherein the material of the solder bump comprises tin, and the bottom metal layer has at least: an adhesive layer disposed on the wafer pad; a titanium-copper alloy layer disposed on the adhesive layer; The wet layer is disposed on the titanium-copper alloy layer, wherein the titanium-copper alloy layer can continue to react with the tin metal particles in the solder bump that are not completely reacted with the wetting layer to form a Cu-Sn5 intermetallic compound (IMC). Since the intermetallic compound is a continuous surface, it is possible to prevent the solder bump and the bottom metal layer from breaking the crack. Further, since the titanium copper alloy layer also inhibits the copper and tin metal particles. The reaction rate, so the formation of Cu6Sn5 intermetallic compound is also slower φ slow. As mentioned above, since the titanium-copper alloy layer is used to replace the original nickel-containing nickel alloy layer, the barrier layer (ie titanium copper) can be avoided. The alloy layer reacts with the interface of the adhesive layer to form a discontinuous block-like intermetallic compound (ie, Ni3Sn4). Thus, the reliability of the wafer structure in subsequent packaging processes and work operations can be improved. MODES OF THE INVENTION Hereinafter, a wafer structure having a bump of 1258195 according to a preferred embodiment of the present invention will be described with reference to the related drawings. Referring to FIG. 2, a wafer having bumps according to a preferred embodiment of the present invention is shown. Schematic diagram of the structure. The wafer 200 has a protective layer 2〇2 and a wafer pad 204, and a wafer bottom metal layer 2〇6 is formed on the wafer pad 204. The protective layer 2 is arranged in the crystal. The circular active surface 201 is used to protect the surface of the wafer 200 and has an opening to expose the wafer pad 204. The bottom metal layer is mainly formed by the adhesive layer 206a, the barrier layer 206b and the wetting layer 206c. When the wafer pad 204 is an aluminum pad, the adhesion layer/barrier layer/wetting layer may preferably be an aluminum/titanium copper alloy/copper three-layer structure. When the pad 2 〇 4 is a steel pad, the adhesion layer/barrier layer/wetting layer may preferably be a titanium/aluminum/titanium-copper alloy/copper four-layer structure. However, regardless of the adhesive layer, the barrier layer, and the wetting layer, the material of the adhesive layer is generally selected from the group consisting of titanium, tungsten, titanium tungsten alloy, titanium alloy, chromium, and Ming. One of the materials or a combination thereof; the material of the barrier layer is titanium-copper alloy; and the material of the wetting layer is selected from the group consisting of copper, chromium copper and copper alloy or a combination thereof. Wherein, the adhesive layer, the early barrier layer and the wetting layer can be formed by means of deplating or electric ore, and the material of the protective layer can comprise polyimide or benzocyclobutene (BCB). ). As described above, since the solder bumps 208 are formed on the wetting layer 206c, that is, so-called copper, chrome-copper or copper alloy, when the solder bumps 208 are reflowed, the tin in the solder bumps 208 is first. The copper in the wetting layer 206c reacts with each other, and then reacts to the lower barrier layer (i.e., the titanium-copper alloy layer) 2〇6b. Since the titanium-copper alloy layer can continue to react with the tin metal particles of the solder bumps 2〇8 which are not completely reacted with the wetting layer 1258195206c, a Cu6Sn5 intermetallic compound (IMC) is formed. Since the intermetallic compound is a continuous surface, it is possible to prevent the solder bump and the bottom metal layer from breaking the crack. Furthermore, since the titanium-copper alloy layer also suppresses the reaction rate of copper and tin metal particles, the formation of Cu6Sn5 intermetallic compound is also slow. Furthermore, since the titanium-copper alloy layer is used to replace the nickel-nickel alloy layer of the original nickel-containing metal, the barrier layer (ie, the titanium-copper alloy layer) and the adhesion layer can be prevented from reacting to form a discontinuous block structure. The metal compound (ie, Ni3Sn4) can improve the reliability of the wafer structure in subsequent packaging processes and work operations. As can be seen from the above, the main feature of the present invention is that a material containing a titanium-copper alloy is formed in a spherical metal layer bonded to a solder bump to replace the original nickel-vanadium alloy layer, so that the solder bump is not formed. The tin and the bottom metal layer react under a long period of time to form a mesometallic compound (ie, Ni3Sn4) which is not a continuous block structure in the other underlying structure of the bottom metal layer, and reduces the solder bump and the bottom of the ball. Bonding strength of the metal layer. The specific embodiments of the present invention are set forth in the detailed description of the present invention, and are not intended to limit the scope of the present invention to the embodiments. The scope of the situation can be implemented in various changes. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a conventional wafer structure having bumps. 1258195 is a cross-sectional view of a wafer structure having bumps in accordance with a preferred embodiment of the present invention. Component Symbol Description: 100 · Wafer 101: Active Surface 102: Protective Layer 104: Wafer Pad _ 106: Bottom Metal Layer 106a: Adhesive Layer 106b: Barrier Layer 106c: Wetting Layer 108: Solder Bump 200 Crystal 201: Active surface _ 202: Protective layer 204: Wafer pad 206: Bottom metal layer 206a: Adhesive layer 206b: Barrier layer 206c: Wetting layer 208: Solder bump 11

Claims (1)

1258195 十、申請專利範圍: h —種具有凸塊之晶圓結構,包含: 一主動表面; 複數個晶圓銲墊,設置於該主動表面上; 保濩層,設置於該主動表面上且具有複數個開口暴 露出該等晶圓銲墊;及 複數個球底金屬層,係設置於該等晶圓銲墊上且每一 該等球底金屬層係分別包含一黏著層、一鈦銅合金 層與一潤濕層,該黏著層係與該晶圓銲墊連接,而 該鈦銅合金層係設置於該黏著層上,且該潤濕層係 設置於該鈦銅合金層上。 2·如申晴專利範圍帛i項戶斤述之具有凸塊之晶圓結構,其 中該黏著層之材質係選自於由鈦、鎢、鈦鎢合金、鉻、 鋁、鈦鋁合金所組成族群中之一種材質。 如申明專利^圍第丨項所述之具有凸塊之晶圓結構,更 形成一銲料凸塊於潤濕層上。 如申明專利範圍第i項所述之具有凸塊之晶圓結構,其 中該保護層之材質係包含聚亞醯胺(P〇lyimide,PI)。 5·如申請專利範圍第1項所述之具有凸塊之晶圓結構,其 中該保護層之材質係包含苯併環丁烯 12 1258195 (Benzocyclobutene,BCB)。 6. 如申請專利範圍第1項所述之具有凸塊之晶圓結構,其 中該黏著層係為鈦金屬層/铭金屬層兩層結構。 7. 如申請專利範圍第1項所述之具有凸塊之晶圓結構,其 中該潤濕層之材質係選自於由銅、鉻銅及銅合金所組成 族群中之一種材質。 131258195 X. Patent application scope: h—a wafer structure having a bump, comprising: an active surface; a plurality of wafer pads disposed on the active surface; a protective layer disposed on the active surface and having a plurality of openings exposing the wafer pads; and a plurality of ball-bottom metal layers disposed on the wafer pads and each of the ball-bottom metal layers respectively comprise an adhesive layer and a titanium-copper alloy layer And a wetting layer, the adhesive layer is connected to the wafer pad, and the titanium-copper alloy layer is disposed on the adhesive layer, and the wetting layer is disposed on the titanium-copper alloy layer. 2. For example, the patent structure of Shen Qing is a bump structure, wherein the material of the adhesive layer is selected from titanium, tungsten, titanium tungsten alloy, chromium, aluminum, titanium aluminum alloy. A material in a group. A bumped wafer structure as described in the above patent, further forming a solder bump on the wetting layer. A wafer structure having a bump as described in claim i, wherein the material of the protective layer comprises polyphthalamide (PI). 5. The bumped wafer structure of claim 1, wherein the material of the protective layer comprises benzocyclobutene 12 1258195 (Benzocyclobutene, BCB). 6. The bumped wafer structure of claim 1, wherein the adhesive layer is a two-layer structure of a titanium metal layer/a metal layer. 7. The bumped wafer structure of claim 1, wherein the material of the wetting layer is selected from the group consisting of copper, chrome copper and copper alloy. 13
TW094100565A 2005-01-07 2005-01-07 Bumped wafer structure TWI258195B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW094100565A TWI258195B (en) 2005-01-07 2005-01-07 Bumped wafer structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094100565A TWI258195B (en) 2005-01-07 2005-01-07 Bumped wafer structure

Publications (2)

Publication Number Publication Date
TWI258195B true TWI258195B (en) 2006-07-11
TW200625481A TW200625481A (en) 2006-07-16

Family

ID=37765189

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094100565A TWI258195B (en) 2005-01-07 2005-01-07 Bumped wafer structure

Country Status (1)

Country Link
TW (1) TWI258195B (en)

Also Published As

Publication number Publication date
TW200625481A (en) 2006-07-16

Similar Documents

Publication Publication Date Title
JP6352205B2 (en) Structure for bonding intermetallic compounds on copper pillar bumps
US5937320A (en) Barrier layers for electroplated SnPb eutectic solder joints
KR100876485B1 (en) MBM layer enables the use of high solder content solder bumps
JP4051893B2 (en) Electronics
TWI231555B (en) Wafer level package and fabrication process thereof
JP4778444B2 (en) Semiconductor device and manufacturing method thereof, wiring board and manufacturing method thereof, semiconductor package and electronic device
US8847387B2 (en) Robust joint structure for flip-chip bonding
US20050017376A1 (en) IC chip with improved pillar bumps
TWI230450B (en) Under bump metallurgy structure
TW200427040A (en) Chip structure and method for fabricating the same
US6819002B2 (en) Under-ball-metallurgy layer
TWI281718B (en) Bump and process thereof
JPWO2006064534A1 (en) Semiconductor device
TW589727B (en) Bumping structure and fabrication process thereof
TWI223883B (en) Under bump metallurgy structure
TW583759B (en) Under bump metallurgy and flip chip
TWI258195B (en) Bumped wafer structure
US20040065949A1 (en) [solder bump]
TWI502706B (en) Robust joint structure for flip-chip bonding
US6875683B2 (en) Method of forming bump
TWI478312B (en) Stack package substrate
KR101009192B1 (en) Bump structure for semiconductor device and fabrication method thereof
TWI249211B (en) Bump structure
TWI262567B (en) Bumped wafer structure
TWI237860B (en) Integrated chip structure for wire bonding and flip chip assembly package and fabrication process thereof