TW200409230A - Method for avoiding non-uniform etching of silicon layer - Google Patents
Method for avoiding non-uniform etching of silicon layer Download PDFInfo
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- TW200409230A TW200409230A TW091134675A TW91134675A TW200409230A TW 200409230 A TW200409230 A TW 200409230A TW 091134675 A TW091134675 A TW 091134675A TW 91134675 A TW91134675 A TW 91134675A TW 200409230 A TW200409230 A TW 200409230A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 83
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 83
- 239000010703 silicon Substances 0.000 title claims abstract description 83
- 238000005530 etching Methods 0.000 title claims abstract description 79
- 238000000034 method Methods 0.000 title claims abstract description 68
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 12
- 239000007789 gas Substances 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 239000004575 stone Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 7
- 241000735576 Felicia Species 0.000 description 3
- 125000005843 halogen group Chemical group 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical compound [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910052776 Thorium Inorganic materials 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- -1 c12 Chemical compound 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Description
200409230 s*、發明說明(1) 【發明所屬之技術領域】 本發明係有關於一種蝕刻矽層的方 於-種避免矽層蝕刻不均句的方法。 且特別疋有關 【先前技術】 矽材質係目前極為普遍使用之半導體材料。1956 一顆半導體κ問世後’多年來碎在我們的生活中已益所^ J。各類型電腦中的記憶體、微處理@ 電源供應器當中,無一不用到IC,而手機、計算機、電: 遊樂器、微波爐…等各種電子產品也一樣。不僅如此,曰 趨蓬勃發展的薄膜電晶體液晶顯示器(thill filin transistor liquid crystal display ;m LCD)也必須 借重於矽,始能發揮其功效。 、 目前各種電子元件的製作通常是經過一連串的清洗、 /儿積、微影、蚀刻…等程序而製得。然而,當石夕在钱刻時 往往會有厚度不均勻的問題發生。由於目前常用的石夕餘刻 劑之主要阻成為H C X ’ X係指鹵素族元素,例如··敦(f )、氣 (C1 )、演(Br)…等,而以這些含有鹵素族元素之蝕刻劑對 石夕進行第一次蝕刻程序1 40以進行圖案化時,如第丨A圖所 示,往往會有Six0yClz之殘留物1〇6形成於圖案化矽層1〇2a 侧壁,而Six〇yClz殘留物106具極佳之化學穩定性。因此, 請再參考第1B圖,當去除光阻1〇4後,欲將圖案化石夕層 10 2a進一步利用一第二次蝕刻程序丨5〇以減少厚度蝕時, Six〇yClz殘留物1〇6便如同硬罩幕(hard mask)般,會防止 圖案化石夕層1 〇 2 a側壁被餘刻,如此一來,便無法均勻地減
200409230 五、發明說明(2) 案化珍層102a的厚度,而形成圖案化矽層102a側壁較 厚且頂部較薄的不均勻輪廓。 鑑於此,為了解決上述問題,本發明主要目的在於 μ: ^種避免矽層蝕刻不均勻的方法,可適用於各種矽層 的蚀刻。 【發明内容】 本發明之目的在於提供一種避免矽層蝕 法,可使石夕層均句地敍刻至—既定厚度。 Ί的方 餘刻ίH 1主要特徵在於順應性形成一抗蝕刻能力佳的 勹1担说θ歹*如··氧化矽)於矽層表面與側壁上,用以均 -餘刻阻力,使整個基底的 用一? 整個義底f f t厚度。並且,該蝕刻緩衝層可利用將 登個基底實I含氧氣體處理程序而製得。 均勺上!^目的,本發明提出一種避免矽層蝕刻不 均勾的方法,此方法的步驟主要係包括: 』不 首先,提供一矽層。接著, 幕層於上述矽層之部分 乂 ,、有預疋圖案之罩 ,實施-第-次餘刻;上述罩幕層為遮蔽 層。然後’去除上述罩幕声。^:二形成-圖案化矽 衝層於上述圖案化矽# & ^ ,順應性形成一蝕刻緩 -第二次蝕表面與側壁上。最後,☆面性施行 述圖案化矽層,使上:::除上述蝕刻緩衝層,且蝕刻上 根據本發明,上述第乂減:至-既定厚度。 義上述㈣之圖案心二人=;=主要目的在於定 弟-人蝕刻耘序之蝕刻劑包括 第6頁 〇632.8795TlF(n);AU91207;Felicia.ptd 200409230 五、發明說明(3) Η等C?X係指i素族元素,例如:_)、氣(ci)、⑽。… 使上居第二次㈣程序之主要目的係在於 有一均句之特定厚度。上述第二次蝕 刻程序所使用之蝕刻劑包括Cl2、SF6或肋!·。 如則所述,上述罩幕層可為光阻層(photoresist ayer)。並且,上述蝕刻緩衝層之材質包括氧化矽,係利 用^施一含氧氣體處理程序以進行氧化法而形成。上述蝕 刻緩衝層的厚度大體為5〜2〇 nm。並且,上述矽層的厚度大 體為120〜250nm。上述含氧氣體大體為9〇%〜99%氧氣與又 10〜1%第二次蝕刻程序之蝕刻劑,其施行溫度約為30〜50〇C 〇 為使本發明之上述目的、特徵和優點能更明顯易懂, 下文特舉較佳實施例,並配合所附圖式,作詳細說明如下 【實施方式】 以下請配合參照第2 A圖至第2F圖,說明根據本發明之 矽層蝕刻方法之一較佳實施例。 首先’請參考第2A圖,先提供一梦層202,其厚度約 為120〜250 nm。該矽層202可能應用於半導體之基底或薄膜 電晶體(thin film transistor ; TFT)之活性層(active layer),甚至任何可能應用矽材質之領域,在此並不加以 設限,且石夕層202可以視需求而設置於任何可能之基底2〇〇 表面。
0632-8795TW(n);AU91207;Felicia.ptd
200409230
接著,請參考第2B圖,先在矽層202表面形成一罩幕 層於碎層202之部分表面,例如利用旋塗法(sp 土 n coat iong)形成一光阻層(photoresist layer)做為罩幕層 。再圖案化罩幕層,例如利用適當之微影程序,將光阻^ 圖案化,以形成一圖案化光阻層2 〇 4。 接著’請參考第2C圖,以圖案化光阻層2〇4為遮蔽, 實施一第一次餘刻程序5 00於矽層20 2,以形成一圖案化石夕 層20 2a。第一次蝕刻程序5〇〇之主要目的在於定義声 之圖案,其蝕刻劑包括HCX,X係指鹵素族元素,例如7氟 (F)、氣(C1)、溴(Br)…等,而以這些含有齒素族元素之 餘刻劑對矽進行蝕刻,往往會有含有_素族元素之矽氧化 殘留物生成,其中以含有氣元素之蝕刻劑為例,則易有 仏〇/込之殘留物206形成於圖案化矽層202a侧壁,而 SixOyClz殘留物206極為穩定,當後續欲將圖案化矽層2〇2a 再進一步利用一第二次蝕刻程序以減少厚度時,s込〇yClz 殘留物206便如同硬罩幕(hard mask)般,會防止圖案化石夕 層2 0 2 a侧壁被钱刻,如此一來,便無法均勻地減少圖案化 矽層20 2a的厚度。 接著’可利用適當溶液去除圖案化光阻層204,如第 2D圖所示。 接著,此步驟為本發明之主要特徵,在進行一第二次 石夕厚度钱刻之前’可先藉由在姓刻反應室内部實施一含氧 氣體處理程序6 0 0 ’如第2 D圖所示。再請參照第2 £圖,以 順應性形成一氧化矽層2 08於圖案化矽層2〇2a表面與側壁
200409230 五、發明說明(5) 上’以做為蝕刻緩衝層。氧化矽蝕刻緩衝層208對後續第 二次#刻程序之蝕刻劑之抗蝕刻能力佳,係為難蝕刻材 質’其厚度約為5〜20nm。含氧氣體可包括90%〜9 9%之氧氣 與1 0〜1 %之第二次蝕刻程序之蝕刻劑,其施行溫度例如為 30〜50oC 〇 最後,全面性施行一第二次餘刻程序7 〇 〇,不僅去除 氧化矽蝕刻緩衝層208,且蝕刻圖案化矽層202a,使圖案 化矽層202a減少至一既定厚度,請參考第2F圖。由於氧化 矽餘刻緩衝層208對所述第二次蝕刻程序700之蝕刻劑义抗 蝕刻能力佳,可均勻地提供一蝕刻阻力,使整個基底的蝕 刻速率均勻一致,可均勻地減少案化矽層2 〇 2 a的厚度。根 據本發明’第一次餘刻程序7〇〇之主要目的係在於使圖案 化矽層202a具有一均勻之既定厚度。第二次蝕刻程序7〇〇 所使用之蝕刻劑必需能蝕刻矽與氧化矽,包括c l2、SF HBr。 本發明雖以較佳實施例揭露如上,然其並非用以限定 本發明的範圍,任何熟習此項技藝者,在不脫離本發明之 精神和範圍内,當可做各種的更動與潤飾,因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。
0632-87951W(n);AU91207;Fclicia.ptd 第9頁 200409230 圖式簡單說明 、b _係顯示習知矽蝕刻時所遭遇到的厚度 ' >音圖。 蝕刻不均勻問題之$〜 第2A圖至第2F圖 矽顯示根據本發明之矽蚀刻方法之一 較佳實施例之製程剖面圖。 【符號說明】 1 0 0、2 0 0〜基底; 1 0 4〜光阻; 140〜第一次蝕刻程序; 2 0 2〜矽層; 5 0 0〜第一次餘刻輕序· 600〜含氧氣體處理輕序 7 0 0〜第二次餘刻程序。 1 02a〜矽層; 106、20 6〜Six0yClz 殘留物; 150〜第二次蝕刻程序; 204〜圖案化光阻層; 20 2a〜圖案化矽層; 2 0 8〜氧化矽蝕刻緩衝層;
0632-8795TWF(n);AU91207;Felicia.ptd 第10頁
Claims (1)
- 200409230 六、申請專利範圍 1 · 一種避免矽層蝕刻不均勻的方法,包括·· 提供一圖案化矽層; 順應性形成一蝕刻緩衝層於上述圖案化矽層表面與側 壁上;以及 全面性施行一蝕刻程序,不僅去除上述蝕刻緩衝層, 且餘刻上述圖案化矽層,使上述圖案化矽層減少至一既定 厚度。 2 ·如申請專利範圍第1項所述之避免矽層蝕刻不均勻 的方法’其中上述蝕刻緩衝層包括氧化矽(s i % )。3 ·如申請專利範圍第2項所述之避免矽層蝕刻不均勻 的方法’其中上述蝕刻緩衝層係利用氧化法形成。 4 ·如申請專利範圍第1項所述之避免石夕層蝕刻不均勻 的方法’其中上述蝕刻程序所使用之蝕刻劑包括C12、sf6 或HBr 〇 5 ·如申請專利範圍第1項所述之避免矽層蝕刻不均勻 的方法’其中上述蝕刻緩衝層的厚度大體為5〜2〇随。 6 ·如申請專利範圍第!項所述之避免矽層蝕刻不均勻 的方法’其中上述矽層的厚度大體為12〇〜25〇11111。 7 · —種避免石夕層钱刻不均勻的方法,包括·· 提供一矽層;形成一具有預定圖案之罩幕層於上述矽層之 ; °丨刀表面 以上述罩幕層為遮蔽,實施一第一次蝕刻程 矽層,以形成一圖案化矽層; 於上述q Q C 200409230 六、申請專利範圍 去除上述罩幕層; 順應性形成一蝕刻緩衝層於上述圖案化矽層 壁上;以及 ,、1只J 衝層行—第二次㈣程序,不僅去除上述钱刻緩 : 丨上述圖案化矽層,使上述圖案化矽層減少至一 既定厚度。 8、·如申請專利範圍第7項所述之避免矽層蝕刻不均勻 、法’其中上述罩幕層係為光阻(phot ores i st)層。 9 ·如申請專利範圍第7項所述之避免矽層蝕刻不均勻 的方法,其中上述蝕刻緩衝層包括氧化矽。 10·如申請專利範圍第9項所述之避免矽層蝕刻不均勻 的方法,其 '上述蝕刻緩衝層係利用氧化法形成。 1、1 ·如申請專利範圍第7項所述之避免矽層蝕刻不均 法,其中上述第二次蝕刻程序所使用之蝕刻劑包括 Cl2、SF6或·。 匕枯 12·如申請專利範圍第7項所述之避免矽層蝕刻不均 ’法’其中上述餘刻緩衡層的厚度大體為5〜2 Onm。 丨、3 ·如申凊專利範圍第7項所述之避免矽層蝕刻不 、方法,其中上述矽層的厚度大體為12〇〜25〇nm。 14· 一種避免矽層蝕刻不均勻的方法,包括: 提供一碎層; .形成一具有預定圖案之罩幕層於上述矽層之部分表面 9 以上述罩幕層為遮蔽,實施一第一次蝕刻程序於上述0632-8795TW(n);AU91207;Fclicia.ptd 第12頁 200409230六、申請專利範圍 矽層,以形成一圖案化矽層; 去除上述罩幕層; 實施一含氧氣體處理程序於上述圖案化矽層表面, 順應性形成一氧化梦層於上述圖案化石夕層表面與側壁上 以及 全面性施行一第二次蝕刻程序,不僅去除上述氧化石 層’且餘刻上述圖案化碎層,使上述圖案化石夕層具有一 定厚度。 —既 1 5 ·如申請專利範圍第丨4項所述之避免矽層蝕刻不均 勻的方法,其中上述罩幕層係為光阻(photoresist)層。 1 6 ·如申請專利範圍第丨4項所述之避免矽層蝕刻不均 勻的方法’其中上述第二次蝕刻程序所使用之蝕刻劑包括 Cl2、SF6 或HBr。 1 7 ·如申請專利範圍第丨4項所述之避免矽層蝕刻不均 句的方法’其中上述氧化矽層的厚度大體為5〜2〇11111。 1 8 ·如申請專利範圍第1 4項所述之避免矽層蝕刻不均 句的方法’其中上述矽層的厚度大體為12〇〜25〇 ηιη。 _ 1 9 ·如申請專利範圍第1 4項所述之避免矽層蝕刻不均 句的方法’其中上述含氧氣體處理程序所使用之氣體大體 為9 0%〜9 9%氧=與1〇〜1%第二次蝕刻程序之蝕刻劑。 一 20 ·、如申請專利範圍第13項所述之避免矽層蝕刻不均 句的方法’其中上述含氧氣體處理程序之溫度大體為
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US4613400A (en) * | 1985-05-20 | 1986-09-23 | Applied Materials, Inc. | In-situ photoresist capping process for plasma etching |
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