九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體製程，且特別是有關於一 種硬罩幕層與半導體元件的製造方法。 【先前技術】 在半導體的製程中’元件的尺寸不斷地微縮，使飿刻 選擇性（etching selectivity )與均勻度將變得更為重要。隨 著兀件的尺寸愈來愈小，光阻圖形及蝕刻圖形的深寬比 (aspect ratio)不斷增加，使得微影製程的困難度也持續 提向，造成元件尺寸的控制更加困難。 為了解決此問題，一般的半導體製程大都是使用介電 層的材料來取代光阻，以做為硬罩幕（hard mask)。在前 段製程（front end 〇f line，FEOL)中，用來定義隔離結構 或閑極結構（gate structure)的硬罩幕材料包括氧化矽、氮 b夕或鼠氧化碎荨。與光阻相比，硬罩幕具有較強的抗名虫 刻能力，因此能夠在蝕刻製程中更精確地的完成各階段的 圖案化製程（patterning)。然而，硬罩幕的抗蝕刻能力必 須繼續提高，使硬罩幕的厚度可以降低，以使進行圖案化 製程後的產品具有均一的品質，從而增加製程裕度及產品 的良率。 【發明内容】 有鏗於此，本發明之目的是提供一種硬罩幕層的製造 方&以k供具有南抗儀刻能力的硬罩幕。 5 129 本發明之再一目的是提供〆種半導體結構的製造方 法，以在前段製程中增加硬罩幕的抗蝕刻能力，從而增加 製程裕度及產品的良率。 _為達上述或是其他目的，本發明提出一種硬罩幕層的 製造方法。首先於基底上形成罩幕層，然後於罩幕層上形 f圖案化光阻層。圖案化光阻層具有數個開D ,這些開口 ^露部分罩幕層。移除部分罩幕層，以暴露開口下方的部 % 分基底。進行第一氧電漿處理製程，以移除部分圖案化光 阻層，並增加罩幕層的抗蝕刻性。接著，進行第二氧電漿 處理製程，以移除殘留的圖案化光阻層。 ^本發明之—實施例中，上述之第—氧電漿處理製程 例如是臨場進行的。 ίϊ發明之-實施例中’上述之第—氧電漿處理製程 的反應室的氣體壓力例如是80〜120毫托。 沾〆明之一貫施例中，上述之第一氧電漿處理製程 的虱乳^量例如是900〜1100立方公分/每分鐘。 的明之一貫施例中，上述之第—氧電漿處理製程 的功率例如是1800〜2200瓦。 的時，之—實施例中，上述之第—氧電漿處理製程 的％間例如是25〜35秒。 在本發明之一實施例中，上述之置篡 氮化石夕或氧切。 ^之罩幕層的材質例如是 ，本發明之一實施例中，上述之第二氧電 例如疋在灰化機中進行灰化製程。 、 mmL· 由於本發明在去除圖案化光阻層之前 電漿處理製程來增加罩幕層的抗餘刻能力，因此 罩幕層的厚度’且_此罩幕層來對其轉料騎圖宰化 程（pattenng)可以精雜控制材料的關鍵尺寸㈤加 謹）。此外’第一氧電漿處理製程是臨場& ^ ’只要在同-侧機台’增加第—氧電漿 呈 的步驟就可以達到增加罩幕層的抗_能力的目的，因此 本發明之硬罩幕層的製造方法也較為簡單。 杜^達上述或是其他目的，本發明再提出—種半導體元 、，造方法。首先於材料層上形成一層罩幕層，然後， 於罩幕層上形成-層圖案化光阻層。圖案化光阻層具有數 個開口，且這些開口暴露部分罩幕層。之後，移除部分罩 幕層’以暴路開口下方的部分材料層。進行抗儀刻處理， 以增加罩幕層“抗侧性。之後，先移除圖案化光阻層， 再移除部分材料層。 曰在本發明之一實施例中，上述之抗蝕刻處理例如是臨 場進行的。 $。在本發明之一實施例中，上述之抗蝕刻處理例如是氧 ，電漿製程。此外，抗蝕刻處理的反應室的氣體壓力例如 疋8〇〜120毫托。抗蝕刻處理的氧氣流量例如是900〜1100 立方公分/每分鐘，功率例如是18〇〇〜22⑻瓦，處理的時 間例如是25〜35秒。 ^ 在本發明之一實施例中，上述之罩幕層的材質例如是 氮化矽或氧化矽。IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD The present invention relates to a semiconductor process, and more particularly to a method of fabricating a hard mask layer and a semiconductor device. [Prior Art] In the process of semiconductors, the size of the elements is continuously reduced, so that etching selectivity and uniformity will become more important. As the size of the element is getting smaller and smaller, the aspect ratio of the resist pattern and the etched pattern is increasing, which makes the difficulty of the lithography process continue to be raised, making the control of the component size more difficult. In order to solve this problem, the general semiconductor process mostly uses a material of a dielectric layer instead of a photoresist as a hard mask. In the front end 〇f line (FEOL), the hard mask material used to define the isolation structure or the gate structure includes cerium oxide, nitrogen b. or oxidized mash. Compared with the photoresist, the hard mask has a strong resistance to engraving, so that the patterning of each stage can be more accurately performed in the etching process. However, the etch resistance of the hard mask must continue to increase, so that the thickness of the hard mask can be reduced to provide a uniform quality of the product after the patterning process, thereby increasing process margin and product yield. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a hard mask layer manufacturer and a hard mask having a south resistance capability. 5 129 A further object of the present invention is to provide a method of fabricating a semiconductor structure to increase the etching resistance of the hard mask during the front-end process, thereby increasing process margin and product yield. For the above or other purposes, the present invention provides a method of manufacturing a hard mask layer. First, a mask layer is formed on the substrate, and then a photoresist layer is patterned on the mask layer. The patterned photoresist layer has a plurality of openings D that expose a portion of the mask layer. Part of the mask layer is removed to expose the portion of the substrate below the opening. A first oxygen plasma treatment process is performed to remove a portion of the patterned photoresist layer and increase the etch resistance of the mask layer. Next, a second oxygen plasma processing process is performed to remove the residual patterned photoresist layer. In the embodiment of the invention, the above-described first oxygen plasma treatment process is carried out, for example, on site. In the embodiment of the invention, the gas pressure of the reaction chamber of the above-described first-oxygen plasma treatment process is, for example, 80 to 120 mTorr. In the consistent application of Zhan Yuming, the amount of the first oxygen plasma treatment process is, for example, 900 to 1100 cubic centimeters per minute. In the consistent embodiment of the invention, the power of the above-mentioned first-oxygen plasma treatment process is, for example, 1800 to 2200 watts. In the embodiment, the % of the above-mentioned first oxygen plasma treatment process is, for example, 25 to 35 seconds. In one embodiment of the invention, the above is set by nitriding or oxygen cutting. The material of the mask layer is, for example, in one embodiment of the invention, wherein the second oxygen source, for example, is subjected to an ashing process in the ashing machine. , mmL· Since the present invention removes the patterned photoresist layer before the plasma treatment process to increase the anti-removal ability of the mask layer, the thickness of the mask layer is 'and the mask layer is used to transfer it to the wafer. The process (pattenng) can be used to control the critical dimensions of the material (5) plus). In addition, the 'first oxygen plasma treatment process is on-the-spot & ^ ' as long as the step of adding the first oxygen plasma in the same side machine can increase the resistance of the mask layer, so the present invention The manufacturing method of the hard mask layer is also relatively simple. For the above or other purposes, the present invention further proposes a semiconductor element and a method of fabrication. First, a mask layer is formed on the material layer, and then a layer-patterned photoresist layer is formed on the mask layer. The patterned photoresist layer has a plurality of openings and these openings expose a portion of the mask layer. Thereafter, a portion of the cover layer is removed as a portion of the material layer below the stormway opening. An anti-etching treatment is performed to increase the mask layer "side resistance. Thereafter, the patterned photoresist layer is removed, and then a portion of the material layer is removed. In an embodiment of the present invention, the above-described etching resistance treatment is performed, for example. In one embodiment of the present invention, the anti-etching treatment is, for example, an oxygen, plasma process. Further, the gas pressure of the reaction chamber resistant to etching treatment is, for example, 〇8〇~120 mTorr. The oxygen flow rate of the etching treatment is, for example, 900 to 1100 cubic centimeters per minute, and the power is, for example, 18 to 22 (8) watts, and the processing time is, for example, 25 to 35 seconds. ^ In an embodiment of the present invention, the mask is The material of the layer is, for example, tantalum nitride or tantalum oxide.
1291205 19051twf.doc/e θ本發明之—實施例中，上述之移除圖案化光阻層例 如疋在灰化機中進行灰化製程。 在本發明之-實施例中，上述之移除部分材料層的步 驟使材料層巾形㈣渠，且此絲形叙後更包括於溝渠 中/成；I電層_後移除罩幕層，以形成淺溝渠隔離結構。 在本發明之一實施例中，上述之材料層例如是矽基 底$體材料及介電材料，且移除部分材料層的步驟使材 料層成為閘極結構。 ^由於本發明利用抗蝕刻處理來增加罩幕層的抗蝕刻 月b力因此在蝕刻材料層之後，罩幕層的殘留量（mask remaining)較兩’使钱刻之後的材料層圖案更為精確。此 外:因為增加了罩幕層的抗蝕刻能力，所以能夠以較薄的 罩幕層來蝕刻材料層，換言之，罩幕層具有較小的深寬比 (aspect rati〇 )，使蝕刻材料層的製程裕度（ window)更高。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 【第一實施例】 圖1A至圖1C是本發明一實施例的一種硬罩幕層的製 造方法流程剖面圖。圖2是上述之硬罩幕層的製造方法步 驟流程圖。 8 1291205 19051twf.doc/e 睛同時芩照圖1A及圖2，本發明的硬罩幕的製造方 法是依序進行步驟200至步驟208。首先進行步驟2〇〇 :於 基底100上形成一層罩幕層1〇2。基底1〇〇例如是矽基的 片(s:iliC0n-based)基底。罩幕層1〇2的材質例如是氮化矽或 氧化石夕，且罩幕層1〇2的形成方法例如是化學氣相沈積 法。然後，進行步驟202 :於罩幕層102上形成一層圖案 化光阻層104’圖案化光阻層1〇4具有數個開口 1〇6。這些 開口 106暴露部分罩幕層1〇2。圖案化光阻層刚的形^ 方法例如是半導體業界所常用的光學微影製程。 然，，請同時參照圖1B及圖2，進行步驟2〇4 :移除 部分罩幕層102,以暴露這些開σ廳下方的部分基底 100。移除部分罩幕層1()2的方法例如是非等向性钱刻製 程。接著’進行步驟206:進行第一氧電漿處理製程1〇8， 移除部分圖案化光阻層刚，並增加罩幕層逝的抗侧 性ϋ電漿處理製程1()8例如是臨場進行的，換言之， 步驟施與步驟綱是在同—個關反應室（etching 咖mber)祕刻機台進行。當然，第―氧電漿處理製程 108也可以是非臨場進行的。 亡匕外J第-氧電漿處理製程1〇8例如是氧氣電漿製 粒。，-氧電漿處理製程1〇8的參數範圍包括：氣體壓力 例如疋80〜12G毫托的反應室氣體壓力、氧氣流量例如是 900 110G立方公分/每分鐘、功率例如是⑻〜瓦； 時間例如是25〜35秒。 在-較佳貫施例中，第一氧電漿處理製程1〇8的參數 1291205 】9051twf.doc/e ，例如是100亳托的反應室氣體壓力、1000立方公分/每 ^鐘的氧氣流量、2000瓦的功率、30秒的時間。另一刀方面， 第一氧電漿處理製程⑽的反應室兩電極距離例如是40 公厘，且晶圓背部冷卻系統例如是以1〇托的晶背氣體壓 ^在曰^心與晶圓進行熱交換;並以2〇托的晶背氣體 土力’在晶圓邊緣與晶圓進行熱交換。 ，之，請同時參照圖1B、1C與圖2，首先，值得一提的 疋’在步驟206中’第一氧電漿處理製程108會移除大部 分=圖案化光阻層1G4 ’使圖1B的結構在經過步驟版 =後，罩幕層102上會殘留-層高分子材料層11〇。高分 :材=層no使罩幕層逝具有更好的抗钱刻能力。隨後， 進仃>驟208 .進行第二氧電漿處理製程112，以移除殘留 ，圖案化光阻層綱。第二氧電漿處理製程U2例如是在 灰化機（asher)中進行灰化（ashing)製程。 本發明在去除圖案化光阻層之前，先進行第一氧電衆 處理^程，再進行第二氧電漿處理製程，使光阻在完全去 除之所’增加罩幕層的抗钱刻能力。因此，可以增加後續 银刻製程的製程裕度，麟確地控侧鍵尺寸。 【弟二實施例】 圖3A至圖3D是本發明—實施例的一種半導體元件 的製造方法流程剖面圖。 请麥照圖3A，首先，於材料層上形成一層罩幕 層302。材料層3()()例如切基的⑽·材料層。 罩幕層302的材質例如是氮化發或氧切，且罩幕層3〇2 10 I29m-e 的形成方法例如是化學氣相沈積法。然後，方、'1291205 19051twf.doc/e θ In the embodiment of the invention, the above-described removal of the patterned photoresist layer, such as ruthenium, is performed in an ashing machine. In the embodiment of the present invention, the step of removing a portion of the material layer causes the material layer to form a (four) channel, and the wire shape is further included in the trench; the electrical layer _ after removing the mask layer To form a shallow trench isolation structure. In one embodiment of the invention, the material layer is, for example, a base material and a dielectric material, and the step of removing a portion of the material layer causes the material layer to be a gate structure. Since the present invention utilizes an anti-etching treatment to increase the etching resistive b-force of the mask layer, the mask remaining of the mask layer is more precise than the pattern of the material layer after the etching. . In addition: because the etching resistance of the mask layer is increased, the material layer can be etched with a thin mask layer, in other words, the mask layer has a small aspect ratio, so that the etching material layer The process margin is higher. The above and other objects, features and advantages of the present invention will become more <RTIgt; [Embodiment] FIG. 1A to FIG. 1C are cross-sectional views showing a flow of a method for manufacturing a hard mask layer according to an embodiment of the present invention. Fig. 2 is a flow chart showing the steps of the above-described method of manufacturing the hard mask layer. 8 1291205 19051twf.doc/e Eyes Referring to Figures 1A and 2 simultaneously, the method of manufacturing the hard mask of the present invention is to perform steps 200 through 208 in sequence. First, step 2 is performed: a mask layer 1〇2 is formed on the substrate 100. The substrate 1 is, for example, a sulfonium-based (s: iliC0n-based) substrate. The material of the mask layer 1〇2 is, for example, tantalum nitride or oxidized stone, and the method of forming the mask layer 1〇2 is, for example, a chemical vapor deposition method. Then, step 202 is performed: forming a patterned photoresist layer 104' on the mask layer 102. The patterned photoresist layer 1〇4 has a plurality of openings 1〇6. These openings 106 expose a portion of the mask layer 1〇2. The method of patterning the photoresist layer is, for example, an optical lithography process commonly used in the semiconductor industry. However, referring to FIG. 1B and FIG. 2 simultaneously, step 2〇4 is performed: a part of the mask layer 102 is removed to expose a part of the substrate 100 below the opening hall. The method of removing a part of the mask layer 1 () 2 is, for example, an anisotropic engraving process. Then, proceed to step 206: performing a first oxygen plasma treatment process 1〇8, removing a portion of the patterned photoresist layer, and increasing the lateral resistance of the mask layer. The plasma processing process 1 () 8 is, for example, on the spot. In progress, in other words, the step-by-step procedure is carried out in the same-etching chamber (etching café) secret engraving machine. Of course, the first-oxygen plasma processing process 108 can also be performed on-site. The J-oxygen plasma treatment process 1 〇 8 is, for example, an oxygen plasma granulation. The parameter range of the oxygen plasma treatment process 1〇8 includes: a gas pressure such as a reaction chamber gas pressure of 疋80 to 12 G mTorr, an oxygen flow rate of, for example, 900 110 Gcm/min, and a power of, for example, (8) watts; For example, it is 25 to 35 seconds. In the preferred embodiment, the first oxygen plasma treatment process 1 〇 8 parameter 129125 】 9051 twf. doc / e, for example, 100 Torr of the reaction chamber gas pressure, 1000 cubic centimeters / per hour of oxygen flow 2000 watts of power, 30 seconds. On the other hand side, the distance between the two electrodes of the reaction chamber of the first oxygen plasma treatment process (10) is, for example, 40 mm, and the back cooling system of the wafer is, for example, a crystal back gas pressure of 1 Torr. Heat exchange; and heat exchange at the edge of the wafer with the wafer at a gas backing force of 2 Torr. Referring to FIG. 1B, FIG. 1C and FIG. 2 simultaneously, firstly, it is worth mentioning that 'in step 206, the first oxygen plasma processing process 108 removes most of the = patterned photoresist layer 1G4'. After the step 1 of the structure of 1B, a layer of the polymer material layer 11 is left on the mask layer 102. High score: material = layer no makes the mask layer have better resistance to money. Subsequently, the second oxygen plasma treatment process 112 is performed to remove the residual, patterned photoresist layer. The second oxygen plasma treatment process U2 is, for example, an ashing process in an asher. Before the removal of the patterned photoresist layer, the first oxygen electricity treatment process is performed, and then the second oxygen plasma treatment process is performed, so that the photoresist is completely removed to increase the resistance of the mask layer. . Therefore, the process margin of the subsequent silver engraving process can be increased, and the side key size can be controlled. [Second Embodiment] Figs. 3A to 3D are cross-sectional views showing the flow of a method of manufacturing a semiconductor device according to an embodiment of the present invention. Referring to Figure 3A, first, a mask layer 302 is formed on the material layer. The material layer 3()() is, for example, a (10) material layer of the base. The material of the mask layer 302 is, for example, nitrided or oxygen cut, and the method of forming the mask layer 3〇2 10 I29m-e is, for example, a chemical vapor deposition method. Then, party, '
上形成—層圖案化級層綱，®案化光阻居 個開口 306。i言此閱Γ7 O A, B_ 一 曰 ^ 丁曰口，換言之， 抗钱刻處理308與上述之非等向性钱刻製程是在同二個姓 刻反應室或姓刻機台進行。由於姓刻反應室的内壁通常旦 有含碳成分的副產物，且這些副產物會與抗敍刻^里3〇8 的氧氣產生反應而被清除，因此以臨場的方式進行抗钱刻 處理308可以清潔蝕刻反應室。當然，抗蝕刻處理3〇8也 可以是非臨場進行的。此外，抗蝕刻處理3〇8例如是氧氣 鲁 電漿製程。另外，抗餘刻處理308的參數範圍包括：反應 至氣體壓力例如疋80〜120毫托，氧氣流量例如是9q〇〜11〇〇 立方公分/每分鐘、功率例如是1800〜2200瓦；時間例如 是25〜35秒。在一較佳實施例中，抗蝕刻處理3〇8的參數 值分別為1〇〇宅托的反應室氣體壓力、1〇〇〇立方公分/每 分鐘的氧氣流量、2000瓦的功率、30秒的時間。另一方面， 抗姓刻處理308的反應室兩電極距離例如是4〇公厘，且晶 圓背部冷卻糸統例如疋以1 〇把的晶背氣體屢力，在晶圓中 11 129观 doc/e …、曰曰圓進行熱交 以 邊緣與晶圓進行熱交換。 〕堡力’在晶圓 繼之，睛同時參照圖3C ,值得一提的是， ，308會移除大部分的圖案化光阻層3 =刻處 t經過抗蝴處理3⑽之後，罩幕層搬i會殘^吉構 層/1〇。高分子材料層310與罩幕層3〇2 ^ Γ2 ’硬罩幕312可以用來做為_材料】· 、 。由於形成有高分子材料層310，因此硬罩^ 於罩幕層302 _刻能力。因為ί知= 做為硬罩幕，所以本一 selec祕y)。隨4對==的㈣選擇性（卿ng 朵阻厚L ^移除圖案化光阻層304。移除圖案化 g 々方法例如是在灰化機中進行灰化|y斤 後，請同時參照圖3D，移除部分 “ j =例如是非等向性侧製程。 中，二二二在數種半導體前段製程 貫施例來說明這些應用方式。 數们 圖3E疋本發明—實施例之圖3D的後續製程剖面 ❺芩照圖3E，在移除部分材料層3〇〇之後，在硬罩幕μ 之間的材料層300中形成溝渠314。之後，在溝渠314之 中形成淺溝渠隔離結構灿。淺溝渠隔離結構灿的 方法例如是在材料層3〇〇上形成-介電層（未緣示），覆 盍材料層3〇0、溝渠叫及硬罩幕犯。此介電層例如是以 12 1291?氣.“ 2密度電漿(HDP)化學氣相沈積法所形成的氧化石夕。接 者，依序進行化學機械研磨製程及回蝕刻製程，而形成之。 圖3E，是本發明一實施例之圖3D的後續製程剖面 圖。請同時參照圖3D與圖3E，，在本實施例中，材料層 、:00由下而上例如是由矽基底318、介電材料32〇與導體材 ，322所構成。介電材料32〇例如是以熱氧化法所例成的The upper layer is patterned to form a layer, and the photoresist is formed by an opening 306. i 此 Γ 7 O A, B_ 一 曰 ^ 丁曰口, in other words, the anti-money engraving process 308 and the above-mentioned anisotropic engraving process is carried out in the same two surnames of the reaction chamber or surname engraving machine. Since the inner wall of the reaction chamber of the surname usually has a by-product of carbonaceous components, and these by-products are removed by reacting with the oxygen of the anti-synthesis 3,8, the anti-scratch treatment is performed in a spot manner. The etching reaction chamber can be cleaned. Of course, the anti-etching treatment 3〇8 can also be performed on the spot. Further, the etching resist treatment 3〇8 is, for example, an oxygen plasma process. In addition, the parameter range of the anti-reception processing 308 includes: reacting to a gas pressure such as 疋80 to 120 mTorr, and the oxygen flow rate is, for example, 9q 〇 11 11 cm 3 /min, and the power is, for example, 1800 to 2200 watts; It is 25 to 35 seconds. In a preferred embodiment, the parameter values of the anti-etching treatment 3〇8 are respectively 1 chamber reaction chamber gas pressure, 1〇〇〇3 cm/min oxygen flow, 2000 watts power, 30 seconds. time. On the other hand, the distance between the two electrodes of the reaction chamber of the anti-surname processing 308 is, for example, 4 mm, and the backside of the wafer is cooled, for example, with a crystal back gas of 1 〇, in the wafer. /e ..., the circle is hot-crossed to exchange heat with the wafer at the edge. 】Bao Li' is followed by the wafer, and the eye is also referred to Figure 3C. It is worth mentioning that 308 will remove most of the patterned photoresist layer 3 = after the t-treatment 3 (10), the mask layer Moving i will be a residual ^ji layer / 1 〇. The polymer material layer 310 and the mask layer 3 〇 2 ^ Γ 2 ' hard mask 312 can be used as _materials. Since the polymer material layer 310 is formed, the hard mask is capable of engraving the mask layer 302. Because zhi know = as a hard mask, so this selec secret y). With 4 pairs of == (four) selectivity (clearing the thickness of L ^ remove the patterned photoresist layer 304. The method of removing the patterned g 々 is, for example, ashing in the ashing machine | Referring to FIG. 3D, the removed portion "j = is, for example, an anisotropic side process. In the middle, two 222 are described in several semiconductor front-end processes to illustrate these application modes. Figures 3E - The present invention - a diagram of an embodiment Subsequent Process Profile of 3D Referring to FIG. 3E, after removing a portion of the material layer 3, a trench 314 is formed in the material layer 300 between the hard masks μ. Thereafter, a shallow trench isolation structure is formed in the trench 314. The shallow trench isolation structure can be formed, for example, by forming a dielectric layer (not shown) on the material layer 3, a layer of the germanium material 3 〇 0, a trench and a hard mask. The dielectric layer is for example It is formed by a 12 1291 gas. "2D plasma chemical vapor deposition (HDP) chemical vapor deposition method, which is formed by sequential chemical mechanical polishing process and etchback process. Figure 3E is A cross-sectional view of the subsequent process of FIG. 3D according to an embodiment of the present invention. Please refer to FIG. 3D and FIG. 3E simultaneously, Embodiment, the material layer embodiment,: 00, for example, bottom 318, the dielectric material and the conductive material 32〇, substrate 322 composed of silicon-based dielectric material is exemplified 32〇 e.g. into thermal oxidation.
夕’而導體材料322例如是以臨場摻雜的化學氣相沉 ，法所形成的摻雜多晶矽。在移除部分材料層3〇〇之後， 會在硬罩幕犯之間的材料層3〇〇中形成溝渠別，並在 ，罩幕祀以下形成閘極結構324。其中，閘極結構Μ4 是由介電材料320與導體材料322構成。 由上述可知，本發明至少具有下列優點： 1·由於利用抗蝕刻處理來增加罩幕層的抗蝕刻能力， 因此在透過硬罩幕來蝕刻基底後，硬罩幕的殘留量可以大 幅增加，使蝕刻之後的材料層圖案更為精確。 2·由於增加了罩幕層的抗蝕刻能力，因此能夠以較薄 的罩幕層來蝕刻材料層，換言之，硬罩幕具有較 比，使侧材料層賴程裕度更高。 3·由於蝕刻反應室的内壁通常具有含碳成分的副產 物’且這些副產齡與抗侧處理的氧氣產生反應而被清 除，因此以臨場的方式進行抗蝕刻處理具有清潔蝕刻反應 室的效果。 〜 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 13 129職 doc/e 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A至圖1C是本發明一實施例的一種硬罩幕層的製 造方法流程剖面圖。 圖2是上述之硬罩幕層的製造方法步驟流程圖。 圖3A至圖3D是本發明一實施例的一種半導體元件的 製造方法流程剖面圖。 圖3E是本發明一實施例之圖3D的後續製程剖面圖。 圖3E’是本發明一實施例之圖3D的後續製程剖面圖。 【主要元件符號說明】 100 :基底 102、302 :罩幕層 104、304 :圖案化光阻層 106、306 :開口 108 ··第一電漿處理製程 110、310 :高分子材料層 112 ··第二電漿處理製程 200〜208 ··步驟 300 :材料層 308 :抗蝕刻處理 312 ··硬罩幕 14 129 職 _ 314 :溝渠 316 :淺溝渠隔離結構 318 :矽基底 320 :介電材料 322 :導體材料 324 :閘極結構The conductor material 322 is, for example, a doped polysilicon formed by a chemical vapor deposition method in the presence of a field. After removing a portion of the material layer 3, a trench is formed in the material layer 3〇〇 between the hard masks, and a gate structure 324 is formed below the mask. The gate structure Μ4 is composed of a dielectric material 320 and a conductor material 322. As can be seen from the above, the present invention has at least the following advantages: 1. Since the etching resistance of the mask layer is increased by the etching resistance treatment, the residual amount of the hard mask can be greatly increased after the substrate is etched through the hard mask. The material layer pattern after etching is more precise. 2. Since the etching resistance of the mask layer is increased, the material layer can be etched with a thin mask layer, in other words, the hard mask has a higher ratio, so that the side material layer has a higher margin. 3. Since the inner wall of the etching reaction chamber usually has a by-product of the carbon-containing component and these by-products are removed by reacting with the anti-side treated oxygen, the anti-etching treatment in a field manner has the effect of cleaning the etching reaction chamber. . The present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the invention, and those skilled in the art can make some modifications without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1C are cross-sectional views showing a flow of a method for manufacturing a hard mask layer according to an embodiment of the present invention. 2 is a flow chart showing the steps of the method for manufacturing the hard mask layer described above. 3A to 3D are cross-sectional views showing the flow of a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. 3E is a cross-sectional view of the subsequent process of FIG. 3D in accordance with an embodiment of the present invention. Figure 3E' is a cross-sectional view of the subsequent process of Figure 3D in accordance with one embodiment of the present invention. [Main component symbol description] 100: Substrate 102, 302: mask layer 104, 304: patterned photoresist layer 106, 306: opening 108 · First plasma processing process 110, 310: polymer material layer 112 ·· Second plasma processing process 200~208 ··Step 300: material layer 308: anti-etching treatment 312 ··hard mask 14 129 jobs_314: trench 316: shallow trench isolation structure 318: germanium substrate 320: dielectric material 322 : Conductor Material 324: Gate Structure
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