TW200407979A - Method of manufacturing low K layer - Google Patents

Method of manufacturing low K layer Download PDF

Info

Publication number
TW200407979A
TW200407979A TW092100364A TW92100364A TW200407979A TW 200407979 A TW200407979 A TW 200407979A TW 092100364 A TW092100364 A TW 092100364A TW 92100364 A TW92100364 A TW 92100364A TW 200407979 A TW200407979 A TW 200407979A
Authority
TW
Taiwan
Prior art keywords
constant layer
low
patent application
manufacturing
scope
Prior art date
Application number
TW092100364A
Other languages
English (en)
Other versions
TW578216B (en
Inventor
Lih-Ping Li
Hsin-Hsien Lu
Syun-Ming Jang
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Application granted granted Critical
Publication of TW578216B publication Critical patent/TW578216B/zh
Publication of TW200407979A publication Critical patent/TW200407979A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835Combinations of two or more different dielectric layers having a low dielectric constant
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Description

200407979 五、發明說明(l) 發明所屬之技術領域: 本發明係有關於低介電常數(Low Dielectric Constant; Low K)的製造方法’特別是有關於可減低介電常數值的低 介電常數製造方法。 先前技術:
隨著半導體技術的進步,元件的尺寸也不斷地縮小,當積 體電路的積集度(Integration)增加時,晶片的表面無法提 供足夠的面積來製作所需的内連線。因此,為了配合元件 細小後所增加的内連線’目前超大型積體電路(yery Large Scale Integration; VLSI)技術大都係採用多層金屬導體 連線的設計。然而,隨著金屬導線層的數目增加及導線間 的距離不斷縮小,電子訊號在金屬連線間傳送時,金屬連 線的電阻電容延遲時間(Resistance Capacitance DeUy Time; RC Delay Time),已成為半導體元件速度受限的主 要原因之一。此外,金屬連線尺寸的縮小,亦使得電致遷 移(Electromigration)的情況日趨嚴重。
為了降低訊號傳遞的時間延遲,目前的發展方向除了以電 阻率約為1 · 67/ζ Ω - cm之銅金屬來取代電阻率約為2.66/ζ Ω 之链金屬成為導線的連線系統外,更可以利用低介電常 數材料來作為導線間的絕緣層,藉以降低金屬與金屬層之 間的寄生電容大小,使元件在速度方面的性能提高,並且
第4頁 200407979 五、發明說明(2) 可以降低功率的消耗(p 〇 w e r D i s s i p a t i ο η )及雜訊干擾 (Cross-talk Noise)。 然而、,由於低介電常數薄膜通常係為鬆散的孔洞(p〇re)結 構’導致低介電常數薄膜之機械強度較差,因此在製程期 間’低介電常數薄膜很容易因一些外力或能量而破裂,造 成製程良率的降低。為了避免低介電常數薄膜的破裂,傳 統上皆必須藉由變更或修改低介電常數材料之前驅物 (Precursor)來提高其破裂門檻。目前,一般係在低介電常 數薄膜形成後,對此低介電常數薄膜進行後續之處理,來 增加其結構強度。 發明内容: 鑒於上述之發明背景中,為了表現超大型積體電路元件良 好的操作特性,低介電常數材料技術日趨重要,因此,本 發明的目的,係為提供一種低介電常數層之製造方法,係 在用電漿處理低介電常數層的步驟後,加入去除低介電常 數層上之緻密層(Dense Layer)的步驟。 根據以上所述之目的,本發明低介電常數層之製造方法包 括:首先,在基材上形成低介電常數層;接著,對低介電 常數層進行電漿處理步驟;隨後,去除低介電常數層表面 之部分材料。其中,去除步驟可使用化學機械研磨法 (Chemical Mechanical Polishing)、氬氣濺擊法(Ar Sputtering)、氟化氫氣體(HF Vapor)製程、濕式蝕刻法或
第5頁 200407979 五、發明說明(3) ' 乾式蝕刻法等。 由於電漿製程後,低介電常數層表面的緻密層會導致整體 低介電常數層的介電常數值提高,因此在加入去除步驟 後,可降低整體低介電常數的介電常數值。如此一來,改 善金屬連線的電阻電容延遲時間,也提昇積體電路的元件 速度。 實施方式: 本發明揭露一種低介電常數層之製造方法,係使積體電路 中之應用低介電常數材料所構成之絕緣層具有較低的介電 常數值,以降低金屬導線層之間的寄生電容大小。為了使 本發明之敘述更加詳盡與完備,可參照下列描述並配合第1 圖至第3圖與第4圖之圖示。第1圖至第3圖所繪示為本發明 低介電常數層之製程剖面示意圖,而第4圖為本發明低介電 常數層之製造流程圖,請一併參照第1圖至第3圖與第4圖。 首先,如同步驟50,利用例如化學氣相沉積法(Chemi cal Vapor Deposition; CVD)或電漿增益化學氣相沉積法 (Plasma Enhanced CVD; PECVD)在基材 1〇上形成一層低介 電常數層12,此低介電常數層12之材料可例如為氟^非晶 碳(Fluorinated Amorphous Carbon ; a 〜c:F)、有機的 MSQ(Methyl Silsesquioxane)、以及無機的 HSQ(Hydr〇gen Silsesquioxane)等 。 當低介電常數層1 2形成後,如同步驟5 2,利用電衆丨4對此
第6頁 200407979 五、發明說明(4) ' ~ =介電常數層12進行電漿處理,此電漿處理步驟可藉以使 知·低介電常數層内之原子排列進行重整及化學反應,而降 低$電常數與其缺陷。其中,電漿處理之反應氣^可例如 為氨氣與氫氣及其混合物等, 但是,經過電漿14所處理的低介電常數層12卻會在立表面 形成一層敏密層16,此敏密層16的介電常數係高於^部低 介電常數材料。在此情況下,整體低介電常數層12的介電 常數值會因此而增加。 在低介電常數材料之技術日趨重要的情況下,本發明更在 電漿處理步驟之後,揭露一道去除步驟。如同步驟54,係 利用例如化學機械研磨法(Chemical Mechanical hli^hing)、例如利用氬氣(Ar)之濺擊法(Sputtering)、 氣化氳氣體(HF Vapor )製程、以及利用化學品之濕式蝕刻 法或乾式敍刻法等,將緻密層1 6去除,而形成低介電常數 層 1 2a 〇 其中,一般緻密層的厚度係介於約1〇〇 A至15〇〇 A之間,因 此可依形成厚度及不同緻密層之材料,調整去除步驟中例 如研磨漿種類、粒徑、蝕刻化學品 '製程時間、蝕刻方法 等製程條件,本發明並不限於此。
例如,在本發明一較佳實施例中,係對厚度約為5〇〇 A的緻 密層,利用用以去除氧化物、且其成分為含矽材料或其混 合物之研磨漿,進行約1 80秒的化學機械研磨步驟,而可使 得原本厚度為2700 A的低介電常數層,厚度減少至 2200 A,如此可將其表面的緻密層去除。
第7頁 200407979 五、發明說明(5) 另外,由於上述步驟5 2之進行電漿處理並非本發明之重 點,因此其所使用的製程參數,例如反應氣體種類、反應 氣體流量、電漿電力、壓力、溫度與製程時間等,皆可視 需要而加以改變,本發明不限於此。 利用本發明低介電常數層之製造方法,不僅具有利用電漿 處理提高低介電常數層之機械強度的優點,也同時改善因 緻密層而降低介電常數值的缺點。如此,由於提昇低介電 常數材料之技術,使得介電常數值減低,而具有改善金屬 連線的電阻電容延遲時間與提昇積體電路元件速度的效 果。 如熟悉此技術之人員所瞭解的,以上所述僅為本發明之較 佳實施例而已,並非用以限定本發明之申請專利範圍;凡 其它未脫離本發明所揭示之精神下所完成之等效改變或修 飾,均應包含在下述之申請專利範圍内。
200407979 圖式簡單說明 圖式簡單說明: 本發明的較佳實施例將輔以下列圖形做更詳細的闡述,其 中: 第1圖至第3圖所繪示為應用本發明低介電常數層之製造方 法的剖面示意圖;以及 第4圖為本發明低介電常數層之製造流程圖。 圖號對照說明:
10 基 材 12 低 介電常數層 12a 低 介 電 常 數 層 14 電 漿 16 緻 密 層 50 形 成 低 介 電 常 數 層之 步驟 52 進 行 電 漿 處 理 之 步驟 54 去 除 緻 密 層 之 步 驟
第9頁

Claims (1)

  1. 200407979 六、申請專利範圍 1.一種低介電常數層之製造方法,至少包括: 形成一低介電常數層於一基材上; 對該低介電常數層進行一電漿處理;以及 進行一去除步驟,藉以去除部分之該低介電常數層。 2 ·如申請專利範圍第1項所述之低介電常數層之製造方法, 其中形成該低介電常數層之步驟係利用一化學氣相沉積法 (CVD) 〇 馨 3. 如申請專利範圍第1項所述之低介電常數層之製造方法, 其中形成該低介電常數層之步驟係利用一電漿增益化學氣 相沉積法(PECVD)。 4. 如申請專利範圍第1項所述之低介電常數層之製造方法, 其中上述之電漿處理步驟係使用一反應氣體,且該反應氣 體之成分係選自於由氫氣、氦氣及其混合物所組成之一族 群。
    5. 如申請專利範圍第1項所述之低介電常數層之製造方法, 其中上述之去除步驟係利用一化學機械研磨法(CMP)。 6. 如申請專利範圍第1項所述之低介電常數層之製造方法, 其中上述之去除步驟係利用一錢擊法(Sputtering)。
    第10頁 200407979 六、申請專利範圍 7.如申請專利範圍第6項所述之低介電常數層之製造方法, 其中上述之去除步驟係利用一氬氣濺擊法。 8 ·如申請專利範圍第1項所述之低介電常數層之製造方法, 其中上述之去除步驟係利用一氟化氳氣體(HF Vapor)製 程。 9.如申請專利範圍第1項所述之低介電常數層之製造方法, 其中上述之去除步驟係利用一濕式蝕刻法。 1 0 .如申請專利範圍第1項所述之低介電常數層之製造方 法,其中上述之去除步驟係利用一乾式蝕刻法。 11. 一種低介電常數層之製造方法,至少包括: 提供一基材; 形成一低介電常數層於該基材上; 對該低介電常數層進行一電漿處理,藉以使得該低介電常 數層内之複數個原子晶格進行一重排動作;以及 進行一去除步驟,藉以去除位於該低介電常數層上之一緻 密層。 1 2.如申請專利範圍第11項所述之低介電常數層之製造方 法,其中形成該低介電常數層之步驟係利用一化學氣相沉
    第11頁 200407979 六、申請專利範圍 積法。 1 3.如申請專利範圍第11項所述之低介電常數層之製造方 法,其中形成該低介電常數層之步驟係利用一電漿增益化 學氣相沉積法。 14.如申請專利範圍第11項所述之低介電常數層之製造方 法,其中上述之電漿處理步驟係使用一反應氣體,且該反 應氣體之成分係選自於由氮氣、氛氣及其混合物所組成之 一族群。 1 5.如申請專利範圍第11項所述之低介電常數層之製造方 法,其中上述之去除步驟係利用一化學機械研磨法。 1 6.如申請專利範圍第11項所述之低介電常數層之製造方 法,其中上述之去除步驟係利用一氬氣濺擊法。 1 7.如申請專利範圍第11項所述之低介電常數層之製造方 法,其中上述之去除步驟係利用一氟化氫氣體製程。 1 8.如申請專利範圍第11項所述之低介電常數層之製造方 法,其中上述之去除步驟係利用一濕式蝕刻法。 19.如申請專利範圍第11項所述之低介電常數層之製造方
    第12頁 200407979 > 、* 六、申請專利範圍 法,其中上述之去除步驟係利用一乾式蝕刻法。
    第13頁
TW092100364A 2002-11-15 2003-01-08 Method of manufacturing low K layer TW578216B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/295,609 US6770570B2 (en) 2002-11-15 2002-11-15 Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer

Publications (2)

Publication Number Publication Date
TW578216B TW578216B (en) 2004-03-01
TW200407979A true TW200407979A (en) 2004-05-16

Family

ID=32297254

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092100364A TW578216B (en) 2002-11-15 2003-01-08 Method of manufacturing low K layer

Country Status (4)

Country Link
US (1) US6770570B2 (zh)
CN (1) CN1327494C (zh)
SG (1) SG111148A1 (zh)
TW (1) TW578216B (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498364B1 (en) * 2000-01-21 2002-12-24 Agere Systems Inc. Capacitor for integration with copper damascene processes
JP2004014841A (ja) * 2002-06-07 2004-01-15 Fujitsu Ltd 半導体装置及びその製造方法
US20040124420A1 (en) * 2002-12-31 2004-07-01 Lin Simon S.H. Etch stop layer
US6753269B1 (en) * 2003-05-08 2004-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method for low k dielectric deposition
US7151315B2 (en) * 2003-06-11 2006-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of a non-metal barrier copper damascene integration
US7892648B2 (en) * 2005-01-21 2011-02-22 International Business Machines Corporation SiCOH dielectric material with improved toughness and improved Si-C bonding
US7202564B2 (en) * 2005-02-16 2007-04-10 International Business Machines Corporation Advanced low dielectric constant organosilicon plasma chemical vapor deposition films
US7564136B2 (en) * 2006-02-24 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Integration scheme for Cu/low-k interconnects
US7635650B2 (en) * 2006-04-14 2009-12-22 Sony Corporation Prevention of plasma induced damage arising from etching of crack stop trenches in multi-layered low-k semiconductor devices
US8617986B2 (en) * 2009-11-09 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and methods for forming the integrated circuits
CN102437089B (zh) * 2011-07-12 2014-05-28 上海华力微电子有限公司 一种铜后道互连工艺
CN102437090B (zh) * 2011-07-12 2015-01-14 上海华力微电子有限公司 无金属阻挡层的铜后道互连工艺
CN102437091B (zh) * 2011-07-22 2013-12-04 上海华力微电子有限公司 采用金属铜合金作为刻蚀阻挡层的铜后道互连工艺
US9633839B2 (en) * 2015-06-19 2017-04-25 Applied Materials, Inc. Methods for depositing dielectric films via physical vapor deposition processes
US10083904B2 (en) * 2016-01-12 2018-09-25 Globalfoundries Inc. Metholodogy for profile control and capacitance reduction

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5976979A (en) * 1997-06-10 1999-11-02 Industrial Technology Research Institute Sequential oxygen plasma treatment and chemical mechanical polish (CMP) planarizing method for forming planarized low dielectric constant dielectric layer
US6140226A (en) 1998-01-16 2000-10-31 International Business Machines Corporation Dual damascene processing for semiconductor chip interconnects
US6162743A (en) 1998-02-10 2000-12-19 Chu; Cheng-Jye Low dielectric constant film and method thereof
US6147009A (en) 1998-06-29 2000-11-14 International Business Machines Corporation Hydrogenated oxidized silicon carbon material
US6383951B1 (en) * 1998-09-03 2002-05-07 Micron Technology, Inc. Low dielectric constant material for integrated circuit fabrication
US6194128B1 (en) 1998-09-17 2001-02-27 Taiwan Semiconductor Manufacturing Company Method of dual damascene etching
JP3888794B2 (ja) * 1999-01-27 2007-03-07 松下電器産業株式会社 多孔質膜の形成方法、配線構造体及びその形成方法
KR100308213B1 (ko) 1999-02-12 2001-09-26 윤종용 반도체 장치를 위한 저유전 층간 절연막의 제조 방법
US6312793B1 (en) 1999-05-26 2001-11-06 International Business Machines Corporation Multiphase low dielectric constant material
US6281142B1 (en) * 1999-06-04 2001-08-28 Micron Technology, Inc. Dielectric cure for reducing oxygen vacancies
US6251806B1 (en) 1999-08-12 2001-06-26 Industrial Technology Research Institute Method to improve the roughness of metal deposition on low-k material
US6211061B1 (en) 1999-10-29 2001-04-03 Taiwan Semiconductor Manufactuirng Company Dual damascene process for carbon-based low-K materials
US6309957B1 (en) 2000-04-03 2001-10-30 Taiwan Semiconductor Maufacturing Company Method of low-K/copper dual damascene
US6342448B1 (en) 2000-05-31 2002-01-29 Taiwan Semiconductor Manufacturing Company Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process
US6346488B1 (en) * 2000-06-27 2002-02-12 Lsi Logic Corporation Process to provide enhanced resistance to cracking and to further reduce the dielectric constant of a low dielectric constant dielectric film of an integrated circuit structure by implantation with hydrogen ions
EP1172847A3 (en) * 2000-07-10 2004-07-28 Interuniversitair Micro-Elektronica Centrum Vzw A method to produce a porous oxygen-silicon layer
US6319809B1 (en) 2000-07-12 2001-11-20 Taiwan Semiconductor Manfacturing Company Method to reduce via poison in low-k Cu dual damascene by UV-treatment
US6372661B1 (en) 2000-07-14 2002-04-16 Taiwan Semiconductor Manufacturing Company Method to improve the crack resistance of CVD low-k dielectric constant material
TW462085B (en) * 2000-10-26 2001-11-01 United Microelectronics Corp Planarization of organic silicon low dielectric constant material by chemical mechanical polishing
US6294457B1 (en) 2001-02-01 2001-09-25 Taiwan Semiconductor Manufacturing Company Optimized IMD scheme for using organic low-k material as IMD layer
US6486082B1 (en) * 2001-06-18 2002-11-26 Applied Materials, Inc. CVD plasma assisted lower dielectric constant sicoh film
US6583043B2 (en) * 2001-07-27 2003-06-24 Motorola, Inc. Dielectric between metal structures and method therefor

Also Published As

Publication number Publication date
US6770570B2 (en) 2004-08-03
TW578216B (en) 2004-03-01
SG111148A1 (en) 2005-05-30
CN1501453A (zh) 2004-06-02
CN1327494C (zh) 2007-07-18
US20040097099A1 (en) 2004-05-20

Similar Documents

Publication Publication Date Title
US7871923B2 (en) Self-aligned air-gap in interconnect structures
US6521547B1 (en) Method of repairing a low dielectric constant material layer
JP3248492B2 (ja) 半導体装置及びその製造方法
JP4659751B2 (ja) 低k誘電体を半導体製造プロセスにおいて形成する方法
TW200407979A (en) Method of manufacturing low K layer
TWI321346B (en) Method of forming metal line in semiconductor device
CN1278415C (zh) 具有多个布线层的半导体器件及其制造方法
US6919101B2 (en) Method to deposit an impermeable film on porous low-k dielectric film
KR100500932B1 (ko) 비아 콘택 식각 후의 감광막 제거 및 건식 세정 방법
US20050009339A1 (en) Method of forming copper wiring in semiconductor device
US6881661B2 (en) Manufacturing method of semiconductor device
US20070218214A1 (en) Method of improving adhesion property of dielectric layer and interconnect process
US6881590B2 (en) Re-performable spin-on process
JP2006073612A (ja) レジスト除去方法
JP2004103747A (ja) 半導体装置の製造方法
JP2000164569A (ja) 半導体装置の製造方法
CN106847740B (zh) 一种形成空气隙/铜互连的工艺方法
JP4948278B2 (ja) 半導体装置の製造方法
KR20100036449A (ko) 반도체 소자의 제조방법
JP2007088017A (ja) 有機絶縁膜とその作製方法,及び有機絶縁膜を用いた半導体装置
US6524973B2 (en) Method for forming low dielectric constant layer
KR100866135B1 (ko) 반도체 소자의 제조방법
CN106783730B (zh) 一种形成空气隙/铜互连的方法
TWI305945B (en) Method of fabricating dual damascene structure
CN107527862B (zh) 一种半导体器件及其制作方法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent