TW200407979A - Method of manufacturing low K layer - Google Patents

Method of manufacturing low K layer Download PDF

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TW200407979A
TW200407979A TW092100364A TW92100364A TW200407979A TW 200407979 A TW200407979 A TW 200407979A TW 092100364 A TW092100364 A TW 092100364A TW 92100364 A TW92100364 A TW 92100364A TW 200407979 A TW200407979 A TW 200407979A
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constant layer
low
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manufacturing
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TW092100364A
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TW578216B (en
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Lih-Ping Li
Hsin-Hsien Lu
Syun-Ming Jang
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Taiwan Semiconductor Mfg
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Description

200407979 五、發明說明（l) 發明所屬之技術領域： 本發明係有關於低介電常數（Low Dielectric Constant; Low K)的製造方法’特別是有關於可減低介電常數值的低 介電常數製造方法。 先前技術：
隨著半導體技術的進步，元件的尺寸也不斷地縮小，當積 體電路的積集度（Integration)增加時，晶片的表面無法提 供足夠的面積來製作所需的内連線。因此，為了配合元件 細小後所增加的内連線’目前超大型積體電路（yery Large Scale Integration; VLSI)技術大都係採用多層金屬導體 連線的設計。然而，隨著金屬導線層的數目增加及導線間 的距離不斷縮小，電子訊號在金屬連線間傳送時，金屬連 線的電阻電容延遲時間（Resistance Capacitance DeUy Time; RC Delay Time)，已成為半導體元件速度受限的主 要原因之一。此外，金屬連線尺寸的縮小，亦使得電致遷 移（Electromigration)的情況日趨嚴重。
為了降低訊號傳遞的時間延遲，目前的發展方向除了以電 阻率約為1 · 67/ζ Ω - cm之銅金屬來取代電阻率約為2.66/ζ Ω 之链金屬成為導線的連線系統外，更可以利用低介電常 數材料來作為導線間的絕緣層，藉以降低金屬與金屬層之 間的寄生電容大小，使元件在速度方面的性能提高，並且
第4頁 200407979 五、發明說明（2) 可以降低功率的消耗（p 〇 w e r D i s s i p a t i ο η )及雜訊干擾 (Cross-talk Noise)。 然而、，由於低介電常數薄膜通常係為鬆散的孔洞（p〇re)結 構’導致低介電常數薄膜之機械強度較差，因此在製程期 間’低介電常數薄膜很容易因一些外力或能量而破裂，造 成製程良率的降低。為了避免低介電常數薄膜的破裂，傳 統上皆必須藉由變更或修改低介電常數材料之前驅物 (Precursor)來提高其破裂門檻。目前，一般係在低介電常 數薄膜形成後，對此低介電常數薄膜進行後續之處理，來 增加其結構強度。 發明内容： 鑒於上述之發明背景中，為了表現超大型積體電路元件良 好的操作特性，低介電常數材料技術日趨重要，因此，本 發明的目的，係為提供一種低介電常數層之製造方法，係 在用電漿處理低介電常數層的步驟後，加入去除低介電常 數層上之緻密層（Dense Layer)的步驟。 根據以上所述之目的，本發明低介電常數層之製造方法包 括：首先，在基材上形成低介電常數層；接著，對低介電 常數層進行電漿處理步驟；隨後，去除低介電常數層表面 之部分材料。其中，去除步驟可使用化學機械研磨法 (Chemical Mechanical Polishing)、氬氣濺擊法（Ar Sputtering)、氟化氫氣體（HF Vapor)製程、濕式蝕刻法或
第5頁 200407979 五、發明說明（3) ' 乾式蝕刻法等。 由於電漿製程後，低介電常數層表面的緻密層會導致整體 低介電常數層的介電常數值提高，因此在加入去除步驟 後，可降低整體低介電常數的介電常數值。如此一來，改 善金屬連線的電阻電容延遲時間，也提昇積體電路的元件 速度。 實施方式： 本發明揭露一種低介電常數層之製造方法，係使積體電路 中之應用低介電常數材料所構成之絕緣層具有較低的介電 常數值，以降低金屬導線層之間的寄生電容大小。為了使 本發明之敘述更加詳盡與完備，可參照下列描述並配合第1 圖至第3圖與第4圖之圖示。第1圖至第3圖所繪示為本發明 低介電常數層之製程剖面示意圖，而第4圖為本發明低介電 常數層之製造流程圖，請一併參照第1圖至第3圖與第4圖。 首先，如同步驟50，利用例如化學氣相沉積法（Chemi cal Vapor Deposition; CVD)或電漿增益化學氣相沉積法 (Plasma Enhanced CVD; PECVD)在基材 1〇上形成一層低介 電常數層12，此低介電常數層12之材料可例如為氟^非晶 碳（Fluorinated Amorphous Carbon ； a 〜c:F)、有機的 MSQ(Methyl Silsesquioxane)、以及無機的 HSQ(Hydr〇gen Silsesquioxane)等 。 當低介電常數層1 2形成後，如同步驟5 2，利用電衆丨4對此
第6頁 200407979 五、發明說明（4) ' ~ =介電常數層12進行電漿處理，此電漿處理步驟可藉以使 知·低介電常數層内之原子排列進行重整及化學反應，而降 低$電常數與其缺陷。其中，電漿處理之反應氣^可例如 為氨氣與氫氣及其混合物等， 但是，經過電漿14所處理的低介電常數層12卻會在立表面 形成一層敏密層16,此敏密層16的介電常數係高於^部低 介電常數材料。在此情況下，整體低介電常數層12的介電 常數值會因此而增加。 在低介電常數材料之技術日趨重要的情況下，本發明更在 電漿處理步驟之後，揭露一道去除步驟。如同步驟54，係 利用例如化學機械研磨法（Chemical Mechanical hli^hing)、例如利用氬氣（Ar)之濺擊法（Sputtering)、 氣化氳氣體（HF Vapor )製程、以及利用化學品之濕式蝕刻 法或乾式敍刻法等，將緻密層1 6去除，而形成低介電常數 層 1 2a 〇 其中，一般緻密層的厚度係介於約1〇〇 A至15〇〇 A之間，因 此可依形成厚度及不同緻密層之材料，調整去除步驟中例 如研磨漿種類、粒徑、蝕刻化學品 '製程時間、蝕刻方法 等製程條件，本發明並不限於此。
例如，在本發明一較佳實施例中，係對厚度約為5〇〇 A的緻 密層，利用用以去除氧化物、且其成分為含矽材料或其混 合物之研磨漿，進行約1 80秒的化學機械研磨步驟，而可使 得原本厚度為2700 A的低介電常數層，厚度減少至 2200 A，如此可將其表面的緻密層去除。
第7頁 200407979 五、發明說明（5) 另外，由於上述步驟5 2之進行電漿處理並非本發明之重 點，因此其所使用的製程參數，例如反應氣體種類、反應 氣體流量、電漿電力、壓力、溫度與製程時間等，皆可視 需要而加以改變，本發明不限於此。 利用本發明低介電常數層之製造方法，不僅具有利用電漿 處理提高低介電常數層之機械強度的優點，也同時改善因 緻密層而降低介電常數值的缺點。如此，由於提昇低介電 常數材料之技術，使得介電常數值減低，而具有改善金屬 連線的電阻電容延遲時間與提昇積體電路元件速度的效 果。 如熟悉此技術之人員所瞭解的，以上所述僅為本發明之較 佳實施例而已，並非用以限定本發明之申請專利範圍；凡 其它未脫離本發明所揭示之精神下所完成之等效改變或修 飾，均應包含在下述之申請專利範圍内。
200407979 圖式簡單說明 圖式簡單說明： 本發明的較佳實施例將輔以下列圖形做更詳細的闡述，其 中： 第1圖至第3圖所繪示為應用本發明低介電常數層之製造方 法的剖面示意圖；以及 第4圖為本發明低介電常數層之製造流程圖。 圖號對照說明：
10 基 材 12 低 介電常數層 12a 低 介 電 常 數 層 14 電 漿 16 緻 密 層 50 形 成 低 介 電 常 數 層之 步驟 52 進 行 電 漿 處 理 之 步驟 54 去 除 緻 密 層 之 步 驟
第9頁

Claims (1)

  1. 200407979 六、申請專利範圍 1.一種低介電常數層之製造方法，至少包括： 形成一低介電常數層於一基材上； 對該低介電常數層進行一電漿處理；以及 進行一去除步驟，藉以去除部分之該低介電常數層。 2 ·如申請專利範圍第1項所述之低介電常數層之製造方法， 其中形成該低介電常數層之步驟係利用一化學氣相沉積法 (CVD) 〇 馨 3. 如申請專利範圍第1項所述之低介電常數層之製造方法， 其中形成該低介電常數層之步驟係利用一電漿增益化學氣 相沉積法（PECVD)。 4. 如申請專利範圍第1項所述之低介電常數層之製造方法， 其中上述之電漿處理步驟係使用一反應氣體，且該反應氣 體之成分係選自於由氫氣、氦氣及其混合物所組成之一族 群。
    5. 如申請專利範圍第1項所述之低介電常數層之製造方法， 其中上述之去除步驟係利用一化學機械研磨法（CMP)。 6. 如申請專利範圍第1項所述之低介電常數層之製造方法， 其中上述之去除步驟係利用一錢擊法（Sputtering)。
    第10頁 200407979 六、申請專利範圍 7.如申請專利範圍第6項所述之低介電常數層之製造方法， 其中上述之去除步驟係利用一氬氣濺擊法。 8 ·如申請專利範圍第1項所述之低介電常數層之製造方法， 其中上述之去除步驟係利用一氟化氳氣體（HF Vapor)製 程。 9.如申請專利範圍第1項所述之低介電常數層之製造方法， 其中上述之去除步驟係利用一濕式蝕刻法。 1 0 .如申請專利範圍第1項所述之低介電常數層之製造方 法，其中上述之去除步驟係利用一乾式蝕刻法。 11. 一種低介電常數層之製造方法，至少包括： 提供一基材； 形成一低介電常數層於該基材上； 對該低介電常數層進行一電漿處理，藉以使得該低介電常 數層内之複數個原子晶格進行一重排動作；以及 進行一去除步驟，藉以去除位於該低介電常數層上之一緻 密層。 1 2.如申請專利範圍第11項所述之低介電常數層之製造方 法，其中形成該低介電常數層之步驟係利用一化學氣相沉
    第11頁 200407979 六、申請專利範圍 積法。 1 3.如申請專利範圍第11項所述之低介電常數層之製造方 法，其中形成該低介電常數層之步驟係利用一電漿增益化 學氣相沉積法。 14.如申請專利範圍第11項所述之低介電常數層之製造方 法，其中上述之電漿處理步驟係使用一反應氣體，且該反 應氣體之成分係選自於由氮氣、氛氣及其混合物所組成之 一族群。 1 5.如申請專利範圍第11項所述之低介電常數層之製造方 法，其中上述之去除步驟係利用一化學機械研磨法。 1 6.如申請專利範圍第11項所述之低介電常數層之製造方 法，其中上述之去除步驟係利用一氬氣濺擊法。 1 7.如申請專利範圍第11項所述之低介電常數層之製造方 法，其中上述之去除步驟係利用一氟化氫氣體製程。 1 8.如申請專利範圍第11項所述之低介電常數層之製造方 法，其中上述之去除步驟係利用一濕式蝕刻法。 19.如申請專利範圍第11項所述之低介電常數層之製造方
    第12頁 200407979 > 、* 六、申請專利範圍 法，其中上述之去除步驟係利用一乾式蝕刻法。
    第13頁
TW092100364A 2002-11-15 2003-01-08 Method of manufacturing low K layer TW578216B (en)

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US20040097099A1 (en) 2004-05-20

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