TW200403728A - Method to perform deep implants without scattering to adjacent areas - Google Patents

Abstract

A method of fabricating an integrated circuit in and on a semiconductor substrate with deep implantations by applying a scattered ion capturing layer in the resist mask opening to capture any implanted ions scattered in the resist and deflected ort of the resist into the mask opening to prevent these ions from reaching the semiconductor substrate and affecting the concentration of ions at the edge of the mask and thus the performance of the integrated circuit.

Description

200403728 V. Description of the invention (1) Scope of the invention The present invention relates to semiconductor integrated circuits, and more specifically to the manufacture of integrated circuits that require deep implantation of impurities. Background of the invention

As the level of accumulation of crystal grains in a semiconductor wafer or a wafer (for example, a silicon substrate) increases, the requirements for the manufacturing method of the semiconductor wafer also increase, such as making deep implantation of impurities in the semiconductor substrate. Today, higher doses of deep implants are required to stop leakage effects and to achieve higher performance and density. However, as the layout of integrated circuits locates transistors, transistor parts, and other components of the circuit closer and closer, it becomes increasingly necessary to perform a deep implantation in one area of the circuit layout in the manufacturing method. The more difficult it is, it is easy to invade a neighboring area and affect the necessary parameters of the area. As the layout of integrated circuits will continue to shrink, this issue will become increasingly critical in future generations of integrated circuits.

During the deep implantation process, the impurities to be implanted (indicated by arrows in Figures 2 and 3 where the conventional techniques are drawn) are scattered within the implantation mask (such as a photoresist). This mask is used to protect other areas of the integrated circuit that we do not want to be implanted with impurities during this implantation step. However, as shown in Fig. 3, some implant impurities will scatter away from the implant mask at the edge of the implant mask and enter the unshielded area of the wafer. The scattering of these unwanted impurities into the adjacent unshielded wafer area will affect the performance of the integrated circuit and reduce the production yield of the integrated circuit wafer in a wafer. Therefore, with integrated circuits (especially integrated products that require deep implantation of impurities)

Page 5 200403728 V. Description of the Invention (2) The density of the circuit is increased. How to have a process to overcome the problem of scattering these impurities into the substrate area near the masked implantation area is of great importance. Therefore, an object of the present invention is to design a process for manufacturing an integrated circuit wafer that requires deep implantation of impurities, which prevents the impurities from being scattered into the area of the substrate near the shielding implanted area. In addition, an object of the present invention is to provide a simple improvement to the conventional deep implantation method, which does not affect the productivity of the conventional deep implantation method and does not complicate the overall process of the integrated circuit chip. Furthermore, an object of the present invention is to propose a simple improvement so that the conventional processing steps performed after the deep implantation step are not substantially affected by the improvement. The invention fans can stop this in order to achieve internal prevention of thinning (ARC: reflected by people. The function is to remove other materials. The point is to remove the light collection period and back in the anti-coating technology and use it. Its preference is for its above and other purposes. In the method for scattering impurities from a masked layer to a substrate near the masked area in a deep implant in accordance with the present invention, in the region adjacent to the masked implanted area The scattered impurity capture layer easily removed by the memory to capture the scattered impurity impurities to reach the wafer substrate. Preferably, this layer is an anti-reflection ', which is generally positioned under a photoresist and is used in this technique to prevent The order of light that exposes the photoresist is from the wafer surface. However, in the present invention, the anti-reflection coating is not used for this purpose to capture scattered impurities instead of preventing reflection of UV light. Although it can make (for example, the hardness of a silicate glass Mask), an anti-reflective coating that can exist during the exposure of the photoresist, and it can be retained after the selection of the resist and used for the new function of the present invention. It is also quite equivalent in the function of implanted impurities Easy to go .

Page 6 200303728 V. Description of the invention (3) Because the scattered implanted impurities contain (1/3) to one hundredth (1/100) of angular scattering, the thickness score of the capture layer is clearly more than that of any part. Removal from implantation with the substrate. It is clearly displayed in the ratio green (1/3, but below the depth suitable for deep implantation of 'bipolar separation'. Details are mandatory below. Phase 0) to one-fifth of the implantation using CMOS Transistor operation, such as the implantation of the collector and base barrier of the high-doping device, the detailed description of the gate doping is based on the conventional adjustment of the ground. One-third of the energy of the original impurity of each feature is Orthogonal to the wafer is a thickness in the range of three (1/50) of the depth of the deep implanted impurities. N-type wells and p-type wells that scatter impurity ion collection layers can also be implanted with heterogeneous source / drain and pocket / extended and emitter electrodes to implant one well and The wells connected in one diagram can obtain the best structure of the present invention. Each feature in the diagram is not arbitrarily enlarged or reduced according to the size for detailed description of the invention. The invention is described in detail below with reference to the drawings. Figure 丨 is a partial cross-sectional view of a half-conductor wafer 10 (here, silicon), which is a trench Ua, llb, and llc to isolate regions 2 to be formed in the wafer during the process. Shallow trench isolation (STI) is formed by etching openings in the wafer with reactive ions and filling the etch 1 ^ with an insulating material 12 (such as silicon oxide) (the unfilled state is not shown in the figure). In order to manufacture a p s sa body, a P-type well and an N-type well must be formed within the wafer 10 by implanting appropriate impurities, such as a p-type well with boron and an N-type well with phosphorus.

200403728 V. Description of the invention (4) As shown in Fig. 2, the method for forming a P-shaped well 13 by conventional techniques is to deposit a photoresist 14 (such as diazonaphthoquinone (di azonaphthoquinone) type) and exposing and developing it so that the photoresist shields all but 13 places (in this example, between trenches 丨 丨 a and ib) where P-wells are to be formed. The boron ions are implanted into the area of the wafer 10 which is not blocked by the photoresist as indicated by arrow 5 in FIG. 2. In the photoresist shielding area (covering the area between the trenches lib and 11c and the trenches ilallb and llc), the boron ions indicated by the two arrows 15 are blocked by the photoresist 14, but some are as shown by the arrow 1 in Figure 3 Some of the scattered ions indicated by a are deflected into the unshielded area shown by hole 16 in Fig. 3. Referring now to FIGS. 4 and 5 and a description of the present invention, a silicon wafer 20 having a shallow trench isolation (sn) trench 21a, 21b, and 21c filled with an insulating material (such as silicon oxide 22) is coated. A thin and easy-to-remove diffused impurity collection layer 23 is provided. Layer 23 is preferably an anti-reflective coating (ARC), such as a spin-on glass or polymer, which is well known in the art. Generally, the thickness of layer 23 will be greater than 30 but less than 1000 nm. The thickness of the layer 23 is determined by the material of the layer, the specific impurities to be implanted, and the depth of the impurities ^ Overall, the thickness of the layer 23 is about one-third (1/3) to about the desired implant depth One-fifth (1 / 5〇). Under the condition that the thickness of the layer 23 is more than about 30 nm but less than 1,000 mm, deep implantation is performed with Zn, ITO, or indium with an energy in the range of more than 8 keV < The dose of boron for ice implantation is in the range of 丨 e 丨 3 to 丨 ^ 丨 6⑽2 ^, L. The anti-reflection coating is deposited to a thickness of less than 30 nm. Up to 5 keV. The energy of scattering impurity ions is

Page 8 200403728 V. Description of the invention (5) The original energy of implanted impurities is in the range of about one-third (丨 / 3) to about one-tenth (1 / 1G). Although Figures 4 and 5 depict the implantation of a -P well, the present invention can be used for deep implantation of an N-well using either phosphorus or arsenic or both. Once again, under the condition that the thickness of the anti-reflective coating is greater than 30 ⑽ but less than 10,000 ⑽, deep implantation is performed with filling at an energy of more than 12 keV and usually in the range of ¥ 40 to 12,000 keV. . The dose of deep implanted phosphorus is in the range of 5ei2 to 1616⑽2. Again—'If the anti-reflection coating is deposited to a thickness of less than 30 ⑽, then the phosphorus energy for deep implantation is as low as 2 2 * Although it is true, the detailed description of the present invention is focused on the formation—CM The transistor can be used in the formation of a lightly doped drain (LDD) and a replayed hybrid anode (HDD). In these applications, boron and phosphorus agents are larger than 5el4 cm2. A photoresist 24 (for example, illustrating the type used in the conventional technique of deep planting of Figs. 2 and 3) is forced on top of the layer 23. It again covers the area between the channels ^ 9 g and _2 1 ^ and the channels 2 1 a, 2 1 b and 2 1 c. The boron ions are implanted into the area of the wafer 20 not covered by the photoresist as shown by arrow 5 to form a p = well 26. In the photoresist shielding area, boron ions are blocked by the photoresist 24, but some of the scattered ions shown by the arrow 25a, some of them are biased to the unshielded area μ shown by the hole 27 of?. However, it is different from the method 1 in Figures 2 and 3 'The scattered ions indicated by the arrow 25a or hole 27 in Figure 5 are captured f thunder 2 3 = and prevent it from reaching the wafer substrate 2G, so that it remains in the crystal The performance of the CM0S transistor made of a 20-inch circuit is described in the chip. North of the formation of the p-type well, the photoresist 24 is removed and applied again to mask P 6 during the formation of the N-type well. It is best to leave layers 2 3 in the crystals before completing all deep implant operations

Page 9 200403728 V. Description of Invention (6) Circle 20. It has been shown in Figs. 4 and 5 that the layer 23 is under the photoresist 24, but it does not necessarily appear under the photoresist. The layers 2 3 only have to cover the area between the trenches 21a and 21b. However, limiting layer 23 to only this region would result in additional steps. To simplify the invention, the method is to deposit layers 23 on the entire wafer. In addition, the antireflective coating has been mentioned above as the preferred material for layer 23, so that a hard mask containing silicate glass (eg, borosilicate glass / tetraethoxysilicate (BSG / TE0S)) can be used. Replaces anti-reflective coating. Unlike the anti-reflection coating, which is spin-on, borosilicate glass / tetraethoxy silicate is deposited by chemical vapor deposition (CVD). Although not required, there are: an emulsified silicon layer (not shown in the figure) # under the impurity ion trap layer 23 (such as an anti-reflection coating and a hard mask layer). Figures 6 and 7 show the absence (Figure 6) and the presence (Figure 7) of the present "ion trap layer 23 (Figure 4-Figure 5) = planting: mode for scattering away from the state: Learn the dagger picture ... The bar on the left-hand side of this picture is without layer 23 (picture 4_5 second friend: the scale of Guangchen degree. Picture 6 ^ 0 ^ 5) Under the conditions, the figure φ LV tells that the 上方 above the n-ditch barrier (ST I) is w. The boron ion branch marked by the circle near the edge of the sealant to increase the concentration of F. Chen Du & Because of the scattered impurity boron ions, J. This boron ions increase the concentration region from the edge of the resist: see. From the figure, it can be seen that a 180 nm hard mask layer of the present invention, and Am With the existence of the boron ion increasing concentration region, it cannot be seen in the Shi Xi wafer. 200403728 V. Description of the invention (7) The advantage of high ion concentration is that a narrow field-effect transistor (FET) is not located in The resist edges will have almost constant thresholds. These field effect transistors are designs used today and in the future to increase the density of integrated circuits. The benefit is that the fabricated Improved yield of integrated circuit wafers. Although the invention has been described in terms of specific embodiments, those skilled in the art will recognize that many changes and modifications can be made without departing from the spirit and scope of the invention as defined by the scope of the appended patents. End of chapter

Page 11 200403728 Brief Description of Drawings Figure 1 is a partial cross-sectional view of a conventional semiconductor wafer containing a shallow trench isolation area to be activated in the integrated circuit manufacturing process. FIG. 2 is a cross-sectional view of the conventional semiconductor wafer of FIG. 1, in which a part of the wafer is masked by a photoresist during deep implantation of impurities to form a P-well. FIG. 3 is an enlarged cross-sectional view of a part of the conventional semiconductor wafer of FIG. 2. The figure shows scattered impurity ions that are not in the vicinity of the portion of the wafer substrate that is blocked by the wafer.

FIG. 4 is a cross-sectional view of the conventional semiconductor wafer of FIG. 1. The wafer as a whole has a thin and easy-to-remove impurity trap layer according to the present invention, and a part of the wafer is subjected to a photoresist during the deep implantation of impurities. The agent was masked to form a P-shaped well. Fig. 5 is an enlarged cross-sectional view of a part of the semiconductor wafer of Fig. 4, which shows scattered impurity ions in the layer of the present invention in the vicinity of the shielded portion of the wafer. Fig. 6 is a Monte Carlo simulation result diagram of a boron ion implanted without a scattering ion trap layer. Figure 7 is a Monte Carlo simulation result of a boron ion implanted with a scattering ion trap layer. Component symbol description:

1 0, 2 0 Wafer 1 1 a, 1 1 b, 11 c, 2 1 a, 2 1 b, 2 1 c Shallow insulation trenches 12 Insulating materials 14, 24 Photoresist 16, 16 Holes 23 Layers 13 , 26 P-type well 1 5, 1 5 a arrow 22 Silicon oxide 2 5, 2 5 a arrow

Page 12

Claims (1)

200403728 Six applications for patent scope 1 · A method for manufacturing a one-on-one integrated circuit in a semiconductor substrate, which includes the following steps: A semiconductor substrate is provided, which has an upper surface to allow ions to pass through; Impurities apply a thin scattering impurity ion trapping layer on the surface of the semiconductor substrate; easy to remove ^ A masking material is applied near the ion trapping layer to provide an opening for implanted ions to pass through the opening in the substrate Mask; implanted with sufficient energy and dose of impurity ions to implant the semiconductor substrate; and carved on ice The ion trapping layer captures those ions that are injected into the resist material but that are ... scattered and deflected into the opening at the edge of the mask opening 2. The method according to item 丨 of the patent application range, wherein the separation is one. An anti-reflective coating. The μ-layer is the method of item 1 in the scope of patent application, wherein the ion traps a hard mask layer. The method of item 1 in the scope of patent application, wherein the ion trapping layer is used in the formation operation of a deep implanted P-type well or N-type well. 5. The method according to item 1 of the patent application range, wherein the thickness of the ion-trapping layer is determined by the energy of the ions to be implanted. 6. The method of claim 5 in the scope of patent application, wherein the thickness of the scattering ion trapping layer is greater than 30 nm and less than 1000 nm. 7. The method according to item 5 of the patent application, wherein the ion trapping layer is smaller than 230 nm and the energy of the boron ion is less than 5 keV. Page 13 200303728 VI. Patent application scope 8 · If the patent application is adjacent to the mask opening 9. If the patent application is applied to the ion trap layer 10. If the patent application is applied to the integrated circuit system 11 · A manufacturing It is required to obtain a integrated circuit method, which includes the following: providing half of the conductive ions to pass through; the semiconductor sub-capture layer; implanting ions at the ion trap; passing implanted ions into the implanted semiconductor substrate with sufficient energy; The mask is opened in the implantation operation structure so that the capture layer is completed. 1 2 · The method t according to item 1 of the patent application range, wherein only the inner 3 of the ion trapping layer is the surface of the semiconductor substrate. Ancient around item 1 Removed. Method, wherein the t j Φ Mg method of item 1 is completed after the implantation operation, wherein the ion trapping layer is used to implant one or two pounds into the deep implantation operation period. ί 久 ί Multiple deep ion implantation steps are performed in the body substrate. The body substrate with a shallow trench isolation integrated circuit is constructed with a top surface to which a thin scattering impurity is applied on the surface of the impurity substrate to be implanted. A masking material is applied near tf to provide a mask with an opening in the substrate; the impurity ions of the amount and agent f are implanted deep into the capture layer with a rafter to capture the shot into the resist material but inside the material. The edge is deflected to the ions in the opening; the masking material is removed, and another masking material with an opening for another use is applied; and the ion is removed after all deep implantation operations of the structure Item method, which covers the ion trapping layer 6. Scope of patent application Thickness is determined by the energy of the ion to be implanted. Wherein (1/3) of the ion trapping layer to about fifty 13. The method according to item 12 of the scope of the patent application, wherein the thickness is about one third (1/50) of the desired implantation depth, where the scattering impurities are about one third of the energy, among which The scattered ion trap 'where the scattered ion trap 14. The method as described in the application item No. 丨 丨 This summer is the original (1/3) to about one percent (1/100) of the implanted impurity ions . 15. The method according to item 11 of the patent application. The layer is an anti-reflective coating. 16. The method according to item 11 of the patent application layer is a hard mask layer. 17. The method according to item 16 of the patent application, wherein the thickness of the hard mask is 180 nm and the implanted ion is boron. 18. The method of claim 11 in which the integrated circuit to be manufactured contains a narrow transistor adjacent to a trench isolation. 19. The method of claim 18, wherein in the process of the narrow transistor, the ion-trapping layer captures scattered ions that affect the performance of the narrow transistor. 20. The method of claim 11 in which the thickness of the scattering ion trapping layer is in a range of 30 nm to 100 nm. Page 15