JPH0797566B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH0797566B2
JPH0797566B2 JP62069612A JP6961287A JPH0797566B2 JP H0797566 B2 JPH0797566 B2 JP H0797566B2 JP 62069612 A JP62069612 A JP 62069612A JP 6961287 A JP6961287 A JP 6961287A JP H0797566 B2 JPH0797566 B2 JP H0797566B2
Authority
JP
Japan
Prior art keywords
thin film
mask material
ion implantation
conductive thin
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62069612A
Other languages
Japanese (ja)
Other versions
JPS63234520A (en
Inventor
典昭 児玉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62069612A priority Critical patent/JPH0797566B2/en
Publication of JPS63234520A publication Critical patent/JPS63234520A/en
Publication of JPH0797566B2 publication Critical patent/JPH0797566B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に関し、特にイオン注
入法を用いて、半導体表面に、不純物領域を形成する方
法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an impurity region on a semiconductor surface by using an ion implantation method.

〔従来の技術〕[Conventional technology]

従来の半導体装置の製造方法では、イオン注入法を用い
て、半導体基板に不純物領域を形成する際、例えば、第
3図(a),(b)に示すように、半導体基板1に形成
されたフィールド酸化膜2、又はゲート酸化膜3の上に
イオン注入マスク材5を形成し、ゲート酸化膜3を介し
て半導体基板1に至るように不純物イオン6を注入し、
不純物領域7を形成していた。
In the conventional method of manufacturing a semiconductor device, when the impurity region is formed in the semiconductor substrate by using the ion implantation method, it is formed in the semiconductor substrate 1 as shown in FIGS. 3 (a) and 3 (b), for example. An ion implantation mask material 5 is formed on the field oxide film 2 or the gate oxide film 3, and impurity ions 6 are implanted so as to reach the semiconductor substrate 1 through the gate oxide film 3.
The impurity region 7 was formed.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述したような従来の半導体装置の製造方法における、
イオン注入法による半導体基板1への不純物領域7の形
成方法では、イオン注入マスク材5がゲート酸化膜3
等、半導体基板1上の薄い絶縁膜上に直接に接する場合
がある。この場合、イオン注入マスク材5が孤立したパ
ターンであると、不純物イオン注入時にイオン注入マス
ク材5に電荷が蓄積され、下層の薄い絶縁膜を破壊する
ことがあるという欠点がある。
In the conventional semiconductor device manufacturing method as described above,
In the method of forming the impurity region 7 in the semiconductor substrate 1 by the ion implantation method, the ion implantation mask material 5 is the gate oxide film 3.
For example, there is a case where it directly contacts the thin insulating film on the semiconductor substrate 1. In this case, if the ion implantation mask material 5 has an isolated pattern, there is a drawback that charges may be accumulated in the ion implantation mask material 5 during the impurity ion implantation, and the underlying thin insulating film may be destroyed.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、半導体基板上に形成
された薄いゲート絶縁膜上に導電性薄膜を形成する工程
と、不純物のイオン注入に対してその下層への前記不純
物の浸入を阻止するマスク材を前記導電性薄膜上に選択
的に形成する工程と、前記マスク材で覆われていない領
域に前記導電性薄膜と前記薄いゲート絶縁膜とを介して
不純物をイオン注入してソース領域およびドレイン領域
を形成する工程と、前記マスク材をマスクとして前記マ
スク材で覆われていない領域の前記導電性薄膜を選択的
にエッチング除去し、ゲート電極を形成する工程とを含
むことを特徴とする。
A method of manufacturing a semiconductor device according to the present invention includes a step of forming a conductive thin film on a thin gate insulating film formed on a semiconductor substrate, and preventing impurities from infiltrating into a lower layer thereof against ion implantation of impurities. A step of selectively forming a mask material on the conductive thin film, and ion-implanting impurities into a region not covered with the mask material through the conductive thin film and the thin gate insulating film to form a source region and A step of forming a drain region, and a step of selectively etching away the conductive thin film in a region not covered with the mask material by using the mask material as a mask to form a gate electrode. .

〔実 施 例〕〔Example〕

次に、本発明について、図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図(a)(b)は、本発明の第1の実施例の縦断面
図である。半導体基板1上にフィールド酸化膜2で囲む
ように素子領域を形成し、素子領域の半導体基板1、表
面には、ゲート酸化膜3を形成する。
1 (a) and 1 (b) are longitudinal sectional views of the first embodiment of the present invention. An element region is formed on the semiconductor substrate 1 so as to be surrounded by the field oxide film 2, and a gate oxide film 3 is formed on the surface of the semiconductor substrate 1 in the element region.

フィールド酸化膜2及びゲート酸化膜3の全面を覆うよ
うに、ポリシリコン、金属シリサイド、高融点金属等の
導電性薄膜4を形成し、この上には、イオン注入マスク
材5を所定の形状で形成する。不純物イオン6が半導体
基板1表面の全面に照射され、イオン注入マスク材5で
覆われてないゲート酸化膜3下の領域の半導体基板1、
表面に不純物イオン6が導電性薄膜4とゲート酸化膜3
を通して注入され、不純物領域7を形成する。
A conductive thin film 4 of polysilicon, metal silicide, refractory metal or the like is formed so as to cover the entire surfaces of the field oxide film 2 and the gate oxide film 3, and an ion implantation mask material 5 is formed on the conductive thin film 4 in a predetermined shape. Form. The entire surface of the semiconductor substrate 1 is irradiated with the impurity ions 6, and the semiconductor substrate 1 in the region below the gate oxide film 3 which is not covered with the ion implantation mask material 5.
Impurity ions 6 are formed on the surface of the conductive thin film 4 and the gate oxide film 3.
Are implanted through to form the impurity region 7.

第2図は本発明の第2の実施例の縦断面図である。FIG. 2 is a vertical sectional view of the second embodiment of the present invention.

半導体薄膜の島10をその端部が半導体基板1の表面に形
成されたシリサイド層9に接するように、フィールド酸
化膜2の上に形成し、半導体薄膜の島10及び半導体基板
1表面を覆うように、ゲート酸化膜3を形成する。
An island 10 of the semiconductor thin film is formed on the field oxide film 2 so that its end portion contacts the silicide layer 9 formed on the surface of the semiconductor substrate 1, and covers the island 10 of the semiconductor thin film and the surface of the semiconductor substrate 1. Then, the gate oxide film 3 is formed.

フィールド酸化膜2及びゲート酸化膜3の全面を覆うよ
うに、ポリシリコン、金属シリサイド、高融点金属等の
導電性薄膜4を形成し、導電性薄膜4の上には、イオン
注入マスク材5、を形成する。イオン注入マスク材5で
覆われていない半導体薄膜の島10の領域に、P型不純物
イオン11を導電性薄膜4及びゲート酸化膜3を通して注
入し、P型不純物領域12を形成する。
A conductive thin film 4 of polysilicon, metal silicide, refractory metal or the like is formed so as to cover the entire surfaces of the field oxide film 2 and the gate oxide film 3, and an ion implantation mask material 5 is formed on the conductive thin film 4. To form. P-type impurity ions 11 are implanted into the region of the island 10 of the semiconductor thin film which is not covered with the ion implantation mask material 5 through the conductive thin film 4 and the gate oxide film 3 to form the P-type impurity region 12.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、イオン注入法により、半
導体基板に不純物領域を形成する際、イオン注入マスク
材のすぐ下層に半導体基板を覆うように導電性薄膜を設
け、この導電性薄膜を基板と短絡、あるいは接地するこ
とにより、不純物イオン注入時、イオン注入マスク材に
電荷が蓄積することを防ぎ、半導体基板と、イオン注入
マスク材の間にある薄い絶縁膜が破壊されるのを防ぐこ
とができる効果がある。
As described above, according to the present invention, when the impurity region is formed in the semiconductor substrate by the ion implantation method, the conductive thin film is provided immediately below the ion implantation mask material so as to cover the semiconductor substrate, and the conductive thin film is used as the substrate. Short circuit or grounding to prevent the accumulation of charges in the ion implantation mask material during impurity ion implantation and to prevent the thin insulating film between the semiconductor substrate and the ion implantation mask material from being destroyed. There is an effect that can be.

また、導電性薄膜をイオン注入マスク材の下に設け、こ
のイオン注入マスク材の側面には、導電性薄膜は形成さ
れないので半導体基本表面に形成される拡散領域のイオ
ン注入マスク材に対するパターンの忠実性は守られる。
Further, a conductive thin film is provided under the ion implantation mask material, and since the conductive thin film is not formed on the side surface of this ion implantation mask material, the pattern of the diffusion region formed on the basic surface of the semiconductor is faithful to the pattern of the ion implantation mask material. Sex is protected.

さらに、ソース・ドレイン領域の形成に、本発明の方法
を適用する場合には、ソース・ドレインのイオン注入後
に、イオン注入マスク材をマスクにして、導電性薄膜を
エッチングし、のこされたマスク下層の導電性薄膜をそ
のままゲート電極とすることができるので、工程数をそ
れほど増やすことなく本発明を適用できる。
Furthermore, when the method of the present invention is applied to the formation of the source / drain regions, after the source / drain ions are implanted, the conductive thin film is etched using the ion implantation mask material as a mask to remove the mask Since the lower conductive thin film can be directly used as the gate electrode, the present invention can be applied without increasing the number of steps.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)(b)は、本発明の第1の実施例の縦断面
図、第2図は本発明の第2の実施例の縦断面図、第3図
(a)(b)は、従来例の縦断面図である。 1……半導体基板、2……フィールド酸化膜、3……ゲ
ート酸化膜、4……導電性薄膜、5……イオン注入マス
ク材、6……不純物イオン、7……不純物領域、8……
n型不純物領域、9……シリサイド層、10……半導体薄
膜の島、11……P型不純物領域、12……P型不純物イオ
ン。
1 (a) and (b) are longitudinal sectional views of a first embodiment of the present invention, FIG. 2 is a longitudinal sectional view of a second embodiment of the present invention, and FIGS. 3 (a) and (b). [FIG. 6] is a vertical sectional view of a conventional example. 1 ... Semiconductor substrate, 2 ... Field oxide film, 3 ... Gate oxide film, 4 ... Conductive thin film, 5 ... Ion implantation mask material, 6 ... Impurity ion, 7 ... Impurity region, 8 ...
n-type impurity region, 9 ... silicide layer, 10 ... island of semiconductor thin film, 11 ... P-type impurity region, 12 ... P-type impurity ion.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/78 301 F ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 29/78 301 F

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に形成された薄いゲート絶縁
膜上に導電性薄膜を形成する工程と、不純物のイオン注
入に対してその下層への前記不純物の浸入を阻止するマ
スク材を前記導電性薄膜上に選択的に形成する工程と、
前記マスク材で覆われていない領域に前記導電性薄膜と
前記薄いゲート絶縁膜とを介して不純物をイオン注入し
てソース領域およびドレイン領域を形成する工程と、前
記マスク材をマスクとして前記マスク材で覆われていな
い領域の前記導電性薄膜を選択的にエッチング除去し、
ゲート電極を形成する工程とを含むことを特徴とする半
導体装置の製造方法。
1. A step of forming a conductive thin film on a thin gate insulating film formed on a semiconductor substrate, and a mask material for preventing the impurity from penetrating into a lower layer thereof against ion implantation of the impurity. Of selectively forming on the conductive thin film,
Forming a source region and a drain region by ion-implanting impurities into a region not covered with the mask material through the conductive thin film and the thin gate insulating film; and using the mask material as a mask By selectively etching away the conductive thin film in the area not covered with
And a step of forming a gate electrode.
JP62069612A 1987-03-23 1987-03-23 Method for manufacturing semiconductor device Expired - Lifetime JPH0797566B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62069612A JPH0797566B2 (en) 1987-03-23 1987-03-23 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62069612A JPH0797566B2 (en) 1987-03-23 1987-03-23 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS63234520A JPS63234520A (en) 1988-09-29
JPH0797566B2 true JPH0797566B2 (en) 1995-10-18

Family

ID=13407850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62069612A Expired - Lifetime JPH0797566B2 (en) 1987-03-23 1987-03-23 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0797566B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01214173A (en) * 1988-02-23 1989-08-28 Sony Corp Manufacture of mos transistor
US6815317B2 (en) * 2002-06-05 2004-11-09 International Business Machines Corporation Method to perform deep implants without scattering to adjacent areas

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60116128A (en) * 1983-11-29 1985-06-22 Seiko Instr & Electronics Ltd Manufacture of semiconductor device
JPS61295627A (en) * 1985-06-24 1986-12-26 Nec Kansai Ltd Ion implantation method

Also Published As

Publication number Publication date
JPS63234520A (en) 1988-09-29

Similar Documents

Publication Publication Date Title
US5602055A (en) Method of manufacturing a semiconductor device incorporating a selectively deposited contact
KR960042942A (en) Semiconductor Device Forming Method
US6066534A (en) Method of manufacturing a field effect transistor
US6916718B2 (en) Approach to prevent undercut of oxide layer below gate spacer through nitridation
JP2886494B2 (en) Manufacturing method of integrated circuit chip
US5891771A (en) Recessed structure for shallow trench isolation and salicide process
JPH02192723A (en) Manufacture of semiconductor device
JPH0521793A (en) Semiconductor device and fabrication thereof
US5705437A (en) Trench free process for SRAM
US5550073A (en) Method for manufacturing an EEPROM cell
EP0877420A2 (en) Method of forming a polysilicon buried contact and a structure thereof
US5401678A (en) Transistor and method for fabricating the same
KR100231593B1 (en) Capacity manufacturing method of semiconductor
JPH0797566B2 (en) Method for manufacturing semiconductor device
JPH07326595A (en) Manufacture of semiconductor device
JP2544937B2 (en) Semiconductor device and manufacturing method thereof
EP0081999B1 (en) A method of fabricating a mos transistor on a substrate
JP2723221B2 (en) Method for manufacturing semiconductor device
KR0175367B1 (en) Semiconductor device and method of manufacturing the same
JPH0714916A (en) Isolation structure of mos field-effect transistor and its manufacture
JPH07153953A (en) Method for forming gate electrode having polyside structure
JP2606444B2 (en) Method for manufacturing semiconductor device
KR100382984B1 (en) Semiconductor device and method for manufacturing the same
JP3147374B2 (en) Semiconductor device
JP3064383B2 (en) Method for manufacturing semiconductor device