CN116169027A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
CN116169027A
CN116169027A CN202310099366.8A CN202310099366A CN116169027A CN 116169027 A CN116169027 A CN 116169027A CN 202310099366 A CN202310099366 A CN 202310099366A CN 116169027 A CN116169027 A CN 116169027A
Authority
CN
China
Prior art keywords
region
photoresist layer
source drain
photoresist
doping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310099366.8A
Other languages
Chinese (zh)
Inventor
李继禄
潘冬
刘念
晏恒
赵光宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Original Assignee
Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan Xinxin Semiconductor Manufacturing Co Ltd filed Critical Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority to CN202310099366.8A priority Critical patent/CN116169027A/en
Publication of CN116169027A publication Critical patent/CN116169027A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a method for manufacturing a semiconductor device. In the manufacturing method, after the first grid electrode is formed on the surface of the first doped region of the semiconductor substrate, a first photoresist layer is covered on the semiconductor substrate, a first through hole and a first weak blocking photoresist are formed in the first photoresist layer, when the first photoresist layer is used for carrying out second doping type ion implantation, the dosage of the dopant which is implanted into the first doped region through the first through hole is larger and is used for forming a heavily doped first source drain region and a heavily doped second source drain region, the dosage of the dopant which is implanted into the first doped region through the first weak blocking photoresist is smaller and is used for forming a lightly doped first LDD region and a lightly doped second LDD region, so that the source drain region and the LDD region of the MOS device are formed only by carrying out one ion implantation, the production cost of a semiconductor device comprising the MOS device is reduced, and the production period is shortened.

Description

Method for manufacturing semiconductor device
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor device.
Background
As semiconductor process technology advances, the integration level of integrated circuits increases, and the feature size of MOSFET, i.e., MOS, devices decreases, but as the feature size decreases to submicron, hot carrier injection effects become severe. Therefore, a lightly doped LDD (LightlyDopedDrain) region is added to the drain (and source) of the conventional MOS device to improve the peak electric field of the drain depletion region of the device, thereby reducing the hot carrier injection effect.
In order to add an LDD region into a MOS device, after a grid electrode of the MOS device is formed and before a side wall (spacer) is formed on the side wall of the grid electrode, light doping implantation is carried out through a self-alignment process to form a light doping region in a substrate on two sides of the grid electrode, after the side wall is formed, heavy doping implantation is carried out through a self-alignment process to respectively form a source region and a drain region on two sides of the grid electrode, the light doping region on the periphery of the source region is adjacent to the source region and extends to the lower portion of the grid dielectric layer to form an LDD region of a source end, and the light doping region on the periphery of the drain region is adjacent to the drain region and extends to the lower portion of the grid dielectric layer to form an LDD region of a drain end. The process adopts two injection to form the source region, the drain region and the LDD region of the same MOS device, has higher process cost and long production period, and particularly when different types of MOS devices are required to be formed on a substrate, the problems of process cost and production period are more prominent, so that an improved process capable of reducing the process cost and shortening the production period is required.
Disclosure of Invention
In order to reduce the process cost of a semiconductor device comprising a MOS device and shorten the production period, the invention provides a manufacturing method of the semiconductor device.
The manufacturing method of the semiconductor device provided by the invention comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first doping region with a first doping type;
forming a first grid electrode on the surface of the first doped region;
covering a first photoresist layer on the semiconductor substrate, forming first through holes respectively positioned at two sides of the first grid electrode in the first photoresist layer, and reducing the thickness of the first photoresist layer positioned between each first through hole and the first grid electrode so as to respectively form first weak blocking photoresist at two sides of the first grid electrode;
performing second doping type ion implantation by using the first photoresist layer as a mask, wherein part of dopants are implanted into the first doping region through the first through hole, and part of dopants are implanted into the first doping region through the first weak blocking photoresist; and
and annealing is carried out, a first source drain region and a second source drain region are respectively formed on two sides of the first grid electrode, and a first LDD region adjacent to the first source drain region and a second LDD region adjacent to the second source drain region are respectively formed on two sides of the first grid electrode.
Optionally, forming the first through hole and the first weak blocking photoresist in the first photoresist layer includes:
providing a photomask, wherein the photomask is provided with a shading area, a semi-shading area and a light transmission area;
exposing the first photoresist layer by using the photomask, wherein part of the first photoresist layer corresponds to the shading area and is not sensitized, part of the first photoresist layer corresponds to the semi-shading area and is partially sensitized in depth, and part of the first photoresist layer corresponds to the light transmitting area and is sensitized in full depth; and
and developing to remove the photosensitive part of the first photoresist layer so as to form the first through hole and the first weak blocking photoresist.
Optionally, the light shield includes a transparent substrate, and a light shielding layer and a semi-light shielding layer formed on a surface of one side of the transparent substrate, where the light shielding layer is used for preventing incident light from passing through, a region where the light shielding layer is formed is the light shielding region, the semi-light shielding layer allows a part of the incident light to pass through, a region where the semi-light shielding layer is formed is the semi-light shielding region, and a region of the transparent substrate uncovered by the light shielding layer and the semi-light shielding layer is the light transmitting region.
Optionally, after forming the first source drain region, the second source drain region, the first LDD region, and the second LDD region, the manufacturing method further includes: and forming side walls on the side walls of the first grid respectively.
Optionally, the first doping type is P-type, and the second doping type is N-type.
Optionally, the energy of the N-type implantation is 20 KeV-50 KeV, and the implantation dosage is 2E15cm -2 ～8E15cm -2 。
Optionally, the first gate is exposed or covered by the first photoresist layer when the second doping type ion implantation is performed.
Optionally, the semiconductor substrate further includes a second doped region having a second doping type, and before the first photoresist layer is covered on the semiconductor substrate, the manufacturing method further includes forming a second gate on a surface of the second doped region; the first photoresist layer covers the second doped region when the second doping type ion implantation is performed.
Optionally, after the second doping type ion implantation is completed, the manufacturing method further includes:
covering a second photoresist layer on the semiconductor substrate, forming second through holes respectively positioned at two sides of the second grid electrode in the second photoresist layer, and reducing the thickness of the second photoresist layer positioned between each second through hole and the second grid electrode so as to respectively form second weak blocking photoresist at two sides of the second grid electrode; and
performing first doping type ion implantation by using the second photoresist layer as a mask, wherein part of dopants are implanted into the second doping region through the second through hole, and part of dopants are implanted into the second doping region through the second weak blocking photoresist;
and annealing is carried out, a third source drain region and a fourth source drain region are respectively formed on two sides of the second grid electrode, and a third LDD region adjacent to the third source drain region and a fourth LDD region adjacent to the fourth source drain region are respectively formed on two sides of the second grid electrode.
Optionally, the ion implantation energy of the first doping type is 15 KeV-50 KeV, and the implantation dosage is 1E15cm -2 ～6E15cm -2 。
In the method for manufacturing the semiconductor device, after the first gate dielectric layer and the first gate electrode are formed on the surface of the first doped region of the semiconductor substrate, the first photoresist layer is covered on the semiconductor substrate, the first through hole and the first weak blocking photoresist are formed in the first photoresist layer, when the first photoresist layer is used for carrying out second doping type ion implantation, the dosage of the dopant which is implanted into the first doped region through the first through hole is larger and is used for forming a heavily doped first source drain region and a second source drain region, the dosage of the dopant which is implanted into the first doped region through the first weak blocking photoresist is smaller and is used for forming a lightly doped first LDD region and a lightly doped second LDD region, so that the source drain region and the LDD region of an MOS device are formed only by carrying out one ion implantation, the production cost of the semiconductor device comprising the MOS device is reduced, and the production period is shortened.
Drawings
Fig. 1 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention after forming a first gate.
Fig. 3 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention after forming a first photoresist layer.
Fig. 4 is a schematic cross-sectional view of a mask in a method for fabricating a semiconductor device according to an embodiment of the invention.
Fig. 5 is a schematic cross-sectional view illustrating a first photoresist layer patterned according to a method of fabricating a semiconductor device according to an embodiment of the invention.
Fig. 6 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention.
Fig. 7 is a schematic cross-sectional view illustrating a method for fabricating a semiconductor device according to an embodiment of the invention after removing the first photoresist layer.
Fig. 8 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention after performing a first doping type ion implantation.
Fig. 9 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention after annealing.
Fig. 10 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention after forming a sidewall.
Detailed Description
The method for manufacturing the semiconductor device of the present invention will be described in further detail with reference to the drawings and specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to scale precisely, but merely to facilitate a clear description of embodiments of the invention, which should not be considered as being limited to the particular shape of the regions shown in the drawings.
It is to be noted that the terms "first," "second," and the like, hereinafter are used to distinguish between similar elements, and it is understood that such terms are used interchangeably where appropriate. If the method described herein comprises a series of steps, and the order of the steps presented herein is not necessarily the only order in which the steps are performed, some of the described steps may be omitted and/or some other steps not described herein may be added to the method. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the structure in the figures is inverted or otherwise oriented (e.g., rotated), the exemplary term "above … …" may also include "below … …" and other orientations.
The embodiment of the invention relates to a manufacturing method of a semiconductor device. The semiconductor device may be any device comprising a MOS device. The semiconductor apparatus may include one or more MOS devices, and the structure and performance of the plurality of MOS devices may vary. For example, the semiconductor device may include at least one of an NMOS transistor, a PMOS transistor, a ZMOS (zero threshold voltage field effect transistor) transistor, and a BiMOS (bipolar metal oxide semiconductor) transistor, and the MOS device may be a High Voltage (HV) device or a Low Voltage (LV) device. The multiple MOS devices in the semiconductor apparatus may be integrated on the same semiconductor substrate, and other electronic components, such as flash memory or other suitable components, may also be integrated on the same semiconductor substrate.
Fig. 1 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention after forming a first gate. Referring to fig. 1 and 2, in step S1, a semiconductor substrate 100 is provided, the semiconductor substrate 100 including a first doping region 110 having a first doping type.
The semiconductor substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a group iii-v compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), etc., or may be other substrates known to those skilled in the art for carrying semiconductor components. The following description will take a silicon substrate as an example of the semiconductor substrate 100.
The semiconductor substrate 100 may have a first doping type, for example, a P-type doping (e.g., doped with boron or indium) or an N-type doping (e.g., doped with phosphorus or arsenic). As shown in fig. 2, a trench isolation structure is formed in the semiconductor substrate 100, extends from a surface of the semiconductor substrate 100 to an inside of the semiconductor substrate 100, and defines a plurality of active regions. The trench isolation structure may be a Deep Trench Isolation (DTI) or a Shallow Trench Isolation (STI), such as a Shallow Trench Isolation (STI) in this embodiment. The active region may have a P-doped or N-doped well region formed therein. And forming a MOS device on the surface of the active region or the surface of the well region.
As shown in fig. 2, the semiconductor substrate 100 illustratively includes at least one first doped region 110, where the first doped region 110 is, for example, an active region or a well region formed in an active region. The first doped region 110 has, for example, a P-type doping (labeled P), and an NMOS transistor or other N-type device may be formed in a surface region of the first doped region 110. Optionally, the semiconductor substrate 100 further comprises at least one second doped region 120, the second doped region 120 being of opposite doping type to the first doped region 110, for example. The second doped region 120 has, for example, an N-type doping, and a PMOS transistor or other P-type device may be formed in a surface region of the second doped region 120. In this embodiment, the first doped region 110 is adjacent to the second doped region 120, and the top of the second doped region 120 and the top of the first doped region 110 are isolated by Shallow Trench Isolation (STI). In other embodiments, however, the first doped region 110 and the second doped region 120 may not be adjacent.
Referring to fig. 1 and 2, in step S2, a first gate NG is formed on the surface of the first doped region 110. The first gate dielectric layer 101 is formed between the first gate NG and the semiconductor substrate 100, for example. In this embodiment, a second gate PG and a second gate dielectric layer 102 between the second gate PG and the semiconductor substrate 100 can also be formed on the surface of the second doped region 120. An oxide layer may be formed on the surface of the semiconductor substrate 100 around the first gate NG and the second gate PG. The first gate dielectric layer 101 and the second gate dielectric layer 102 may comprise silicon oxide (SiO) 2 ) Silicon oxynitride (SiON), hafnium oxide (HfO), or other suitable materials. The first gate NG and the second gate PG may include doped polysilicon, undoped polysilicon, or metal, wherein the undoped polysilicon may be doped by being exposed in a subsequent first doping type ion implantation or second doping type ion implantation. In another embodiment, the top surfaces of the first gate NG and the second gate PG may be formed with a hard mask layer.
Referring to fig. 1 and 3, in step S3, a first photoresist layer PR is covered on a semiconductor substrate 100. In this embodiment, the first photoresist layer PR is, for example, a positive photoresist. The first photoresist layer PR covers the first gate NG, the second gate PG and the semiconductor substrate 100 around them. In step S3, patterning is further performed on the first photoresist layer PR to form first through holes respectively located at two sides of the first gate NG in the first photoresist layer PR, and the thickness of the first photoresist layer PR located between each of the first through holes and the first gate NG is reduced to form a first weak blocking photoresist respectively located at two sides of the first gate NG. The patterning process may specifically include the following processes: first, as shown in fig. 4, taking a positive photoresist as an example, a mask 200 is provided, the mask 200 has a light shielding region 200a, a semi-light shielding region 200b and a light transmitting region 200c, and illustratively, the mask 200 includes a transparent substrate, and a light shielding layer and a semi-light shielding layer formed on one side surface of the transparent substrate, wherein the light shielding layer and the semi-light shielding layer include chromium or other suitable dark portion materials, for example, and the light shielding layer is used for preventing incident light from passing through, the area where the light shielding layer is formed is the light shielding region 200a, the light transmittance of the semi-light shielding layer is greater than that of the light shielding layer, the semi-light shielding layer allows a part of incident light (for example, greater than 0 and less than 100% of incident light) to pass through, the area where the semi-light shielding layer is formed is the semi-light shielding region 200b, and the transparent substrate area uncovered by the light shielding layer and the semi-shielding layer is the light transmitting region 200c; then, the mask 200 is used to expose the first photoresist layer PR, wherein the light shielding region 200a, the semi-light shielding region 200b and the light transmitting region 200c respectively correspond to different regions of the first photoresist layer PR, after exposure, a portion of the first photoresist layer PR corresponding to the light shielding region 200a is not substantially exposed, a portion of the first photoresist layer PR corresponding to the semi-light shielding region 200b is exposed, and all of the first photoresist layer PR corresponding to the light transmitting region 200c is exposed; then, development is performed to remove the portion of the first photoresist layer PR where the light is sensed, wherein the thickness of the first photoresist layer PR is reduced to form a first weak blocking photoresist in the region of the first photoresist layer PR where the light is sensed to a partial depth, and the first photoresist layer PR is removed to form a through hole in the region of the first photoresist layer PR where the light is sensed to a full depth.
As shown in fig. 5, after the patterning process, first through holes 10 are formed in the first photoresist layer PR at two sides of the first gate NG, so as to facilitate source and drain implantation; in addition, the thickness of a portion of the first photoresist layer PR is reduced to form a first weak blocking light barrier 20, in this embodiment, the first weak blocking light barrier 20 is located between each first through hole 10 and the first gate NG, and the capability of the first weak blocking light barrier 20 to block ions from passing through is reduced relative to the first photoresist layer PR in other regions, which is used for LDD implantation.
In step S3, other processes may be used to form the first through hole 10 and the first weak blocking photoresist 20 in the first photoresist layer PR. For example, in one embodiment, step S3 includes the following process: firstly, forming a bottom photoresist layer (positive photoresist), and exposing the bottom photoresist layer by using a photomask to make the bottom photoresist layer of the first through hole forming region sensitive; then, an upper photoresist layer is coated on the bottom photoresist layer, and the upper photoresist layer is exposed by using another photomask, so that the first through hole forming region and the upper photoresist layer of the first weak barrier photoresist forming region are exposed (the bottom photoresist layer is not exposed at this time); and developing to remove the upper photoresist layer and the bottom photoresist layer of the first through hole forming region, and removing the upper photoresist layer of the first weak barrier photoresist forming region, thereby forming the first through hole and the first weak barrier photoresist in a lamination of the bottom photoresist layer and the upper photoresist layer.
The first photoresist layer PR on the top surface of the first gate NG may remain or may be removed to expose the top surface of the first gate NG, if necessary, during the patterning process. In this embodiment, since the types of MOS devices to be formed in the second doped region 120 and the first doped region 110 are different, the doping types of the source and drain regions are different, and when the patterning process is performed on the first photoresist layer PR located in the first doped region 110, the second doped region 120 is blocked by the light blocking region 200a on the photomask 200, so that after the patterning process, the first photoresist layer PR located in the second doped region 120 is not sensitized and remains.
Fig. 6 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention. Referring to fig. 1 and 6, in step S4, a second doping type ion implantation 30 (for example, N-type ion implantation in this embodiment) is performed using the patterned first photoresist layer PR as a mask, wherein a portion of the dopant is implanted into the first doping region 110 through the first through hole 10 on both sides of the first gate NG to form a first source drain implantation region 111 and a second source drain implantation region 112, respectively, a portion of the dopant is implanted into the first doping region 110 through the first weak blocking photoresist 20 on both sides of the first gate NG to form a first LDD implantation region 113 and a second LDD implantation region 114, respectively, wherein the first source drain implantation region 111 and the first LDD implantation region 113 on the same side of the first gate NG are adjacent, the first source drain implantation region 111 is located on a side of the first LDD implantation region 113 away from the first gate NG, the second source drain implantation region 112 and the second LDD implantation region 114 on the same side of the first gate NG are adjacent, and the second source drain implantation region 112 is located on a side of the second LDD implantation region 114 away from the first gate NG.
In performing the above-described second doping type ion implantation 30, since the first weak blocking photoresist 20 blocks a portion of the dopant from passing therethrough, the dopant dose implanted into the first doping region 110 through the first through hole 10 is greater than the dopant dose implanted into the first doping region 110 through the first weak blocking photoresist 20, the doping concentrations of the first and second source drain implantation regions 111 and 112 are substantially the same, the doping concentrations of the first and second LDD implantation regions 113 and 114 are substantially the same, and the doping concentration of any one of the first and second source drain implantation regions 111 and 112 is greater than the doping concentration of any one of the first and second LDD implantation regions 113 and 114. The doping concentrations of the first LDD implant region 113 and the second LDD implant region 114 may be adjusted according to the thickness setting of the first weak blocking light barrier 20 and the setting of the ion implantation conditions. Optionally, the dopant used for the ion implantation of the second doping type is phosphorus, the implantation energy is 20 KeV-50 KeV, and the implantation dosage is 2E15cm -2 ～8E15cm -2 . After the second doping type ion implantation 30 is completed, the first photoresist layer PR is removed, and the resulting structure is shown in fig. 7.
Optionally, the method further includes forming a first doping type source/drain implant region and an LDD implant region in the second doping region 120, and forming the first source/drain implant region 111 and the first doping type implant region 30 by ion implantation (i.e. the second doping type ion implantation) together with the first doping region 110 to reduce the cost and shorten the production periodThe two source-drain implant regions 112, the first LDD implant region 113 and the second LDD implant region 114 may be formed by one ion implantation (first doping type implantation) in the second doping region 120 to form a source-drain implant region and an LDD implant region having a first doping type (P-type ion implantation in this embodiment, for example), and specifically may include the following steps: first, a second photoresist layer (not shown) is coated on the semiconductor substrate 100; then, forming second through holes respectively located at both sides of the second gate electrode PG in the second photoresist layer, and reducing the thickness of the second photoresist layer located between each of the second through holes and the second gate electrode PG to respectively form second weak blocking light barriers (not shown) at both sides of the second gate electrode PG; then, using the second photoresist layer as a mask, a first doping type ion implantation (e.g. P-type ion implantation such as B-implantation or BF-implantation is performed 2 Implantation), wherein a portion of the dopant is implanted into the second doped region 120 through the second through holes at two sides of the second gate PG to form a third source drain implanted region 121 and a fourth source drain implanted region 122 (refer to fig. 8), respectively, a portion of the dopant is implanted into the second doped region 120 through the second weak blocking light at two sides of the second gate PG to form a third LDD implanted region 123 and a fourth LDD implanted region 124, respectively, wherein the third source drain implanted region 121 and the third LDD implanted region 123 located at the same side of the second gate PG are adjacent, the third source drain implanted region 121 is located at a side of the third LDD implanted region 123 away from the second gate PG, the fourth source drain implanted region 122 and the fourth LDD implanted region 124 located at the same side of the second gate PG are adjacent, and the fourth source drain implanted region 122 is located at a side of the fourth LDD implanted region 124 away from the second gate PG. Optionally, the first doping type ion implantation energy is 15 KeV-50 KeV, and the implantation dosage is 1E15cm -2 ～6E15cm -2 . During the ion implantation of the first doping type, since the second weak blocking photoresist blocks part of the dopant from passing through, the dopant dose implanted into the second doping region 120 through the second through hole is greater than the dopant dose implanted into the second doping region 120 through the second weak blocking photoresist, the doping concentrations of the third source drain implantation region 121 and the fourth source drain implantation region 122 are substantially the same, and the doping concentrations of the third LDD implantation region 123 and the fourth LDD implantation region 12 are substantially the same4 and the doping concentration of any one of the third source drain implant region 121 and the fourth source drain implant region 122 is greater than the doping concentration of any one of the third LDD implant region 123 and the fourth LDD implant region 124. After the first doping type ion implantation is completed, the second photoresist layer is removed, and the resulting structure is shown in fig. 8.
Fig. 9 is a schematic cross-sectional structure of a semiconductor device after annealing in the method of manufacturing the semiconductor device according to an embodiment of the present invention. Referring to fig. 1 and 9, in step S5, annealing is performed to drive and stabilize dopant ions implanted into the first and second doped regions 110 and 120, forming first and second source drain regions 111a and 112a, respectively, on both sides of the first gate NG, and forming first and second LDD regions 113a and 114a adjacent to the first and second source drain regions 111a and 112a, respectively, on both sides of the first gate NG. In addition, in the present embodiment, a third source drain region 121a and a fourth source drain region 122a are also formed on both sides of the second gate electrode PG, and a third LDD region 123a adjacent to the third source drain region 121a and a fourth LDD region 124a adjacent to the fourth source drain region 122a are also formed on both sides of the second gate electrode PG, respectively. In another embodiment, the first source drain region 111a, the second source drain region 112a, the first LDD region 113a and the second LDD region 114a may be formed by annealing, and then the first doping type ion implantation and annealing may be performed to form the third source drain region 121a, the fourth source drain region 122a, the third LDD region 123a and the fourth LDD region 124a. For example, the first source drain region 111a is a source region, and the second source drain region 112a is a drain region; or the first source drain region 111a is a drain region and the second source drain region 112a is a source region.
Fig. 10 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention after forming a sidewall. Referring to fig. 10, optionally, a sidewall 130 (spacer) may be further formed on sidewalls of the first gate NG and the second gate PG to protect the first gate NG and the second gate PG. The sidewall 130 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the sidewall 130 may be formed as a single layer or multiple layers. In this embodiment, the first LDD region 113a extends from below the sidewall 130 on the same side of the first gate NG as the first LDD region 113a to below the first gate dielectric layer 101, the second LDD region 114a extends from below the sidewall 130 on the same side of the first gate NG as the second LDD region 114a to below the first gate dielectric layer 101, the third LDD region 123a extends from below the sidewall 130 on the same side of the second gate PG as the third LDD region 123a to below the second gate dielectric layer 102, and the fourth LDD region 124a extends from below the sidewall 130 on the same side of the second gate PG as the fourth LDD region 124a to below the second gate dielectric layer 102.
In this embodiment, the first gate NG formed on the surface of the first doped region 110, the first source drain region 111a, the second source drain region 112a, the first LDD region 113a and the second LDD region 114a distributed on two sides of the first gate NG form an NMOS transistor through the above process. The second gate PG formed on the surface of the second doped region 120, and the third source drain region 121a, the fourth source drain region 122a, the third LDD region 123a and the fourth LDD region 124a distributed on two sides of the second gate PG form a PMOS transistor. In the above process, only one ion implantation is required to form the first source drain region 111a, the second source drain region 112a, the first LDD region 113a and the second LDD region 114a, and only one ion implantation is required to form the third source drain region 121a, the fourth source drain region 122a, the third LDD region 123a and the fourth LDD region 124a, which is helpful to reduce the production cost and the production cycle of the semiconductor device including the MOS device. For example, the third source drain region 121a is a source region, and the fourth source drain region 122a is a drain region; or the third source drain region 121a is a drain region and the fourth source drain region 122a is a source region.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first doping region with a first doping type;
forming a first grid electrode on the surface of the first doped region;
covering a first photoresist layer on the semiconductor substrate, forming first through holes respectively positioned at two sides of the first grid electrode in the first photoresist layer, and reducing the thickness of the first photoresist layer positioned between each first through hole and the first grid electrode so as to respectively form first weak blocking photoresist at two sides of the first grid electrode;
performing second doping type ion implantation by using the first photoresist layer as a mask, wherein part of dopants are implanted into the first doping region through the first through hole, and part of dopants are implanted into the first doping region through the first weak blocking photoresist; and
and annealing is carried out, a first source drain region and a second source drain region are respectively formed on two sides of the first grid electrode, and a first LDD region adjacent to the first source drain region and a second LDD region adjacent to the second source drain region are respectively formed on two sides of the first grid electrode.
2. The method of claim 1, wherein forming the first via and the first weak blocking photoresist in the first photoresist layer comprises:
providing a photomask, wherein the photomask is provided with a shading area, a semi-shading area and a light transmission area;
exposing the first photoresist layer by using the photomask, wherein part of the first photoresist layer corresponds to the shading area and is not sensitized, part of the first photoresist layer corresponds to the semi-shading area and is partially sensitized in depth, and part of the first photoresist layer corresponds to the light transmitting area and is sensitized in full depth; and
and developing to remove the photosensitive part of the first photoresist layer so as to form the first through hole and the first weak blocking photoresist.
3. The method of claim 2, wherein the mask comprises a transparent substrate, and a light shielding layer and a semi-light shielding layer formed on a side surface of the transparent substrate, the light shielding layer is used for preventing incident light from passing through, a region where the light shielding layer is formed is the light shielding region, the semi-light shielding layer allows a part of the incident light to pass through, a region where the semi-light shielding layer is formed is the semi-light shielding region, and a region of the transparent substrate uncovered by the light shielding layer and the semi-light shielding layer is the light transmitting region.
4. The method of manufacturing of claim 1, wherein after forming the first source drain region, the second source drain region, the first LDD region, and the second LDD region, the method further comprises:
and forming side walls on the side walls of the first grid respectively.
5. The method of claim 1, wherein the first doping type is P-type and the second doping type is N-type.
6. The method of claim 1, wherein the second doping type has an ion implantation energy of 20 KeV-50 KeV and an implantation dose of 2E15cm -2 ～8E15cm -2 。
7. The method of claim 1, wherein the first gate is exposed or covered by the first photoresist layer when the second doping type ion implantation is performed.
8. The method of any of claims 1-7, wherein the semiconductor substrate further comprises a second doped region having a second doping type, the method further comprising forming a second gate on a surface of the second doped region prior to overlaying the first photoresist layer on the semiconductor substrate; the first photoresist layer covers the second doped region when the second doping type ion implantation is performed.
9. The method of claim 8, wherein after completing the second doping type ion implantation, the method further comprises:
covering a second photoresist layer on the semiconductor substrate, forming second through holes respectively positioned at two sides of the second grid electrode in the second photoresist layer, and reducing the thickness of the second photoresist layer positioned between each second through hole and the second grid electrode so as to respectively form second weak blocking photoresist at two sides of the second grid electrode; and
performing first doping type ion implantation by using the second photoresist layer as a mask, wherein part of dopants are implanted into the second doping region through the second through hole, and part of dopants are implanted into the second doping region through the second weak blocking photoresist; and
and annealing is carried out, a third source drain region and a fourth source drain region are respectively formed on two sides of the second grid electrode, and a third LDD region adjacent to the third source drain region and a fourth LDD region adjacent to the fourth source drain region are respectively formed on two sides of the second grid electrode.
10. The method of claim 9, wherein the first doping type ion implantation has an energy of 15KeV to 50KeV and an implantation dose of 1E15cm -2 ～6E15cm -2 。
CN202310099366.8A 2023-02-02 2023-02-02 Method for manufacturing semiconductor device Pending CN116169027A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310099366.8A CN116169027A (en) 2023-02-02 2023-02-02 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310099366.8A CN116169027A (en) 2023-02-02 2023-02-02 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
CN116169027A true CN116169027A (en) 2023-05-26

Family

ID=86417801

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310099366.8A Pending CN116169027A (en) 2023-02-02 2023-02-02 Method for manufacturing semiconductor device

Country Status (1)

Country Link
CN (1) CN116169027A (en)

Similar Documents

Publication Publication Date Title
CN108807281B (en) Semiconductor device and method of forming the same
US6586306B2 (en) Method for fabricating semiconductor device
JP2000196079A (en) Manufacture of mos semiconductor
US6767778B2 (en) Low dose super deep source/drain implant
KR100391959B1 (en) Semiconductor apparatus and method of manufacture
GB2313233A (en) CMOS transistor and manufacturing method therefor
TWI438886B (en) Esd protection device and method for fabricating the same and integrated circuit
US6083783A (en) Method of manufacturing complementary metallic-oxide-semiconductor
JPH11330269A (en) Method for forming twin well
CN108470680B (en) Method for manufacturing semiconductor structure
US6225229B1 (en) Removable photoresist spacers in CMOS transistor fabrication
CN116169027A (en) Method for manufacturing semiconductor device
US8178932B2 (en) Semiconductor device having transistors
JPH06260607A (en) Semiconductor device and its manufacture
CN112928068B (en) Method for saving light doping mask number in CMOS production process
KR100264211B1 (en) Method for fabricating semiconductor device
KR0144124B1 (en) Fabrication method of ldd mosfet
KR100334968B1 (en) Method for fabricating buried channel type PMOS transistor
JPH07297296A (en) Method of manufacturing semiconductor device
KR100486084B1 (en) Method for fabricating ldd type cmos transistor
KR100275960B1 (en) A method for fabricating semiconductor device
KR100327438B1 (en) method for manufacturing of low voltage transistor
KR100439102B1 (en) Method for manufacturing a semiconductor device
JPH06196642A (en) Semiconductor device and manufacture thereof
KR20040003494A (en) Method of manufacturing a semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Country or region after: China

Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province

Applicant after: Wuhan Xinxin Integrated Circuit Co.,Ltd.

Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province

Applicant before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd.

Country or region before: China