CN113327846A - Analog circuit comprising high-resistance resistor and GGNMOS ESD (grounded-gate bipolar transistor) and manufacturing method thereof - Google Patents
Analog circuit comprising high-resistance resistor and GGNMOS ESD (grounded-gate bipolar transistor) and manufacturing method thereof Download PDFInfo
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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Abstract
The invention discloses an analog circuit comprising a high-resistance resistor and a GGNMOS ESD and a manufacturing method thereof. Forming a first STI, a second STI, a first high-voltage P well and a second high-voltage P well on a semiconductor substrate; carrying out polycrystalline silicon deposition on the surface of the semiconductor substrate to form a polycrystalline silicon area; opening a window in a polysilicon region on a semiconductor substrate; and performing high-resistance injection and high-energy injection to form high-resistance polysilicon, N + polysilicon, a first ESD injection well and a second ESD injection well. The two photomasks are combined into one photomask by utilizing high-resistance injection and high-energy injection, the problem that the process for manufacturing the analog circuit comprising the high-resistance resistor and the GGNMOS ESD is complex is solved, and the manufacturing cost is saved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to an analog circuit comprising a high-resistance resistor and a GGNMOS ESD and a manufacturing method thereof.
Background
High resistance and GGNMOS (gate-grounded NMOS electrostatic discharge) ESD are widely used in analog circuits in chip design. A schematic cross-sectional view of a high-resistance device in an analog circuit in the prior art is shown in fig. 1, and the high-resistance device includes a first STI1(Shallow Trench Isolation), a first high-voltage P-well 3, a first P-type body region 2, and a high-resistance polysilicon 4. Fig. 2 shows a schematic cross-sectional view of a GGNMOS ESD device in an analog circuit in the prior art, where the GGNMOS ESD device includes a plurality of second STIs 5, a second high-voltage P-well 6, a second P-type body region 7, two N-type body regions 8, a first ESD injection well 9, and N + polysilicon 10.
As can be seen from fig. 1 and 2, the standard high-resistance resistor and the GGNMOS ESD device have a certain difference in structure, the standard high-resistance resistor does not have an ESD injection well, and the GGNMOS ESD device has an ESD injection well. The manufacturing process has the problems of complex steps and high manufacturing cost.
Disclosure of Invention
The invention provides an analog circuit comprising a high-resistance resistor and a GGNMOS ESD and a manufacturing method thereof, aiming at overcoming the defects of complex process steps and higher manufacturing cost of manufacturing the analog circuit comprising the high-resistance resistor and the GGNMOS ESD in the prior art.
The invention solves the technical problems through the following technical scheme:
in a first aspect, the invention provides an analog circuit comprising a high-resistance resistor and a GGNMOS ESD and a manufacturing method thereof, wherein the high-resistance resistor comprises a first STI, a first high-voltage P well, a first P-type body region and high-resistance polysilicon; the GGNMOS ESD comprises a plurality of second STI, a second high-voltage P well, a second P-type body region, two N-type body regions, a first ESD injection well and N + polysilicon; the manufacturing method comprises the following steps:
forming the first STI, the second STI, the first high-voltage P-well and the second high-voltage P-well on a semiconductor substrate;
carrying out polycrystalline silicon deposition on the surface of the semiconductor substrate to form a polycrystalline silicon area;
opening a window in the polycrystalline silicon region on the semiconductor substrate;
performing high-resistance injection and high-energy injection to form the high-resistance polysilicon, the N + polysilicon, the first ESD injection well and a second ESD injection well, wherein the second ESD injection well is positioned above the second high-voltage P well of the GGNMOS ESD;
and forming the first P-type body region, the second P-type body region and the two N-type body regions.
Preferably, the step of performing high resistance injection and high energy injection comprises:
performing high-resistance injection to form a high-resistance structure in the region where the high-resistance polysilicon and the N + polysilicon are located;
performing high-energy implantation to form the first ESD implantation trap and the second ESD implantation trap.
Preferably, the step of performing high resistance injection and high energy injection comprises:
performing high-energy implantation to form the first ESD implantation trap and the second ESD implantation trap;
and performing high-resistance injection to form a high-resistance structure in the region where the high-resistance polysilicon and the N + polysilicon are located.
Preferably, the step of forming the first P-type body region, the second P-type body region and the two N-type body regions includes:
performing P + type ion implantation on two sides of the first STI and a region between the second ESD implantation trap and the second STI above the second ESD implantation trap and the second high-voltage P trap to form the first P type body region and the second P type body region;
and performing N + type ion implantation in an upper region between two sides of the region where the N + polysilicon is located and the second ESD implantation trap to form two N-type body regions.
Preferably, the concentration of the N + type ion implantation is 3E15/cm2-4E15/cm2。
Preferably, the high resistance implantation is performed by implanting boron ions, and the boron ions stay in the polysilicon region.
Preferably, the high-energy implantation adopts P-type ion implantation, and the P-type ions are gathered below the region where the high-resistance polysilicon and the N + polysilicon are located.
Preferably, during the high energy implantation, the concentration of the implanted P-type ions is adjusted according to the performance requirement of the first ESD implantation well.
Preferably, the concentration of the boron ion implantation is 4.5-5E 14/cm2The dosage of the boron ion implantation is 1-5E 13/cm2。
In a second aspect, the present invention provides an analog circuit including a high resistance resistor and a GGNMOS ESD, where the high resistance resistor and the GGNMOS ESD are manufactured by the method for manufacturing the analog circuit including the high resistance resistor and the GGNMOS ESD according to the first aspect.
The positive progress effects of the invention are as follows: according to the analog circuit comprising the high-resistance resistor and the GGNMOS ESD and the manufacturing method thereof, the high-resistance injection insertion high-energy ESD injection replaces an independent ESD injection well photomask, namely, the high-resistance injection and the high-energy injection are utilized to realize that two photomasks are combined into one photomask, the free GGNMOS ESD is manufactured, the problem that the process for manufacturing the analog circuit comprising the high-resistance resistor and the GGNMOS ESD is complex is solved, and the manufacturing cost is saved.
Drawings
FIG. 1 is a schematic cross-sectional view of a high resistance device in a prior art analog circuit.
Fig. 2 is a schematic cross-sectional view of a GGNMOS ESD device in a prior art analog circuit.
Fig. 3 is a flowchart of a method for manufacturing an analog circuit including a high-resistance resistor and a GGNMOS ESD in embodiment 1 of the present invention.
Fig. 4 is a first cross-sectional view of the high resistance device in step S4 of fig. 3.
Fig. 5 is a schematic cross-sectional view of the GGNMOS ESD device of step S4 of fig. 3.
Fig. 6 is a second cross-sectional view of the high resistance device in step S4 in fig. 3.
Fig. 7 is a second schematic cross-sectional view of the GGNMOS ESD device of step S4 of fig. 3.
Fig. 8 is a schematic cross-sectional view of a high-resistance device produced based on the production method of example 1.
Fig. 9 is a schematic cross-sectional view of a GGNMOS ESD device produced based on the fabrication method of example 1.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
The embodiment provides a manufacturing method of an analog circuit including a high resistance resistor and a GGNMOS ESD, and as shown in fig. 3, the manufacturing method disclosed by the embodiment includes the following steps:
step S1, forming a first STI1, a second STI5, a first high voltage P-well 3, and a second high voltage P-well 6 on the semiconductor substrate.
In the present embodiment, when the first STI1 and the second STI5 are fabricated on the semiconductor substrate, in other words, STI regions are fabricated. Etching grooves in preset regions of the first high-voltage P trap 3 and the second high-voltage P trap 6 through a mask, and then filling SiO into the grooves2(silica), SiO filling by instrument pair2The trenches are polished to form regions corresponding to the first STI1 and the second STI5, i.e., shallow trench isolation regions.
Step S2, performing polysilicon deposition on the surface of the semiconductor substrate to form a polysilicon region.
Polysilicon deposition over the formed first and second STI1, 5 forms a polysilicon layer, i.e., a polysilicon region.
Step S3, a window is opened in a polysilicon region on a semiconductor substrate.
And coating optical cement on the polycrystalline silicon layer, wherein the optical cement is used for blocking boron ion injection or injection of other ions when subsequent high-resistance injection and high-energy injection are carried out. Thus, as shown in fig. 4 and 5, a window is opened in the gate polysilicon region not covered by the photoresist.
Step S4, high resistance implantation and high energy implantation are performed to form high resistance polysilicon, N + polysilicon 10, first ESD implantation well 9 and second ESD implantation well 11. A cross-sectional schematic of the high resistance and GGNMOS ESD device after this step is shown in fig. 6 and 7.
The high-resistance injection adopts boron ion injection, and the boron ions stay in the polycrystalline silicon area.
Specifically, referring to fig. 4 and 5, the polysilicon region is implanted with boron ions in the direction indicated by the arrow, and the boron ions may be heavily doped boron ions, so that the boron ions stay in the polysilicon region. High resistance injection is a term of art, and the range of energies employed for high resistance injection is clear to those skilled in the art. In this embodiment, the process is mainly applied to 10V to 12V (volt) devices, and diffusion is not required.
In one possible implementation, the depth of the boron ion implantation may be 0.5 to 1 μm, and the implantation angle may be 3 to 6 degrees, and those skilled in the art will understand that the implantation depth and the implantation angle may be determined according to a specific process, and are not particularly limited herein.
Wherein, the high-energy implantation adopts P-type ion implantation, and the P-type ions are gathered below the region where the high-resistance polysilicon and the N + polysilicon 10 are located.
Further, referring to fig. 6 and 7, when the high energy implantation is performed on the region above the gate high resistance polysilicon and the N + polysilicon 10 not covered by the photoresist, the implantation is performed along the direction indicated by the arrow. And continuing to inject P-type ions into the polysilicon region subjected to the high-resistance injection, so that the P-type ions penetrate through the N + polysilicon 10 and the region where the high-resistance polysilicon is located. In other words, the P-type ions are gathered under the regions where the high-resistance polysilicon and the N + polysilicon 10 are located, and the first ESD implantation well 9 and the second ESD implantation well 11 are formed.
Preferably, during the high energy implantation, the concentration of implanted P-type ions may be adjusted according to the performance requirements of the first ESD implant well 9.
In this embodiment, the concentration of the implanted P-type ions may be adjusted according to the performance requirement of the first ESD implantation well 9 included in the GGNMOS ESD device to enhance the performance of the GGNMOS ESD device.
In one possible implementation, the step of performing the high resistance injection and the high energy injection in step S4 includes:
firstly, high-resistance injection is carried out to form a high-resistance structure in the area where the high-resistance polysilicon and the N + polysilicon 10 are located;
high-energy implantation is performed again to form a first ESD implantation well 9 and a second ESD implantation well 11.
In another possible implementation manner, the step of performing the high resistance injection and the high energy injection in step S4 includes:
performing high-energy injection to form a first ESD injection well 9 and a second ESD injection well 11;
then, high-resistance injection is performed to form a high-resistance structure in the region where the high-resistance polysilicon and the N + polysilicon 10 are located.
The concentration of the boron ion implantation is 4.5-5E 14/cm2The dosage of the boron ion implantation is 1-5E 13/cm2。
In this embodiment, when the first ESD injection well 9 and the second ESD injection well 11 are formed, high resistance injection and high energy injection need to be performed, and the order of the high resistance injection and the high resistance injection is not particularly limited. The implantation energy of the normal ESD implantation trap is 100-150 Kev, and in the process of high-resistance implantation, the implantation energy needs to be increased because a polycrystalline silicon region where boron ions stay can generate a certain blocking effect. Can reach 200-300 Kev, but the dosage is basically not changed much compared with the prior art, and the embodiment of the application adopts 1-5E 13/cm2The dose of the implant. Those skilled in the art can make adjustments according to actual situations, and details are not described herein.
Step S5, forming a first P-type body region 2, a second P-type body region 7, and two N-type body regions 8. Cross-sectional schematic diagrams of the high resistance and GGNMOS ESD devices after this step are shown in fig. 8 and 9.
In the present embodiment, referring to fig. 8, first P type body regions 2 in the high resistance are formed by performing P + type ion implantation at both sides of the first STI 1. Referring to fig. 9, in the region between the second STIs 5, a second P type body region 7 is formed by performing P + -type ion implantation. It will be understood by those skilled in the art that the implantation depth and the implantation angle may be determined according to the specific process when implanting the P + type ions.
Wherein, step S5 includes:
p + -type ion implantation is performed at both sides of the first STI1 and a region between the second STI5 located above the second ESD implant well 11 and the second high-voltage P well 6 to form the first and second P-type body regions 2 and 7.
And N + type ion implantation is carried out in the upper area between the two sides of the area where the N + polysilicon 10 is located and the second ESD implantation trap 11 to form two N type body areas 8.
Wherein the concentration of N + type ion implantation is 3E15/cm2-4E15/cm2。
Specifically, since the first STI1 is isolated from the second ESD implantation well 11 in the high resistance resistor, the resistance of the resistor itself is not affected. In other words, the high-resistance polysilicon is a surface device whose function is not affected by the well implant. In addition, the GGNMOS ESD is a bulk device, and the influence of the resistance of boron ions staying in the polysilicon region on the GGNMOS ESD device is limited, so that the performance of the high-resistance resistor and the GGNMOS ESD device manufactured according to the manufacturing process in the embodiment of the application meets the process requirements.
Further, referring to fig. 9, in the process of manufacturing the GGNMOS ESD device, when N + type ions are implanted into the region between the second ESD implantation well 11 and the two sides of the region where the N + polysilicon 10 is located, the high resistance implantation corresponding to the P + type ions above the gate of the GGNMOS ESD device generates a counter impact with the high concentration implantation corresponding to the N + type ions.
In this embodiment, as shown in fig. 9, a sidewall blocking region 13 is formed on one side of a region corresponding to the formation of the N + polysilicon mixed high-resistance polysilicon 12, and the sidewall blocking region 13 may be an alloy blocking layer or a silicide blocking layer. The silicon oxide is deposited first and then is processed by a photomask, but in the process, the silicon oxide barrier layer is not exposed, the non-gate polysilicon area which is not covered by the photoresist is etched, and then the etched polysilicon area is cleaned to form the side wall of the gate, namely the side wall barrier area 13.
The embodiment provides a manufacturing method of an analog circuit comprising a high-resistance resistor and a GGNMOS ESD. Forming a first STI, a second STI, a first high-voltage P well and a second high-voltage P well on a semiconductor substrate; carrying out polycrystalline silicon deposition on the surface of the semiconductor substrate to form a polycrystalline silicon area; opening a window in a polysilicon region on a semiconductor substrate; and performing high-resistance injection and high-energy injection to form high-resistance polysilicon, N + polysilicon, a first ESD injection well and a second ESD injection well. The high-resistance injection insertion high-energy ESD injection is used for replacing an independent ESD injection well photomask, namely, the high-resistance injection and the high-energy injection are used for combining two photomasks into one photomask, so that the free GGNMOS ESD is manufactured, the problem that the process for manufacturing the analog circuit comprising the high-resistance resistor and the GGNMOS ESD is complex is solved, and the manufacturing cost is saved.
Example 2
This embodiment provides an analog circuit including a high resistance resistor and a GGNMOS ESD, which are manufactured by the method of embodiment 1.
Compared with the traditional manufacturing mode of a standard high-resistance resistor and a GGNMOS ESD device, the analog circuit comprising the high-resistance resistor and the GGNMOS ESD provided by the embodiment utilizes high-resistance injection to insert high-energy ESD injection to replace a single ESD injection well photomask, namely, the high-resistance injection and the high-energy injection are utilized to realize that two photomasks are combined into one photomask, so that free GGNMOS ESD is manufactured, the problem that the process for manufacturing the analog circuit comprising the high-resistance resistor and the GGNMOS ESD is complex is solved, and the manufacturing cost is saved. Meanwhile, the efficacy of the GGNMOS ESD device is adjusted by adjusting the concentration of the implanted ions according to the performance requirement of the first ESD implantation trap, and the competitiveness of the power device is improved.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (10)
1. A manufacturing method of an analog circuit comprising a high-resistance resistor and GGNMOS ESD (grounded-gate bipolar transistor) ESD (electrostatic discharge), wherein the high-resistance resistor comprises a first STI (shallow trench isolation), a first high-voltage P well, a first P-type body region and high-resistance polysilicon; the GGNMOS ESD comprises a plurality of second STI, a second high-voltage P well, a second P-type body region, two N-type body regions, a first ESD injection well and N + polysilicon;
the manufacturing method is characterized by comprising the following steps:
forming the first STI, the second STI, the first high-voltage P-well and the second high-voltage P-well on a semiconductor substrate;
carrying out polycrystalline silicon deposition on the surface of the semiconductor substrate to form a polycrystalline silicon area;
opening a window in the polycrystalline silicon region on the semiconductor substrate;
performing high-resistance injection and high-energy injection to form the high-resistance polysilicon, the N + polysilicon, the first ESD injection well and a second ESD injection well, wherein the second ESD injection well is positioned above the second high-voltage P well of the GGNMOS ESD;
and forming the first P-type body region, the second P-type body region and the two N-type body regions.
2. The method of fabricating an analog circuit comprising a high resistance resistor and a GGNMOS ESD according to claim 1, wherein the steps of performing high resistance injection and high energy injection comprise:
performing high-resistance injection to form a high-resistance structure in the region where the high-resistance polysilicon and the N + polysilicon are located;
performing high-energy implantation to form the first ESD implantation trap and the second ESD implantation trap.
3. The method of fabricating an analog circuit comprising a high resistance resistor and a GGNMOS ESD according to claim 1, wherein the steps of performing high resistance injection and high energy injection comprise:
performing high-energy implantation to form the first ESD implantation trap and the second ESD implantation trap;
and performing high-resistance injection to form a high-resistance structure in the region where the high-resistance polysilicon and the N + polysilicon are located.
4. The method of fabricating an analog circuit comprising a high resistance resistor and a GGNMOS ESD according to claim 1, wherein the step of forming the first P-type body region, the second P-type body region, and the two N-type body regions comprises:
performing P + type ion implantation on two sides of the first STI and a region between the second ESD implantation trap and the second STI above the second ESD implantation trap and the second high-voltage P trap to form the first P type body region and the second P type body region;
and performing N + type ion implantation in an upper region between two sides of the region where the N + polysilicon is located and the second ESD implantation trap to form two N-type body regions.
5. The method of claim 4 wherein the N + type ion implantation concentration is 3E15/cm2-4E15/cm2。
6. The method of claim 1, wherein the high resistance implant uses boron ion implant, and the boron ions stay in the polysilicon region.
7. The method of claim 1, wherein the high energy implant is a P-type ion implant, and the P-type ions are collected under the region where the high resistance poly-si and the N + poly-si are located.
8. The method of claim 7, wherein during the high energy implantation, the concentration of the implanted P-type ions is adjusted according to the performance requirement of the first ESD implantation well.
9. The method of claim 6, wherein the boron ion implantation concentration is 4.5-5E 14/cm2The dosage of the boron ion implantation is 1-5E 13/cm2。
10. An analog circuit comprising a high resistance resistor and a GGNMOS ESD, wherein the high resistance resistor and the GGNMOS ESD are formed using the method of any of claims 1-9 for forming an analog circuit comprising a high resistance resistor and a GGNMOS ESD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010672739.2A CN113327846B (en) | 2020-07-14 | 2020-07-14 | Analog circuit comprising high-resistance resistor and GGNMOS ESD and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010672739.2A CN113327846B (en) | 2020-07-14 | 2020-07-14 | Analog circuit comprising high-resistance resistor and GGNMOS ESD and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113327846A true CN113327846A (en) | 2021-08-31 |
| CN113327846B CN113327846B (en) | 2023-08-22 |
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Citations (7)
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| US20030207543A1 (en) * | 2002-01-14 | 2003-11-06 | Salling Craig T. | Structure and method of MOS transistor having increased substrate resistance |
| US20060125039A1 (en) * | 2004-12-15 | 2006-06-15 | Tower Semiconductor Ltd. | Low parasitic capacitance schottky diode |
| US20070158748A1 (en) * | 2006-01-10 | 2007-07-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Resistor structure for ESD protection circuits |
| US20090166740A1 (en) * | 2007-12-31 | 2009-07-02 | Anup Bhalla | Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection |
| US20120018775A1 (en) * | 2010-05-05 | 2012-01-26 | Peking University | Electrostatic discharge protection device and method for fabricating the same |
| CN102969312A (en) * | 2012-12-18 | 2013-03-13 | 江南大学 | High-voltage ESD (electro-static discharge) protective device triggered by bidirectional substrate |
| WO2017092408A1 (en) * | 2015-12-01 | 2017-06-08 | 无锡华润上华半导体有限公司 | Method for manufacturing polysilicon high resistance |
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Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030207543A1 (en) * | 2002-01-14 | 2003-11-06 | Salling Craig T. | Structure and method of MOS transistor having increased substrate resistance |
| US20060125039A1 (en) * | 2004-12-15 | 2006-06-15 | Tower Semiconductor Ltd. | Low parasitic capacitance schottky diode |
| US20070158748A1 (en) * | 2006-01-10 | 2007-07-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Resistor structure for ESD protection circuits |
| US20090166740A1 (en) * | 2007-12-31 | 2009-07-02 | Anup Bhalla | Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection |
| US20120018775A1 (en) * | 2010-05-05 | 2012-01-26 | Peking University | Electrostatic discharge protection device and method for fabricating the same |
| CN102969312A (en) * | 2012-12-18 | 2013-03-13 | 江南大学 | High-voltage ESD (electro-static discharge) protective device triggered by bidirectional substrate |
| WO2017092408A1 (en) * | 2015-12-01 | 2017-06-08 | 无锡华润上华半导体有限公司 | Method for manufacturing polysilicon high resistance |
| CN106816433A (en) * | 2015-12-01 | 2017-06-09 | 无锡华润上华半导体有限公司 | A kind of manufacture method of polysilicon high-ohmic |
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| CN113327846B (en) | 2023-08-22 |
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