200308052 玖、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路，且特別是有關於一種在兩 導體間建立導電連接之穿透接點。 【先前技術】 現在’當製造積體電路時，介金屬（intermetallic)接點，其 直徑小於在其下方與上方之金屬執跡（track)之寬度，係用以 導電性連接兩金屬執跡。接點區中之金屬執跡間之重疊部份 必需加入積體電路佈局之考量中。 圖3 2顯示現今設計IC時之示範佈局之一部份。位於上結構 面或導體面内之四個金屬執跡500，502，504與506由實線示 於圖32中。在相關方式中，位於下結構面内之四個金屬軌跡 5 0 8，5 1 0，5 1 2與5 1 4由虛線表示此；此下結構面位於該上結 構面之下方且彼此隔開。由圖32可看出，金屬執跡500-514 依此方式示範般排列於圖3 2，使得分別在某一結構面内之：金 屬軌跡500_5〇6與508-514彼此平行延伸，且不同結構面之金屬 轨跡500-5 1 4以成對方式排列使得某一結構面之金屬軌跡往 上延伸至接點處516，518，520與522,而另一結構面之各自 金屬軌跡以相同方向延伸。可發現，各金屬執跡5 0 0 - 5 1 4，亦 即上結構面之金屬軌跡與該下結構面之金屬執跡，在接點處 516，518，520 與 522 具有寬度加大區 524，526，528，530 與 5 3 2，5 3 4，5 3 6與5 3 8 ;此現象之參考是，只能看見下結構面 之金屬執跡50 8-514之寬度加大區532-538之短區之外形，因為 外形之其他部份被上結構面之金屬執跡5 〇 〇 - 5 0 6之寬度加大 區524-530所遮住。寬度加大區524-528由介金屬接點540, 200308052 542，544與546形成電性内連接；介金屬接點540，542，544 與5 46之橫截面小於該寬度加大區且在製程中，其係製造於獨 立於導體面之構造外之構造步驟中。 藉由雙箭頭，圖3 2額外顯示最小寬度w 1，w 2與最小間距s 1， s 2，當設計電路時必需考量於此佈局中，且其根據製造方法， 比如用於往後製造中之CMOS方法，而由設計規則所決定。最 小寬度w 1，w2分別決定上與下結構面之金屬執道之最小寬 度，與比如從用以構造該各別結構面之微影步驟中之實際限 制所得之結果。最小間距s 1，s2分別決定金屬執道間之最小距 離或上與下結構面上對第一特徵與第二特徵間之間距/與比 如從用以構造該各別結構面之微影步驟中之實際限制所得之 結果。 由圖32也可發現，各金屬執道500-514在各接點處516-522 以朝外方向在各側邊上寬度上加大了 X長度。另可看出，寬度 加大區524-538大於介金屬接點540-546之橫截面。所得之重疊 部份必需加入介金屬接點540-546之孔洞之結構與上與下結 構面之金屬執道之結構間之對準誤差所得之製造容忍度之考 量中。因為在寬度上加大了 X長度，可能之最小導體間距si與 s2分別無法使用於具介金屬接點之金屬執道例之佈局中。然 而，具最小寬度之同一結構面之兩金屬軌道間之最小間距可 由sl+X而有效給予，因而，加大了 X值，亦即最小導體寬度必 需加大之長度，因為考量到介金屬接點而之必要性重疊。 上述同一結構面之金屬軌道間之最小間距之加入導致1C整 合度變小。然而，變小的晶片面積在許多1C使用領域中是需 200308052 要的，因為晶片面積通常必需符合基本需求，比如在晶片卡 之領域中。 參考圖3 2描述之該接點形成方式之另一缺點在於，因為上 述理由，介金屬接點之直徑必需永遠小於導體，因而成為電 子遷移之關鍵點。 【發明内容】 因此，需要一種接點形成方式，其有較高之整合度與較高 之電子遷移抗性。 」 本發明之目的是提供一種在一第一導體與一第二導體間形 成導電連接之一穿透接點，及其製造方法，使得該穿透接點 可改良電子特性及/或允許較高之整合度。 該目的係由根據申請專利範圍第1項之方法以及根據申請 專利範圍第1 3項之穿透接點達成。 本發明係根據，為允許在一導體面内構成該導體，使得各 導體間之間距為製程技術所能達到之最小可能間距，必需不 同於傳統方式之構成導體於接點處於各穿透接點。根據本發 明，某一導體或圖形與穿透接點係在同一製程步驟内形成於 該接點區内，亦即藉由形成一接點開口於該接點區内，接著 填滿該接點開口至該導體之一溝槽終止處。此效果在於，該 穿透接點内之該導體之寬度自動調整至該穿透接點之大小。 因為形成該接點開口之步驟以及依自調整方法調整至該穿透 接點之大小之後續之構成寬廣導體區之步驟，以及該穿透接 點之形成步驟係實施於不同於在該接點區外構成該導體之步 驟内，寬度之增加不會導致在導體面之相鄰導體間必需考量 -9- 200308052 之任何最小間距之變大，因為當形成接點開口時所發生之對 準誤差係小於關於所用之各製程之構成步驟之特性間之最小 間距。本發明所需之晶片面積因而可縮小。此外，因為自調 整，穿透接點不需如同導體般要變狹，因而可增加穿透接點 之抗電子遷移性並減少其電阻。 利用本發明，可能設計與製造晶片面積縮小且因為增加抗 電子遷移性與減少導體間之接點電阻所導致之電子特性改良 之積體電路。 」200308052 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to an integrated circuit, and more particularly to a penetrating contact for establishing a conductive connection between two conductors. [Previous Technology] Now, when manufacturing integrated circuits, the diameter of the intermetallic contact is smaller than the width of the metal track below and above it, which is used to conductively connect the two metal tracks. The overlap between the metal tracks in the contact area must be considered in the integrated circuit layout. Figure 32 shows part of the exemplary layout when designing an IC today. The four metal tracks 500, 502, 504, and 506 located in the upper structural plane or the conductor plane are shown in Fig. 32 by solid lines. In a related manner, the four metal tracks 5 0 8, 5 1 0, 5 1 2 and 5 1 4 located in the lower structural plane are represented by dashed lines; the lower structural plane is located below the upper structural plane and is spaced apart from each other. . It can be seen from FIG. 32 that the metal tracks 500-514 are arranged as shown in FIG. 32 in this way, so that the metal tracks 500_50 and 508-514 extend in parallel with each other in a certain structural plane, and have different structures. The metal trajectories of the surface 500-5 1 4 are arranged in pairs so that the metal trajectories of a certain structural surface extend upward to the joints 516, 518, 520, and 522, while the respective metal trajectories of the other structural surface are in the same direction. extend. It can be found that each metal track 5 0 0-5 1 4, that is, the metal track of the upper structural surface and the metal track of the lower structural surface, has a widened area 524 at the contact points 516, 518, 520, and 522. , 526, 528, 530 and 5 3 2, 5, 3 4, 5, 3 6 and 5 3 8; the reference for this phenomenon is that only the metal track 50 8-514 on the lower structure surface can be seen to increase the width 532- The short area of 538 is externally shaped, because the other parts of the shape are covered by the metal structure track 500-500 on the upper surface of the widened area 524-530. The widened areas 524-528 are electrically interconnected by dielectric metal contacts 540, 200308052 542, 544, and 546; the cross-sections of the dielectric metal contacts 540, 542, 544, and 5 46 are smaller than the widened area and are in the process It is manufactured in a construction step independent of the construction of the conductor surface. With the double arrows, Figure 3 2 additionally shows the minimum widths w 1, w 2 and the minimum spacings s 1, s 2. This layout must be considered when designing the circuit, and it is based on the manufacturing method, such as in subsequent manufacturing The CMOS method is determined by design rules. The minimum widths w1, w2 determine the minimum widths of the metal channels of the upper and lower structural surfaces, respectively, and the results obtained, for example, from practical restrictions in the lithography steps used to construct the respective structural surfaces. The minimum distances s1, s2 determine the minimum distance between the metal channels or the distance between the first feature and the second feature on the upper and lower structural surfaces / and, for example, from the lithography step used to construct the respective structural surfaces The results of practical restrictions. It can also be seen from FIG. 32 that the widths of the metal lanes 500-514 at each contact point 516-522 in the outward direction are increased by the X length on each side. It can also be seen that the enlarged area 524-538 is larger than the cross section of the intermetallic contacts 540-546. The obtained overlapping part must be added to the manufacturing tolerance calculation based on the alignment error between the structure of the holes in the metal contacts 540-546 and the structure of the metal structure of the upper and lower structure planes. Because the X length is increased in width, the possible minimum conductor spacings si and s2, respectively, cannot be used in the layout of metal domes with dielectric metal contacts. However, the minimum distance between two metal tracks of the same structural plane with the minimum width can be effectively given by sl + X. Therefore, the value of X is increased, that is, the length of the minimum conductor width must be increased, because the intermetallic connection is considered. The necessity of points overlaps. The addition of the minimum distance between the metal rails of the same structural plane results in a smaller 1C integration. However, the smaller chip area is needed in many 1C applications, because the chip area usually has to meet basic requirements, such as in the field of chip cards. Another disadvantage of the contact formation method described with reference to FIG. 32 is that, for the reasons described above, the diameter of the dielectric metal contact must always be smaller than that of the conductor, thus becoming a key point for electron migration. SUMMARY OF THE INVENTION Therefore, there is a need for a contact formation method, which has a higher integration degree and a higher resistance to electron migration. The object of the present invention is to provide a penetrating contact that forms a conductive connection between a first conductor and a second conductor, and a method for manufacturing the same, so that the penetrating contact can improve electronic characteristics and / or allow higher Degree of integration. This objective is achieved by the method according to item 1 of the scope of patent application and the penetration contact according to item 13 of the scope of patent application. The present invention is based on the fact that in order to allow the conductor to be formed within a conductor surface, the distance between the conductors is the smallest possible distance that can be achieved by process technology, and the conductor must be different from the traditional way to form the conductor at each penetration point . According to the present invention, a certain conductor or pattern and a penetrating contact are formed in the contact area in the same process step, that is, by forming a contact opening in the contact area, and then filling the contact. Open to the end of one of the grooves of the conductor. The effect is that the width of the conductor in the penetration contact is automatically adjusted to the size of the penetration contact. Because the step of forming the contact opening and the subsequent step of forming a broad conductor area adjusted to the size of the penetrating contact according to the self-adjusting method, and the step of forming the penetrating contact are implemented differently from the contact In the step of forming the conductor outside the zone, the increase in width will not cause any minimum spacing between the adjacent conductors on the conductor surface to be taken into account. -9-200308052, because the alignment error that occurs when the contact opening is formed Is less than the minimum distance between the characteristics of the constituent steps of each process used. The wafer area required by the present invention can therefore be reduced. In addition, because of self-adjustment, the penetration contact does not need to be narrowed like a conductor, so it can increase the resistance to electron migration of the penetration contact and reduce its resistance. With the present invention, it is possible to design and manufacture a integrated circuit having a reduced chip area and improved electronic characteristics due to increased resistance to electron migration and reduced contact resistance between conductors. "
根據特別實施例，介金屬接點製造於雙鑲嵌（D a m a s c e n e)技 術。 — 本發明之其他較佳實施例係定義於底下之詳細描述與申請 專利範圍内。 為讓本發明之上述和其他目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明 如下： -- 【實施方式】According to a particular embodiment, the intermetallic contacts are manufactured in a double damascene (D a m a s c e n e) technology. — Other preferred embodiments of the present invention are defined in the detailed description and patent application below. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows:-[Embodiment]
在開始描述本發明之前，相同元件或功能相同元件在圖中 標示為相同參考符號，在圖示之描述中避免了這些元件之重 覆描述。 圖1顯示根據本發明之介金屬接點之佈局。參考圖1之描 述，可清楚發現本發明能夠將佈局中之導體面或結構面之導 體間相距間距放置於考量具最小導體寬度之製程參數而得之 最小可能間距。 在圖1之佈局部份中，四個·導體或圖形（trace) 1 0，1 2，14， -10- 200308052 1 6由實線表示，該些導體排列於上結構面或導體面中。而， 虛線表示之四個導體1 8，2 0，2 2與2 4則排列於下結構面中。 相同於圖32之例，圖1之佈局中之導體10-24係排列成使得， 同一結構面之導體1 0 -1 6與1 8 - 2 4分別彼此平行排列，而成對定 位之導體1 0-24則排列成使得某一結構面之一導體在某一方 向上延伸至接點處2 6，2 8，3 0與3 2 ;從此接點處，另一結構 面之一相關導體則持續延伸於相同方向（在圖1中，是紙張之 長度方向）。在各接點處2 6 - 3 2處，穿透接點形成於接點區34， 3 6，3 8與4 0内：此穿透接點之大小相同於接點區，因而在底 下描述中，其用相同於相關接點區之相同參考符號來標示。 此事實之參考是，在接點區34-40内，下導體18-24之輪廓線先 被上導體10-1 6之實線所遮住，接著則被橫跨過該上導體10-16 之接點區3 4 - 4 0之虛線部份遮住。 要注意，在圖1之佈局中，無導體顯示其區有寬度加大，雖 然根據本發明，上結構面之各.導體10-1 6使得在該接點區3‘40 内，做為該接點區寬度與做為接點34-40寬度之寬度分別為自 調整方式，這將在底下詳細解釋。更準確地說，這意味著， 如果圖1代表導體-接點排列之上視面，上結構面之各導體 10-16之實線將沿著虛線34-4.0之接點處26-32延伸。此偏差代 表之理由將於底下詳細解釋。 利用雙箭頭，圖1另外顯示出最小導體寬度w 1與w 2 ;以及最 小間距s 1與s 2，其由在此佈局下之製程技術決定，且當計設此 佈局時必需考量到此。導體寬度w 1與w2決定上與下導體面之 導體之最小寬度，而最小間距s 1與s2決定導體面（亦即上或下 -11 - 200308052 導體面）之相鄰導體之最小間距或其他特徵。另一雙箭頭指出 接點3 4與相鄰上導體1 2間之間距s 3，接點3 4導電性内連接上 導體1 0與下導體1 8。已指出，如上述般，根據本發明，上導 體1 〇在接點處2 6之寬度可自調整成接點3 4之寬度，使得間距 S3也能代表上導體1 0與相鄰導體1 2間之間距。甚至，相鄰導 體3 4與3 6間之間距s 4也顯示於圖1中。 由圖1也可看出’即使提供介金屬接點3 4-40，最小可能間距 si與s2以及最小可能導體寬度wl與w2可用於導體1〇_24之排 列中；且即使偏離於圖1之佈局表示，兩相鄰上導體i 〇_丨6間 之間距（亦S3)在接點處26-32處係小於最小間距sl。如上述， 導體i 0-24如所示般分別具有最小導體寬度則與w2，也位於接 點區3 4 - 4 0内，雖然根據本發明，在接& #γ 1石 牡接點慝26-32處，上導體 10_ 16所具有之寬度可依自調整方式而自碉軟认斗r —· 、阳目為整於該接點，因為 在CAD佈局設計之例中，這可保證當檢查是否已遵守設計規 則時，此種檢查可由子程式實施之，當檢查是否遵守：‘體 面之特徵間之最小間距S 1時，不雲亜 ♦而要£分接點處26-32。也就 是，在上導體10-16用沿著虛線34 之 、評之輪廓線表示之其他例 中，當檢查是否遵守設計規則時，在 .了隹接點處26-32將會造成誤 差，因為接點區34-40與導體1〇-1 間之間距s且因而其小於最 小間距s 1。 儘管加大寬度可在接點處26·32自調整至介金屬接點34_4〇 之接點寬度’可依彷彿這些導體在其總長度之方向上具最〗 寬度wl般使得上導體1〇-16以相當狹窄之間距而放置，：事實 之理由在於，位於該接點區3“〇外之該導體ι〇_ι6之建構與該 -12- 200308052 接點區3 4 - 4 0内之該導體1 0 -1 6之接點之建構係實施於不 程步驟。依此，接點區34-40内之該導體10-16之區内之間 成未受到此製程之限制，比如以微影為條件之最小間距 si。接點區34與上導體12間之間距S3必需只大於製程容忍 定義之最小間距，比如在曝光過程中之上與下導體之對 差以及在曝光蝕刻過程中之介金屬接點3 4之寬度容忍度 而這些製程容忍度達小於比如以微影為條件之導體1 0-最小寬度w 1與w2以及最小間距s 1與s2。 - 為完整起見，此事實之參考在於，因為該些介金屬接 造於共同製程步驟中，相鄰介金屬接點間之間距也受到 守取決於所用之光罩技術且不同於s 1之製程相關最小間 影響。 如圖1之佈局之上述描述中，本發明能將在佈局中之導 考量以微影為條件之最小間距s 1與s2之最小可能間距來 放置，而這將導致面積需求之最小化或更上一層樓。對 片之固定面積由某些標準規定之特殊使用領域，這意味 省下面積來實施其他功能等。甚至，由圖1可看出，各介 接點寬度大於接點處26-40外之導體10-24之寬度，使得介 接點之電子遷移抵抗性本質上可獲得改善。對於積體電 言，本發明可導致晶片面積變小並改善電子特性。 參考圖2-29,根據本發明之產生介金屬接點之各實施例 述於底下。各圖顯示出在產生該介金屬接點之連續製程 剖面圖，在左側顯示於由各介金屬接點導電性連接或即 電性連接之上與下導體；在右側顯示出不進行内連接之 同製 距形 條件 度所 準誤 〇 缺 24之 點製 要遵 距s4 體以 相隔 於晶 著可 金屬 金屬 路而 將描 後之 將導 上與 -13- 200308052 割面A的話，該些剖 所示實施例代表製 甘欠（Damascene)技術 執道之最小寬度， 需小於或等於傳統 如參考圖3 2所做描 下金屬軌道。如果假設下導體20延伸於切 面圖相關於圖1之佈局中之切線A之剖面。 程步驟之順序，介金屬接點可產生於雙鑲 内，並介金屬接點之寬度大於上與下金屬 然而相對於此，介金屬接點之寬度永遠必 類型之介金屬接點内之上與下金屬轨道， 述般。 根據本發明之第一實施例之產生介金屬接點將參考圖2·8描 述。圖2顯示已形成下導體面之導體且應用光罩於構成上導= 與下導體面之製程步驟順序之情況。圖2顯示下導體面之下導 體18與下導體20已利用如鑲嵌技術形成於第_絕緣層5〇内， 下導體面由參考符號52表示且相鄰於該第—絕緣層5〇之主側 邊54。可發現，當構成下導體面52之下導體18，2〇時，已考 量設計規則所需之最小間距s2。第二絕緣層5 6已分別利用， 比如沉積法而應用至該第一絕緣層5 〇與該主側邊5 4。如·雙箭 頭所示，第二絕緣層具厚度tl。接著，構成上導體面之上導體 10與12之光罩58應用於該絕緣層56之主側邊59且比如由曝光 與接著製程之適當方式構成’以產生開口 6〇與62於將要形成 導體1 0與1 2之位置；以及將該第二絕緣層5 6曝光於這些位 置。比如為光阻之光罩5 8係調整成分別相關於下導體面與相 關於下導體18與20，或相關於用以構成該些導體之導體光罩。 圖3顯示當比如利用蝕刻步驟時’上導體面6 4之具深度d 1之 溝槽66，68已成於該第二絕緣層内之曝光位置60，62所發 生之情況。深度dl定義上導體面64之層厚度。接著，利用習 -14- 200308052 知技術來去除光罩58，比如樹脂剝離（lacquer stripping)，乾 蚀刻或濕姓刻。 圖4顯示當比如為光阻之用於形成介金屬接點34之光罩72 應用至第二絕緣層5 6之已成形上側邊5 9且已利用如曝光與顯 影來構成，以成開口 74於光罩72内，該開口 74定義該第二絕 緣層5 6之側邊5 9上之一曝光接點區。光罩7 2調整成相關於下 或上導體面且相對於下或上導體光罩52，64。 如圖5所示，接著將接點開口 76從光罩72内之開口 74往—下蝕 刻至下導體面52與下導體18，以及該主側邊54而深入於第二 絕緣層56。因而深度為d2 = tl-dl。在短過度蝕刻之例中，下導 體18之區將開口於該下導體重疊於形成該上導體之該溝槽 66(圖4)之區。上導體溝槽66與下導體18間之不對準將導致接 點區變小，如參考圖9之描述。在接點開口 7 6之邊緣部份7 8 處，開口深度減少了深度d 1，相比於形成該上導體之該溝槽 6 6之區。 當已蝕刻接點開口 76時，去除光罩72，如圖6所示，於是， 如圖7所示，上導體面64之導電材質78，比如由銅、鋁或其他 金屬形成之金屬材質，利用沉積法或其他適合的方法來應用 至該第二絕緣層56之側邊59。由圖7之左側可看出，所應用之 導電材質7 8填滿介金屬接點3 4之接點開口 7 6以及上導體1 0之 溝槽66(圖1)。在圖7之右側，可看到上導體12之溝槽68已填滿。 如圖8所示，以厚度t3高過該第二絕緣層5 6之側邊5 9之過度 材質在後續製程步驟利用如化學機械研磨法去除，而圖8之情 況將建立於，分別已完成介金屬接點34與上導體面64與上導 -15- 200308052 體10，12。另外由圖8可看出，去除該過度的導電材質78可使 得導體1 0，1 2彼此絕緣。Before the description of the present invention, the same elements or functionally identical elements are marked with the same reference signs in the drawings, and repeated description of these elements is avoided in the description of the illustrations. FIG. 1 shows the layout of the intermetallic contacts according to the present invention. Referring to the description of FIG. 1, it can be clearly found that the present invention can place the distance between conductors of a conductor surface or a structural surface in a layout in the smallest possible distance obtained by considering a process parameter having a minimum conductor width. In the layout part of FIG. 1, four conductors or traces (trace) 10, 12, 14, -10- 200308052 16 are indicated by solid lines, and these conductors are arranged on the upper structural surface or conductor surface. The four conductors 18, 20, 22, and 24 indicated by the dotted lines are arranged in the lower structural plane. Same as the example in FIG. 32, the conductors 10-24 in the layout of FIG. 1 are arranged so that the conductors 1 0 -1 6 and 1 8-2 4 on the same structural plane are arranged parallel to each other to form a pair of positioned conductors 1 0-24 is arranged so that one conductor of a certain structural surface extends to the contact point in a certain direction 2 6, 2 8, 3 0 and 3 2; from this contact point, the relevant conductor of another structural surface continues Extend in the same direction (in Figure 1, the length direction of the paper). At each contact point 2 6-3 2, penetrating contacts are formed in the contact areas 34, 3 6, 3 8 and 40: the size of this penetrating contact is the same as the contact area, so it is described below In the figure, they are marked with the same reference symbols as the corresponding contact areas. The reference of this fact is that within the contact area 34-40, the outline of the lower conductor 18-24 is first covered by the solid line of the upper conductor 10-1 6 and then is crossed by the upper conductor 10-16 The dotted area of the contact area 3 4-40 is hidden. It should be noted that in the layout of FIG. 1, the non-conductor shows that the area has an increased width, although according to the present invention, each of the upper structural surfaces. The conductor 10-1 6 makes the contact area 3'40 as the The width of the contact area and the width of the contact 34-40 are self-adjusting methods, which will be explained in detail below. More precisely, this means that if Figure 1 represents the top view of the conductor-contact arrangement, the solid lines of the conductors 10-16 on the upper structural surface will extend along the 26-32 points of the dotted line 34-4.0 . The reasons for this deviation will be explained in detail below. Using double arrows, Figure 1 additionally shows the minimum conductor widths w 1 and w 2; and the minimum pitches s 1 and s 2, which are determined by the process technology under this layout, and must be considered when planning this layout. The conductor widths w 1 and w 2 determine the minimum width of the conductor on the upper and lower conductor surfaces, and the minimum distance s 1 and s 2 determine the minimum distance between adjacent conductors on the conductor surface (that is, the upper or lower -11-200308052 conductor surface) or other feature. The other double arrow indicates the distance s 3 between the contact point 3 4 and the adjacent upper conductor 12, and the contact point 3 4 conductively connects the upper conductor 10 and the lower conductor 18. It has been pointed out that, as mentioned above, according to the present invention, the width of the upper conductor 10 at the contact 26 can be adjusted to the width of the contact 34, so that the distance S3 can also represent the upper conductor 10 and the adjacent conductor 12 Space between. Furthermore, the distance s 4 between adjacent conductors 34 and 36 is also shown in FIG. It can also be seen from FIG. 1 'Even if intermetallic contacts 3 4-40 are provided, the smallest possible spacing si and s2 and the smallest possible conductor widths wl and w2 can be used in the arrangement of the conductors 10-24; and even if it deviates from FIG. 1 The layout indicates that the distance (also S3) between two adjacent upper conductors i0_ 丨 6 is less than the minimum distance sl at the contact points 26-32. As mentioned above, the conductors i 0-24 have the smallest conductor width and w2 respectively as shown, and are also located in the contact area 3 4-4 0. Although according to the present invention, the contact & At 26-32, the width of the upper conductor 10_16 can be self-adjusted according to the self-adjusting method. — —, The sun is rounded to the contact, because in the example of CAD layout design, this can ensure that When checking whether the design rules have been complied with, such checks can be carried out by subroutines. When checking for compliance with: 'Minimum distance S 1 between decent features, it is not necessary to go to the tap point 26-32. That is, in other examples where the upper conductors 10-16 are indicated by the outlines along the dotted line 34, when checking whether the design rules are observed, 26-32 will cause errors at the contact points, because The distance s between the contact area 34-40 and the conductor 10-1 is therefore smaller than the minimum distance s1. Although the increased width can be adjusted from 26 to 32 at the contact point to the contact width of the intermetallic contact point 34_4 ′, it can be as if these conductors have the maximum width w1 in the direction of their total length, making the upper conductor 1-10. 16 is placed at a relatively narrow distance: the reason for the fact is that the construction of the conductor ι〇_ι6 located outside the contact area 3 ″ 〇 and the -12-200308052 contact area 3 4-4 0 The construction of the contacts of the conductors 10 to 16 is implemented in a non-procedure step. According to this, the formation of the conductors within the contact area 34-40 within the conductor 10-16 is not restricted by this process, such as micro- The minimum distance si of the shadow is the condition. The distance S3 between the contact area 34 and the upper conductor 12 must only be greater than the minimum distance defined by the process tolerance, such as the difference between the upper and lower conductors during exposure and the exposure during etching. The tolerance of the width of the intermetallic contacts 34 is smaller than the tolerance of these processes, such as the conductor 1 0-minimum width w 1 and w 2 and the minimum distance s 1 and s 2 on the condition of lithography.-For the sake of completeness, this fact The reference is that because these intermetals are connected in a common process step, adjacent The distance between the dependent contacts is also affected by the smallest correlation that depends on the mask technology used and is different from the process of s 1. As shown in the above description of the layout of FIG. 1, the present invention can minimize the guiding considerations in the layout. The minimum possible distance between s1 and s2 is placed under the condition of the shadow, and this will result in the minimum area requirement or a higher level. The fixed area of the film is a special field of use specified by some standards, which means that the province Lower area to implement other functions, etc. It can be seen from Fig. 1 that the width of each contact point is larger than the width of the conductor 10-24 outside the contact point 26-40, which makes the resistance of electron migration of the contact point essentially Improved. For integrated electronics, the present invention can lead to a smaller chip area and improved electronic characteristics. With reference to Figures 2-29, the embodiments of the present invention that produce intermetallic contacts are described below. The figures show A cross-sectional view of the continuous process for producing the intermetallic contact is shown on the left side above and below the conductive connection or the electrical connection by the intermetallic contact; on the right side, the same distance shape condition without internal connection is shown. The standard system of the missing point is to follow the distance from the s4 body to the metal surface of the crystallized metal, and then guide the trace to the -13- 200308052 cut plane A. The representative examples of these sections are The minimum width of the Damascene technique should be less than or equal to the traditional description of the metal track as described with reference to Figure 32. If it is assumed that the lower conductor 20 extends in a cross-section, the section related to the tangent line A in the layout of Figure 1 In the order of the process steps, the intermetallic contacts can be generated in the double setting, and the width of the intermetallic contacts is larger than the upper and lower metal. However, the width of the intermetallic contacts is always the same type of intermetallic contacts. The upper and lower metal tracks are as described above. The generation of the intermetallic contact according to the first embodiment of the present invention will be described with reference to Figs. FIG. 2 shows a case where a conductor having a lower conductor surface has been formed and a photomask is applied to form a sequence of process steps of the upper conductor = and the lower conductor surface. FIG. 2 shows that the lower conductor 18 and the lower conductor 20 have been formed in the first insulating layer 50 using a damascene technique. The lower conductor surface is indicated by the reference symbol 52 and is adjacent to the main of the first insulating layer 50. Side 54. It can be found that when forming the conductors 18, 20 below the lower conductor surface 52, the minimum distance s2 required by the design rules has been considered. The second insulating layer 56 has been applied to the first insulating layer 50 and the main side 54 by, for example, a deposition method. As shown by the double arrows, the second insulating layer has a thickness t1. Next, a mask 58 constituting the conductors 10 and 12 above the upper conductor surface is applied to the main side 59 of the insulating layer 56 and is constituted, for example, by an appropriate method of exposure and bonding process to create openings 60 and 62 to form the conductor 10 and 12 positions; and exposing the second insulating layer 56 to these positions. For example, the photomasks 58 and 8 for the photoresist are adjusted to be related to the lower conductor surface and the lower conductors 18 and 20, respectively, or to the conductor masks used to form the conductors. Fig. 3 shows what happens when the trenches 66, 68 with a depth d of the upper conductor surface 64 have been formed at the exposure positions 60, 62 in the second insulating layer when, for example, an etching step is used. The depth dl defines the layer thickness of the upper conductor surface 64. Next, the mask 58 is removed using known techniques such as lacquer stripping, dry etching or wet engraving. FIG. 4 shows that when, for example, a photoresist 72 for forming a metal contact 34 is applied to the formed upper side 59 of the second insulating layer 5 6 and has been formed using, for example, exposure and development, to form an opening 74 is inside the photomask 72. The opening 74 defines an exposed contact area on one of the sides 59 of the second insulating layer 56. The reticle 72 is adjusted in relation to the lower or upper conductor surface and relative to the lower or upper conductor reticle 52, 64. As shown in FIG. 5, the contact opening 76 is then etched down from the opening 74 in the mask 72 to the lower conductor surface 52 and the lower conductor 18, and the main side edge 54 penetrates into the second insulating layer 56. Thus the depth is d2 = tl-dl. In the example of short over-etching, the area of the lower conductor 18 will open in the area where the lower conductor overlaps the trench 66 (FIG. 4) forming the upper conductor. Misalignment between the upper conductor trench 66 and the lower conductor 18 will result in a smaller contact area, as described with reference to FIG. At the edge portion 7 8 of the contact opening 7 6, the depth of the opening is reduced by the depth d 1, compared to the area of the trench 66 that forms the upper conductor. When the contact opening 76 has been etched, the photomask 72 is removed, as shown in FIG. 6. Therefore, as shown in FIG. 7, the conductive material 78 of the upper conductor surface 64 is, for example, a metal material formed of copper, aluminum, or other metals. The deposition method or other suitable method is used to apply the side 59 of the second insulating layer 56. It can be seen from the left side of FIG. 7 that the applied conductive material 7 8 fills the contact openings 76 of the dielectric metal contacts 34 and the trench 66 of the upper conductor 10 (FIG. 1). On the right side of FIG. 7, it can be seen that the trench 68 of the upper conductor 12 is filled. As shown in FIG. 8, the excessive material with a thickness t3 higher than the side 5 9 of the second insulating layer 5 6 is removed in a subsequent process step using, for example, a chemical mechanical polishing method, and the situation in FIG. 8 will be established based on the completion Intermediate metal contact 34 and upper conductor surface 64 and upper conductor -15-200308052 body 10,12. In addition, it can be seen from FIG. 8 that removing the excessive conductive material 78 can insulate the conductors 10, 12 from each other.
為更清楚，圖8中之接點開口 7 6之虛線8 0顯示出，填於接點 開口 76内之部份金屬材質78屬於導體10，而部份金屬材質屬 於介金屬接點34。因而虛線80構成位於該接點區内且由圖4之 光罩所定義之該導體1 〇之此部份與該介金屬接點3 4間之界線 或接點表面。可看出，導體10之寬度以自調整方式來適應於 接點區内之該介金屬接點3 4，因為接點區内之該導體1 0_與該 介金屬接點34定義於共同的蝕刻步驟（圖5)。 如上述，在產生該介金屬接點時進行了兩個調整動作，亦 即調整有關於該下導體面之該上導體面之該光罩58以及調整 有關於下或上導體面之該接點開口 76之該光罩72。然而，此 兩個調整動作皆受到對準誤差之影響，這些誤差相對於最小 間距s 1與d2是很小所以能避免短路。然而，發生於構成上導 體1 0時發生之對準誤差將導致問題於形成介金屬接點3 4-之接 點開7 6時；在底下，參考圖9與1 0來解釋這些問題。For the sake of clarity, the dotted line 80 of the contact opening 76 in FIG. 8 shows that part of the metal material 78 filled in the contact opening 76 belongs to the conductor 10, and part of the metal material belongs to the intermetallic contact 34. The dashed line 80 thus forms the boundary or contact surface between the portion of the conductor 10 and the intermetallic contact 34, which is located in the contact area and is defined by the mask of FIG. It can be seen that the width of the conductor 10 is adapted to the intermetallic contact 34 in the contact area in a self-adjusting manner, because the conductor 10_ and the intermetallic contact 34 in the contact area are defined in a common Etching step (Figure 5). As described above, two adjustment actions were performed when the intermetallic contact was generated, that is, the photomask 58 related to the lower conductive surface and the upper conductive surface and the contact related to the lower or upper conductive surface were adjusted. The photomask 72 of the opening 76. However, both of these adjustments are affected by alignment errors, which are small relative to the minimum pitches s 1 and d2 so short circuits can be avoided. However, alignment errors that occur while forming the upper conductor 10 will cause problems when the contacts forming the intermetallic contacts 3 4-7 are opened; below, these problems will be explained with reference to FIGS. 9 and 10.
圖9顯示圖2 - 8之介金屬接點在相關於圖5情況下之情況。不 同於圖5之情況，圖9所示之發生於構形上導體1 0之對準誤差 具長度△ s。如同圖5之例，蝕刻時間與蝕刻率調整成使得用 開口該下導體1 8之短過蝕刻時間内，蝕刻深度為d2。可發現， 該下導體1 8未完全開口於該接點區内，而只開口於其重疊於 該結構之區内，亦即上導體1 0之溝槽6 6，因為該接點開口 7 6 之開口深度只在此往下延伸至該下導體1 8。因為光罩5 8之誤 對準，該接點區，亦即該接點開口 7 6或該介金屬接點間之邊 -16- 200308052 界區該該下導體1 8，係變小，可從比如8 2處看出。這意味著， 接點電阻值將取決於對調該上導體面64之該光罩5 8時產生之 誤對準（圖2)而增加，且這將導致意外的不平坦以及積體電路 内之接點電阻值之變化。 如圖1 0所示，增加蝕刻時間以及蝕刻深度也無法解決圖9所 示之問題。圖1 0顯示相關於圖5之介金屬接點3 4之條件，相同 於圖9之例，大小為As之對準誤差發生於上導體面調整時。 不同於圖5與圖9，蝕刻時間與蝕刻率係調整成使得蝕刻~深度 為11。因為較多的蝕刻時間，整個下導體1 8露出於介金屬接點 之區内，但如從圖1 0之8 4處着出，同時執行絕緣層5 0之增強 蝕刻於位於下導體1 8側邊之區内且設計有上導體1 0之溝槽6 6 之區内，因而底導體18未構造於該處。由84處可看出，溝槽 因而形成於下導體1 8之側邊。由在下導體1 8之侧邊處之蝕刻 部份與接點開口邊緣區内之不同蝕刻深度所導致此拓樸將導 致額外問題，就金屬沉積時之阻障緊密與填滿特徵而言j 請參考圖1 1 -1 8，將描述一實施例，其解決因為構成上導體 面時之誤對準所形成之圖2 -1 0之實施例中之問題，其解決之 道在於提供蝕刻終止層於下導體面之上。 下列實施例解決有關於上導體面之構成或曝光時之誤對準 之接點區變小問題，或當增加蝕刻時間時在介金屬接點之底 部發生之拓撲問題，其解決之道為提供一額外絕緣層1 0 0於第 一絕緣層5 0與第二絕緣層5 6之間。因此，圖1 1，其代表在關 於圖2之情況之製造時之介金屬接點，其顯示具第一導體面52 之絕緣層5 0，特別是，下導體1 8與2 0，加於該絕緣層5 0頂端 -17- 200308052 絕相， 二係60 第58口 該罩開 之光之 端該面 頂，體 ο 8 』Γ ο 5 導 罩下 光該 之於 面對 體相 導義 上定 該且 成整 G構調 10以而 層用面 緣及體 絕以導 外，下 額56該 該層於 之緣對 層 緣 絕 外 額 該 於 位 與 程與 製10 個體 兩導 行上 執該 著生 接產 ， 以 例刻 施蝕^ 實槽， : 8 一 溝 6 第之與 4 6 該 6 6 之面槽 述體溝 描導之 11 而上 d 行度 執深 圖中具 考其k 參 ， 如驟 步 圖 罩 光 除 去 示 所 2 11 圖 金 介 該 與 δ 罩 光 新。 之出 Π 看 開可 點13 接圖 的由 來， 4 未 7 D 接之 區 點 接 於 位 成有 ^ 具 以罩 用光 用該 應 ， L 2 且 7 不同於該第一實施例，介金屬接點之接點開口 76之部份係 接著利用由圖14可看出之可選擇性終止於該額外絕緣層100 之蝕刻製程來蝕刻至至該第二絕緣層5 6内。這允許，不同於 第一實施例，可在該接點開ό 76之邊界區102，亦即，在沒有 溝槽66之區内，完全移除該第二絕緣層56，如此可獲得該接 點開口與該額外絕緣層1 〇〇之平坦底部。額外絕緣層1 〇〇__當成 姓刻終止層。 由圖15可看出，光罩72在形成往下接觸到蝕刻終止層100之 接點開口 76後，可移除光罩72。由圖16可看出，在移除光罩 72可進行一蝕刻製程，利用此蝕刻製程，能打開露出於接點 開口 76之蝕刻終止層100之部份，且下導體18完全露出於介金 屬接點開口 7 6之區内。此蝕刻製程可相對於該第一絕緣層5 0 與該第二絕緣層5 6而選擇，如本例般。現在完全接點開口 7 6 之形成。 由圖15可看出，下導體18之有效接點區永遠相同，只要接 -18- 200308052 點開口 7 6之寬度相對於該下導體1 8之寬度延伸之長度χ只夠 補償在調整光罩72時發生的誤對準。 根據第一實施例之步驟7與8，介金屬接點3 4與上導體面64 以及該第一與第二導體10與12可如由圖17般利用導電材質78 與接著去除剩餘之導電材質78而形成。Fig. 9 shows the situation of the intermetallic contacts of Figs. 2-8 in the case of Fig. 5. Unlike the case of FIG. 5, the alignment error of the conductor 10 on the configuration shown in FIG. 9 has a length Δs. As in the example of Fig. 5, the etching time and the etching rate are adjusted so that the etching time of the lower conductor 18 is shorter than the etching time, and the etching depth is d2. It can be found that the lower conductor 18 is not completely open in the contact area, but only in the area where it overlaps the structure, that is, the groove 6 6 of the upper conductor 10, because the contact opening 7 6 The opening depth only extends down to the lower conductor 18 here. Because of the misalignment of the photomask 5 8, the contact area, that is, the contact opening 76 or the edge between the intermetallic contacts -16-200308052 boundary area, the lower conductor 1 8 is smaller, but Seen from, for example, 8 2. This means that the contact resistance value will increase depending on the misalignment (Fig. 2) generated when the mask 58 of the upper conductor surface 64 is reversed, and this will cause unexpected unevenness and in-circuit of the integrated circuit. Changes in contact resistance. As shown in FIG. 10, increasing the etching time and etching depth cannot solve the problem shown in FIG. Fig. 10 shows the conditions related to the intermetallic contact 34 of Fig. 5, which is the same as the example of Fig. 9. The alignment error of As occurs when the upper conductor plane is adjusted. Unlike FIG. 5 and FIG. 9, the etching time and the etching rate are adjusted so that the etching ~ depth is 11. Because of the longer etching time, the entire lower conductor 18 is exposed in the area of the intermetallic contact. However, if it exits from Fig. 10-8, the enhanced etching of the insulating layer 50 is performed on the lower conductor 18 at the same time. The area in the side and the area in which the grooves 6 6 of the upper conductor 10 are designed, so the bottom conductor 18 is not constructed there. It can be seen from 84 that the groove is thus formed on the side of the lower conductor 18. This topology will result in additional problems caused by the different etch depths in the etched portion at the side of the lower conductor 18 and the edge area of the contact opening. In terms of tight barriers and filling characteristics during metal deposition, please Referring to FIGS. 1 to 18, an embodiment will be described that solves the problem in the embodiment of FIGS. 2 to 10 formed due to misalignment when forming the upper conductor surface. The solution is to provide an etch stop layer Above the lower conductor plane. The following embodiment solves the problem of the contact area that is related to the composition of the upper conductor surface or misalignment during exposure, or the topological problem that occurs at the bottom of the intermetallic contact when the etching time is increased. The solution is to provide An additional insulating layer 100 is between the first insulating layer 50 and the second insulating layer 56. Therefore, FIG. 11, which represents the intermetallic contact at the time of manufacture in the case of FIG. 2, shows the insulating layer 50 with the first conductor surface 52, in particular, the lower conductors 18 and 20 are added to The top of the insulating layer 5 0-17- 200308052 is out of phase, the second series 60 mouth 58 the end of the light that the cover opens, the surface top, the body ο 8 』Γ ο 5 The light under the guide cover should be applied to the body phase. The upper and lower G structure is adjusted to 10, and the layer surface and body must be out of the guide. The amount of 56 is the edge of the layer to the edge of the layer. The in-place and process and system 10 are the two guides. Dedicated to the birth and delivery, for example, to etch the solid groove,: 8 a ditch 6th and 4 6 the 6 6 of the surface groove description of the body groove description 11 Considering its k reference, as shown in the step diagram, the masking light is removed, and the 2 11 figure Jinjie and the delta masking light are new. The origin of Π can be seen 13 points of the origin of the picture, 4 and 7 D are connected to the point of the place ^ with the cover to use the light, L 2 and 7 are different from the first embodiment, the metal A portion of the contact opening 76 of the contact is then etched into the second insulating layer 56 using an etching process that can be selectively terminated in the additional insulating layer 100 as can be seen in FIG. 14. This allows, unlike the first embodiment, the second insulating layer 56 to be completely removed in the boundary region 102 of the contact opening 76, that is, in the region without the trench 66, so that the contact can be obtained. Dot the opening and the flat bottom of the additional insulating layer 1000. The extra insulating layer 1 〇〇__ is used as the last cut layer. It can be seen from FIG. 15 that the photomask 72 can be removed after forming the contact opening 76 which contacts the etching stopper layer 100 downward. It can be seen from FIG. 16 that an etching process can be performed after removing the photomask 72. With this etching process, a part of the etch stop layer 100 exposed at the contact opening 76 can be opened, and the lower conductor 18 is completely exposed at the dielectric metal. Within the contact opening 76. This etching process may be selected relative to the first insulating layer 50 and the second insulating layer 56, as in this example. The full contact opening 7 6 is now formed. It can be seen from FIG. 15 that the effective contact area of the lower conductor 18 is always the same. As long as the width of the point opening 7 6 connected to the -18-200308052 point opening 6 is relative to the width of the lower conductor 18, the length χ can only compensate for the adjustment of the mask Misalignment occurred at 720 hours. According to steps 7 and 8 of the first embodiment, the intermetallic contacts 34 and the upper conductor surface 64 and the first and second conductors 10 and 12 can use the conductive material 78 as shown in FIG. 17 and then remove the remaining conductive material 78 was formed.
除了解決在上導體面構成時之誤對準相關之接點面積變小 問題以及當增加蝕刻時間時在介金屬接點底部發生的拓撲問 題外，在第一實施例之問題中，利用提供該額外蝕刻終1層 1 0 0，第二實施例所提供之優點更在於可去除亦即剝落用以形 成接點開口之光罩72(圖14)，而下導體面52之導體18仍未露出 (圖14與15)。這是有利的，因為光罩72，比如為光阻，一般由 會將露出之金屬層強烈氧化之氧氣電漿去除。然而，圖1 6之 蝕刻終止層100之去除也可在去除光罩72之前進行（圖15)，然 · 而，因為上述理由，上述製程步驟之順序是較好的。 在上述實施例中，上導體面與上導體之厚度由深入於絕緣 層56之蝕刻深度dl定義（分別·參考圖3與12)。因而厚度dl未直 接有關於蝕刻深度之重複性，因而不受意外變化之影響。在 _ 底下，將參考圖19-29來根據本發明之製造介金屬接點之實施 · 例；在此實施例中，第二絕緣層5 6由底下定義之：在兩絕緣 層2 00，2 02之間排列一當成蝕刻終止層之中介層204 ;以及該 上導體面與該上導體之厚度可分別相對於該絕緣層202超過 該中介層204之厚度而調整，無關於任何蝕刻速率或蝕刻時 圖1 9顯示在製造介金屬接點時之情況，其相關於圖2〜1 1之 •19- 200308052 情況。特別是，圖1 9顯示出内部形成第一導體面與導體 2 0之第一絕緣層5 0 ;位於該第一絕緣層5 0之上側邊5 4上 刻終止層1 0 0 ;取代前兩個實施例之該第二絕緣層5 6且位 刻終止層1 0 0上之絕緣層2 0 0、2 0 2，該絕緣層2 0 0、2 0 2具 其間之該中介層204 ;以及用以構成該上導體面並應用至 緣層202之該光罩58。如上述，該光罩58對準於該下導 52，且具有用以成兩上導體溝槽之兩蝕刻開口 60，62。 19中，絕緣層202，中介層204，絕緣層200與蝕刻終止；ΐ 之厚度分別為d2，d4，d3與d5。 當應用該上導體之該光罩58時，如圖19所示，厚度為 該絕緣層2 0 2使選擇性蝕刻製程所蝕刻，如圖2 0所示，以 上導體面64，特別是上導體10與上導體12之該溝槽66, 份。該蝕刻選擇性終止於中介層204上，因而其當成蝕刻 層。 接著，如圖21所示，移除該光罩58，且如圖22所示， 屬接點之該光罩72係應用至該絕緣層202，該光罩72在該 區具一開口 74，以做為接點開口之後續形成。藉由相對 中介層204之另一選擇性蝕刻製程，在該光罩72所定義之 點區74内之該絕緣層202係被.移除，如圖23所示。在該接 74内之其他選擇性蝕刻製程用以去除該中介層204，如圖 示；及用以去除該絕緣層2 0 0，如圖2 5所示。根據圖2 3 -蝕刻製程選擇性終止於在待蝕刻之該層下方之各層，亦 終止於中介層20 4，絕緣層2 0.0與蝕刻終止層1 0 0上。在這 刻製程後，已完成接點開口 7 6之形成，除了尚未去除該 18與 之蝕 於姓 位於 該絕 體面 在圖 r 100 d2之 成該 68部 終止 介金 接點 於該 該接 點區 24所 25之 即其 些# #刻 -20- 200308052 終止層1 〇 〇外。 之後，去^ ^ ”尤卓72，如圖26所示，且在另一蝕刻製程中， 打開蝕刻終止； 〇〇,且該下導體18係露出於該介金屬接點之 區内，因而完忠In addition to solving the problem of smaller contact area related to misalignment in the formation of the upper conductor surface and the topology problem that occurs at the bottom of the intermetallic contact when the etching time is increased, in the problem of the first embodiment, the One additional layer of 100 is etched. The advantage provided by the second embodiment is that the photomask 72 (FIG. 14) used to form the contact opening can be removed, and the conductor 18 of the lower conductor surface 52 is not exposed. (Figures 14 and 15). This is advantageous because the photomask 72, such as a photoresist, is generally removed by an oxygen plasma that strongly oxidizes the exposed metal layer. However, the removal of the etch stop layer 100 of FIG. 16 can also be performed before the photomask 72 is removed (FIG. 15). However, for the reasons described above, the order of the above process steps is better. In the above embodiment, the thickness of the upper conductor surface and the upper conductor is defined by the etching depth d1 which penetrates into the insulating layer 56 (refer to Figs. 3 and 12 respectively). Therefore, the thickness dl is not directly related to the repeatability of the etching depth, and thus is not affected by accidental changes. Under _, an example of manufacturing an intermetallic contact according to the present invention will be described with reference to FIGS. 19-29; in this embodiment, the second insulating layer 56 is defined by the following: the two insulating layers 2 00, 2 An interposer 204 as an etch stop layer is arranged between 02; and the thickness of the upper conductor surface and the upper conductor can be adjusted relative to the thickness of the insulating layer 202 exceeding the thickness of the interposer 204, regardless of any etching rate or etching Figure 19 shows the situation when the intermetallic contact is manufactured, which is related to the situation of • 19-200308052 in Figure 2 ~ 11. In particular, FIG. 19 shows a first insulating layer 50 forming a first conductor surface and a conductor 20 inside; a stop layer 1 0 0 is engraved on the side 5 4 above the first insulating layer 50; before replacing The two embodiments of the second insulating layer 56 and the etch stop layer 100 on the insulating layer 2 0 0, 2 0 2, the insulating layer 2 0, 2 0 2 with the interposer 204 therebetween; And the photomask 58 for forming the upper conductor surface and applying it to the edge layer 202. As described above, the mask 58 is aligned with the lower guide 52 and has two etched openings 60, 62 for forming two upper conductor trenches. In 19, the insulating layer 202, the interposer 204, the insulating layer 200, and the etching stop; the thicknesses of ΐ are d2, d4, d3, and d5, respectively. When the photomask 58 of the upper conductor is applied, as shown in FIG. 19, the thickness of the insulating layer 202 is etched by a selective etching process, as shown in FIG. 20, the upper conductor surface 64, especially the upper conductor 10 and 66 of the groove of the upper conductor 12. The etch selectively ends on the interposer 204, so it acts as an etch layer. Next, as shown in FIG. 21, the photomask 58 is removed, and as shown in FIG. 22, the photomask 72 belonging to the contact is applied to the insulating layer 202, and the photomask 72 has an opening 74 in the area. The subsequent formation as a contact opening. By another selective etching process with respect to the interposer 204, the insulating layer 202 in the point region 74 defined by the photomask 72 is removed, as shown in FIG. Other selective etching processes in the junction 74 are used to remove the interposer 204, as shown in the figure; and are used to remove the insulating layer 200, as shown in FIG. According to Figure 2 3-the etching process is selectively terminated on the layers below the layer to be etched, and also terminated on the interposer 20 4, the insulating layer 2 0.0 and the etch stop layer 100. After the manufacturing process at this moment, the formation of the contact opening 76 has been completed, except that the 18 and the eclipse that is located on the sacred surface are completed at the figure r 100 d2. The 68 termination termination contacts are at the contact. Area 24, 25, which is some ## 刻 -20- 200308052 The termination layer is 1000 outside. After that, go to ^ ^ "Yu Zhuo 72", as shown in FIG. 26, and in another etching process, turn on the etching termination; 〇〇, and the lower conductor 18 is exposed in the area of the intermetallic contact, and thus completed Loyal
战该接點開口 7 6之形成，如圖2 7所示。在該蝕 刻步驟中，中A 1增2 0 4額外蝕刻於該上導體面内之該形成區 内’特別在該上道 工等體10與12之區内，因而溝槽68之深度可增 加至d2十d4。此益μ也丨 域刻製程可相對於該絕緣層2 〇 〇與該絕緣層5 0 而選擇。如該第_ a _ 木一貫施例般，也可能在當已打開該蝕刻-終止 層100時來去除 Μ九罩7 2，但在此例中，可在該金屬表面打開 言玄;匕 ^ ’因而受到已打開之此金屬表面所導致之氧化 問題之影響。在 上迷例中，而，在蝕刻該蝕刻終止層1 0 〇時， 可避免在該上導㈣ 骚面之構成區内同時蝕刻該中介層204。 如上述貫施例如 〇a ' 版 開口 ，亦即接點開口 76與上導體之溝槽 66與68，接著用道 導電材質78填滿，如圖28所示，接著將去除 過量使用之導雷 質78。可發現，上導體面之厚度相等於此 兩層202與204之展择 m 子度’因而不受蝕刻率或蝕刻時間之影響。 因31 *、、員示根據本發明之又一實施例之沿著圖1之介金 屬接點34之平面A與平面B之剖面圖。圖3〇與31所示之介金屬 接點有關於根據19-29之製程步驟所產生之接點，然而阻障層 300直接位於該下導體面之該導體18、2〇底下，以及直接位於 該上導體面之該導體10、12底下，且在該些層5〇、1〇〇、 20 0-204之底下。當此結構變小時，此阻障層有助於解決可靠 性問題，就該導體之製造而言。該上導體丨〇、丨2下方與該介 金屬接點34下方之該阻障層3〇〇可應用於填滿圖以之該接點 -21 - 200308052 開口步驟之前。 上述之絕緣層56，200，202與50可包括二氧化矽或低 質，亦即介電常數低於二氧化矽之絕緣材質。上述絕緣眉 與204可包括氮矽化合物，碳矽化合物，或SiCOH。導體面 64與導體10，12與18, 20與當成填充材質之導電材質可為 阻障層3 0 0比如可為包括鈕與.氮化鈕之多層。然而，在此 之材質並非全部的例子。 參考上述描述，雖然其指出，蝕刻步驟已表示於圖中^ 為非等向性，也可能使用等向性蝕刻製程或至少使得介 接點之受蝕刻邊緣不會垂直延伸之蝕刻製程。這導致分 該上與下導體之邊界表面處之介金屬接點開口有不同大 原則上可相買於該上或下導體面而實行之該接點開口之 在此例中較坪是相對於介金屬接點較大之導體面而進行 為介金屬接點與各導體間之間距會較小。 甚至，雖然全部蝕刻製程已用於形成該接點開口，原則 也可能使用其他方法，比如鑽孔法（drill)等。甚至，本發 受限於該些層之材質，其在此僅是舉例用。特別是，各 需要使用相同材質，比如該兩導體面。 此外，指出要導電性連接至該下導體之該上導體之該 之填充可在形成該接點開口之前進行，在此例中之該上 之金屬係利用額外蝕刻步驟而在形成該接點開口之前從 點區内去除，接著由要填滿該接點開口之該導電材質取 甚至，可能只填滿該接點開口 ，接著在另一步驟中填滿 點區外之該溝槽。 K材 ，1〇〇 52， 銅。 所列 使其 金屬 別在 調整 ,因 上， 明未 層不 溝槽 導體 該接 代。 該接 -22- 200308052 【圖式簡單說明】 圖1顯示根據本發明之介金屬接點之佈局； 圖2〜圖8顯示根據本發明之一第一實施例之兩對之上與下 導體之剖面圖，一對導體由介金屬接點所連接，且亦顯示出 在製程中之下一製造步驟之條件； 圖9顯示相關於圖5之剖面圖之一剖面圖，上導體之結構中 之對準錯誤之效應清楚顯示出； 圖1 0顯示相關於圖5之剖面圖之一剖面圖，在較大蝕刻Ί罙度 之例中，上導體之結構中之對準錯誤之效應清楚顯示出； 圖1 1〜1 8顯示顯示根據本發明之一第二實施例之兩對之上 與下導體之剖面圖，一對導體由介金屬接點所連接，且亦顯 示出在製程中之下一製造步驟之條件； 圖1 9〜2 9顯示顯示根據本發明之一第三實施例之兩對之上 與下導體之剖面圖，一對導體由介金屬接點所連接，且亦顯 示出在製程中之下一製造步驟之條件； 圖3 0顯示顯示根據本發明之一第四實施例之介金屬接點排 列之剖面圖； 圖31顯示圖30之該介金屬接點之剖面圖，該區對圖30之區 呈直角而延伸；以及 圖32顯示使用傳統介金屬接點之1C之佈局。 圖式代表符號說明 10，12，14，16，18，20，22，24，500，502，504，5 06， 508 ， 510， 512， 514：導體 26， 28， 30， 32， 516， 518， 520， 522 ：接點處 -23- 200308052 34，36，38，40:接點區/介金屬接點 50， 56， 200， 202 ：絕緣層 52 :下導體面 5 4，5 9 :上主側邊 5 8，7 2 ·•光罩 60 ， 62 ：開口 64 :上導體面 6 6，6 8 :溝槽 74 :接點區 7 6 :接點開口 7 8 :邊緣 80 :邊界/接點表面 8 2 :位移 _ 84 :溝槽拓撲 1 0 0 :蝕刻終止層 1 0 2 :邊界區 2 0 4 :中介層 3 0 0 :阻障層 524 ， 526 ， 528 ， 530 ， 532 ， 534 ， 536 ， 538 寬度加大區 540，542，544，546 ：介金屬接點。 -24-The formation of the contact opening 76 is shown in Fig. 27. In this etching step, the medium A 1 is increased by 2 0 4 and is additionally etched in the formation area within the upper conductor surface, particularly in the area of the upper working body 10 and 12, so that the depth of the groove 68 can be increased. To d2 ten d4. This benefit μ can also be selected with respect to the insulating layer 2000 and the insulating layer 50. As in the first embodiment, it is also possible to remove the M 9 cover 7 2 when the etch-stop layer 100 has been opened, but in this example, the word surface can be opened on the metal surface; 'So affected by the oxidation problem caused by the metal surface that has been opened. In the above example, when the etching stop layer 100 is etched, it is possible to avoid etching the interposer 204 at the same time in the constituent region of the upper conductive surface. As described above, for example, a 0a ′ version of the opening, that is, the contact opening 76 and the grooves 66 and 68 of the upper conductor, are then filled with a conductive material 78, as shown in FIG. 28, and then the excessively used lightning guide is removed. Quality 78. It can be found that the thickness of the upper conductor surface is equal to the spread m 'of the two layers 202 and 204 and is not affected by the etching rate or etching time. Because 31 *, it shows a cross-sectional view along plane A and plane B of the metal contact 34 in FIG. 1 according to another embodiment of the present invention. The intermetallic contacts shown in FIGS. 30 and 31 are related to the contacts generated according to the process steps of 19-29, but the barrier layer 300 is directly under the conductors 18, 20 on the lower conductor surface, and directly under Bottom of the conductors 10, 12 on the upper conductor surface, and under the layers 50, 100, 200-204. When the structure becomes smaller, the barrier layer helps to solve reliability problems, as far as the manufacture of the conductor is concerned. The barrier layer 300 below the upper conductors 丨 0, 丨 2 and below the dielectric metal contact 34 can be applied to fill the figure with the contact -21-200308052 before the opening step. The above-mentioned insulating layers 56, 200, 202, and 50 may include silicon dioxide or a low-quality insulating material having a dielectric constant lower than that of silicon dioxide. The above-mentioned insulating eyebrows 204 may include a nitrogen silicon compound, a carbon silicon compound, or SiCOH. The conductive surface 64 and the conductors 10, 12 and 18, 20 and the conductive material used as the filling material may be a barrier layer 3 0 0, for example, may include a multilayer including a button and a nitride button. However, the materials used here are not all examples. Referring to the above description, although it is pointed out that the etching step has been shown in the figure as anisotropic, it is also possible to use an isotropic etching process or an etching process that at least prevents the etched edges of the contact points from extending vertically. This results in that the openings of the metal contacts at the boundary surfaces of the upper and lower conductors are different. In principle, the openings of the contacts can be bought on the upper or lower conductor surface. Conductors with larger intermetallic contacts will have smaller distances between the intermetallic contacts and each conductor. Even though the entire etching process has been used to form the contact openings, other methods, such as drilling, may be used in principle. Moreover, the present invention is limited to the materials of these layers, which are only used as examples here. In particular, it is necessary to use the same material for each, such as the two conductor surfaces. In addition, it is indicated that the filling of the upper conductor to be conductively connected to the lower conductor may be performed before the contact opening is formed. In this example, the upper metal is formed by using an additional etching step to form the contact opening. It was previously removed from the dot area, and then was taken from the conductive material to fill the contact opening. It may only fill the contact opening, and then fill the trench outside the dot area in another step. K material, 10052, copper. Listed so that the metal is not adjusted, so it is necessary to replace the grooved conductors.该 接 -22- 200308052 [Schematic description] Figure 1 shows the layout of the intermetallic contacts according to the present invention; Figures 2 to 8 show the two pairs of upper and lower conductors according to a first embodiment of the present invention A cross-sectional view of a pair of conductors connected by a dielectric metal contact, and also showing the conditions of the next manufacturing step in the process; Figure 9 shows a cross-sectional view of a cross-sectional view related to Figure 5, the pair of conductors in the structure of the upper conductor The effect of quasi-error is clearly shown; FIG. 10 shows a cross-sectional view related to the cross-sectional view of FIG. 5. In the case of a large etching depth, the effect of misalignment in the structure of the upper conductor is clearly shown; Figures 11 to 18 show cross-sectional views of two pairs of upper and lower conductors according to a second embodiment of the present invention. A pair of conductors are connected by a metal-to-metal contact, and it is also shown that the next one is manufactured in the manufacturing process. Step conditions; Figures 19 to 29 show cross-sectional views of two pairs of upper and lower conductors according to a third embodiment of the present invention. A pair of conductors are connected by a metal-to-metal contact and are also shown in the manufacturing process. Conditions for the next manufacturing step; Figure 30 shows A cross-sectional view showing an arrangement of a metal-metal contact according to a fourth embodiment of the present invention; FIG. 31 shows a cross-sectional view of the metal-metal contact of FIG. 30, which extends at a right angle to the area of FIG. 30; and FIG. 32 Shows 1C layout using traditional intermetallic contacts. Symbols of the drawings: 10, 12, 14, 16, 18, 20, 22, 24, 500, 502, 504, 5 06, 508, 510, 512, 514: conductors 26, 28, 30, 32, 516, 518 520, 522: contact point-23- 200308052 34, 36, 38, 40: contact area / metal contact 50, 56, 200, 202: insulation layer 52: lower conductor surface 5 4, 5 9: upper Main side 5 8, 7 2 · • Mask 60, 62: opening 64: upper conductor surface 6 6, 6 8: groove 74: contact area 7 6: contact opening 7 8: edge 80: boundary / connection Point surface 8 2: displacement_ 84: trench topology 1 0 0: etch stop layer 1 2 2: boundary area 2 4 4: interposer 3 0 0: barrier layer 524, 526, 528, 530, 532, 534, 536, 538 widened areas 540, 542, 544, 546: intermetallic contacts. -twenty four-