AU2003235621A1 - Feedthrough contacts and method for producing the same - Google Patents

Feedthrough contacts and method for producing the same

Info

Publication number
AU2003235621A1
AU2003235621A1 AU2003235621A AU2003235621A AU2003235621A1 AU 2003235621 A1 AU2003235621 A1 AU 2003235621A1 AU 2003235621 A AU2003235621 A AU 2003235621A AU 2003235621 A AU2003235621 A AU 2003235621A AU 2003235621 A1 AU2003235621 A1 AU 2003235621A1
Authority
AU
Australia
Prior art keywords
producing
same
feedthrough contacts
feedthrough
contacts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003235621A
Inventor
Wolfgang Klein
Klaus Koller
Markus Schwerd
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of AU2003235621A1 publication Critical patent/AU2003235621A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
AU2003235621A 2002-01-16 2003-01-07 Feedthrough contacts and method for producing the same Abandoned AU2003235621A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10201448A DE10201448A1 (en) 2002-01-16 2002-01-16 Production of a through-contact used in the production of integrated circuits comprises forming an insulating layer, forming a contact opening in a contact region, and filling the contact opening with a conducting material
DE10201448.5 2002-01-16
PCT/EP2003/000065 WO2003060993A1 (en) 2002-01-16 2003-01-07 Feedthrough contacts and method for producing the same

Publications (1)

Publication Number Publication Date
AU2003235621A1 true AU2003235621A1 (en) 2003-07-30

Family

ID=7712273

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003235621A Abandoned AU2003235621A1 (en) 2002-01-16 2003-01-07 Feedthrough contacts and method for producing the same

Country Status (5)

Country Link
EP (1) EP1466360A1 (en)
AU (1) AU2003235621A1 (en)
DE (1) DE10201448A1 (en)
TW (1) TW200308052A (en)
WO (1) WO2003060993A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007052049B4 (en) 2007-10-31 2020-06-18 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Process for structuring vertical contacts and metal lines in a common etching process

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4324638A1 (en) * 1992-07-28 1994-02-03 Micron Technology Inc Electric contact prodn. for integrated circuit - by self aligned process, esp. in ULSI mfr.
US5726100A (en) * 1996-06-27 1998-03-10 Micron Technology, Inc. Method of forming contact vias and interconnect channels in a dielectric layer stack with a single mask
US5891799A (en) * 1997-08-18 1999-04-06 Industrial Technology Research Institute Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates
US6211092B1 (en) * 1998-07-09 2001-04-03 Applied Materials, Inc. Counterbore dielectric plasma etch process particularly useful for dual damascene
US6157081A (en) * 1999-03-10 2000-12-05 Advanced Micro Devices, Inc. High-reliability damascene interconnect formation for semiconductor fabrication
US6225211B1 (en) * 1999-04-29 2001-05-01 Industrial Technology Research Institute Method for making stacked and borderless via structures on semiconductor substrates for integrated circuits
US6017817A (en) * 1999-05-10 2000-01-25 United Microelectronics Corp. Method of fabricating dual damascene
US6313025B1 (en) * 1999-08-30 2001-11-06 Agere Systems Guardian Corp. Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit
US6399512B1 (en) * 2000-06-15 2002-06-04 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer
US6635566B1 (en) * 2000-06-15 2003-10-21 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit

Also Published As

Publication number Publication date
WO2003060993A1 (en) 2003-07-24
TW200308052A (en) 2003-12-16
EP1466360A1 (en) 2004-10-13
DE10201448A1 (en) 2003-07-24

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase