EP1466360A1

EP1466360A1 - Feedthrough contacts and method for producing the same

Info

Publication number: EP1466360A1
Application number: EP03729428A
Authority: EP
Inventors: Klaus Koller; Wolfgang Klein; Markus Schwerd
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2002-01-16
Filing date: 2003-01-07
Publication date: 2004-10-13
Also published as: DE10201448A1; TW200308052A; WO2003060993A1; AU2003235621A1

Abstract

The invention relates to a method for producing feedthrough contacts (34) for creating a conductive connection between a first strip conductor (18) and a second strip conductor (10). According to the inventive method, an insulating layer (56) extending to a contact area (74) is formed on the first strip conductor (18), and a trench (66) for the second strip conductor (10), extending to the contact area (74), is formed in the upper side (70) of said insulating layer (56). A contact opening (76) is then formed in the contact region (74), said opening extending from the upper side (70) to the first strip conductor (18). The trench (66) opens up into said opening, the width of the contact opening being larger than the width of the trench. The contact opening (76) is then filled with a conductive material (78) in order to produce the feedthrough contact (34) and the second strip conductor (10) in the contact area (74), in such a way that the width of the second strip conductor (10)in the contact area (74) adapts to the size of the feedthrough contact (76) in a self-adjusting manner.

Description

description

Through contact and method of making the same

The present invention relates generally to integrated circuits and, in particular, to a through contact for producing a conductive connection between two conductor tracks.

At present, inter-metal contacts are used in the manufacture of integrated circuits for the conductive connection of two metal tracks, which have a diameter which is smaller than the width of the metal track above and below. When laying out an integrated circuit, the resulting overlap of the metal tracks in the contact area must be taken into account.

FIG. 32 shows a section of an exemplary layout that could previously have occurred in the design of an integrated circuit. Solid metal lines show four metal tracks 500, 502, 504 and 506 in FIG. 32, which are arranged in an upper structure or conductor track plane. Correspondingly, four metal tracks 508, 510, 512 and 514 are shown with dotted lines, which are arranged in a lower structural level, which is located below the upper structural level and is insulated therefrom. As can be seen in FIG. 32, the metal tracks 500-514 in FIG. 32 are arranged by way of example so that the metal tracks 500-506 or 508-514 of a structural plane run parallel to one another, and that the metal tracks 500-514 of the different structure levels are each arranged in pairs so that a metal track of one structure level extends to a contact location 516, 518, 522 and 522, from where a respective metal track of the other structure level leads in the same direction. As can be seen, each metal track 500-514, ie both that of the upper structural level and that of the lower structural level, has a contact point 516, 518, 520 and 522 A broadened area 524, 526, 528, 530 or 532, 534, 536 and 538, whereby it is pointed out that only a short section of the border of the broadened area 532-538 of the metal tracks 508-514 of the lower structural level can be seen since the rest of the border is covered by the widened area 524-530 of the metal tracks 500-506 of the upper structural level. The widened regions 524-528 are electrically connected to one another by intermetallic contacts 540, 542, 544 and 546, which have a cross section which is smaller than the widened regions, and which are produced in a structuring step which is separate from the structuring of the interconnect levels become.

Fig. 32 also shows by means of double arrows minimum widths wl, w2 and minimum distances sl, s2 which must be adhered to during the circuit design during the layout and which are determined by design rules which depend on the manufacturing process intended for later production, e.g. a CMOS process. The minimum widths w1 and w2 define the minimum width of the metal tracks of the upper and lower structure level and are obtained, for example, due to physical limits in the lithography step for structuring the individual structure levels. The minimum distances sl and s2 define the minimum distance that a metal web must have from another metal web or a first feature from a second feature at the upper and lower structure level, and is also obtained, for example, due to physical limits in the lithography step for structuring the individual structure levels.

As can be seen from FIG. 32, each metal track 500-514 at the contact location 516-522 is widened to the outside by a length X on each side. As can also be seen, the broadened areas 524-538 are larger than the cross-section of the intermetallic contacts 540-546. The resulting overlap takes process tolerances into account that result from adjustment errors between the structuring of the holes for the intermetallic contacts 540-546 on one side and the structuring of the metal tracks of the upper or lower structural level on the other side. Due to the widening by the length X, the minimum possible conductor spacing sl or s2 cannot be used in the layout for metal tracks with intermetallic contacts. The minimum distance between two metal tracks of the same structure level with minimum width effectively results in sl + X and is therefore increased by the value X, ie the length by which the minimum track width must be widened due to the necessary overlap with regard to the metal contact.

The above-explained increase in the minimum distance between metal tracks of the same structural level consequently brings about a reduction in the degree of integration of integrated circuits. However, a reduced chip area would be desirable in many areas of application of integrated circuits, since there are often considerable demands on the chip area, such as in the field of chip cards.

A further disadvantage of the contacting scheme described with reference to FIG. 32 is that the intermetallic contacts must always have a smaller diameter than the conductor tracks for the above reasons and are therefore the critical point for electromigration.

There is therefore a need for a contacting scheme which enables a higher integration rate and a higher resistance to electromigration.

The object of the present invention is to provide a through contact for producing a conductive connection of a first conductor track and a second conductor track and a method for producing the same, so that the through contact has improved electrical properties and / or enables an increased integration rate.

This object is achieved by a method according to claim 1 and a through contact according to claim 13.

The present invention is based on the knowledge that the conventional way of structuring the conductor tracks at the contact location must be separated from the respective through contact in order to enable the structuring of the conductor tracks with the least possible spacing in terms of process technology Conductor tracks can be carried out in one conductor level. According to the invention, therefore, one of the conductor tracks is formed within the contact area together with the through contact in the same process step, namely by forming and then filling a contact opening in the contact area, into which a trench for the one conductor track opens. This enables a self-adjustment of the width of this conductor track in the area of

Through contact to the size of the through contact achieved. Since the formation of the contact opening and thus the structuring of the wide area of the one conductor track, which is self-adjusted to the size of the through contact, and the through contact are carried out in a step separate from the structuring of this conductor track outside the contact area, the widening does not result in an increased minimum distance to be observed between adjacent conductor tracks of a conductor level, since the adjustment errors in the formation of the contact opening are smaller than the minimum distances of features of a structuring step to be observed due to the process. Consequently, the chip area required is reduced by the invention. Furthermore, the self-adjustment prevents the through contact from being narrower than the conductor tracks, as a result of which the electro-migration resistance of the through contact can be increased and the resistance of the latter can be reduced. On the basis of the present invention, it is consequently possible to design and manufacture integrated circuits which have a reduced space requirement and which have improved electrical properties owing to the increased resistance to electromigration and the reduced resistance of the contacts between conductor tracks.

According to a special exemplary embodiment, the metallic contact is produced using dual damascene technology.

Further preferred embodiments of the present invention are defined in the following detailed description and in the subclaims.

Preferred exemplary embodiments of the present invention are explained in more detail below with reference to the accompanying drawings. Show it:

1 shows a portion of an exemplary layout in which intermetallic contacts are used in accordance with the present invention;

Fig. 2 to Fig. 8 cross-sectional views of two pairs of an upper and a lower conductor track, of which the

Interconnects of a pair are connected by an intermetallic contact, wherein states of successive process steps in the manufacture are shown, according to a first exemplary embodiment of the present invention;

FIG. 9 shows a cross-sectional view corresponding to that of FIG. 5, the effect of an adjustment error in the structuring of the upper conductor track being illustrated; FIG. 10 shows a cross-sectional view corresponding to that of FIG. 5, the effect of an adjustment error when structuring the upper conductor track being illustrated in the case of a greater etching depth;

11 to 18 are cross-sectional views of two pairs of an upper and a lower conductor track, of which the conductor tracks of a pair are connected by an metal contact, states of successive process steps being shown during production being shown according to a second exemplary embodiment of the present invention;

19 to 29 are sectional views of two pairs of an upper and a lower interconnect, of which the interconnects of a pair are connected by an intermetallic contact, showing states of successive process steps during manufacture, according to a third exemplary embodiment of the present invention;

30 shows a cross-sectional view of an intermetallic contact arrangement according to a fourth exemplary embodiment of the present invention;

31 shows a cross-sectional view of the intermetallic contact arrangement from FIG. 30, the section running perpendicular to that from FIG. 30; and

32 shows an exemplary layout of an integrated circuit using conventional intermetallic contacts.

Before the invention with reference to exemplary embodiments is explained in more detail with reference to the figures, it is pointed out that the same or functionally identical elements in the Figures are provided with the same reference numerals, and that a repeated description of these elements is avoided in the description of the figures.

1 first shows a portion of an exemplary layout in which through contacts are used in accordance with the present invention. From the description that follows now with reference to FIG. 1, it will be clear that the present invention makes it possible to set conductor tracks of a conductor track or structural level in a layout as narrowly as it is by means of the process parameters for conductor tracks with a minimal conductor track width is possible.

In the layout section of FIG. 1, four conductor tracks 10, 12, 14, 16 are shown with solid border lines, which are arranged in an upper structural level or conductor track level. Furthermore, four conductor tracks 18, 20, 22 and 24 are shown with dotted outline lines, which are arranged in a lower structural level. As in the example of FIG. 32, the conductor tracks 10-24 in the layout of FIG. 1 are arranged such that conductor tracks 10-16 or 18-24 of a structural plane are arranged parallel to one another, and that the conductor tracks 10-24 are arranged in pairs are aligned so that a conductor track of a structural plane extends in one direction to a contact location 26, 28, 30 and 32, from where a corresponding conductor track of the other structural plane continues in the same direction (in the longitudinal direction of the sheet in FIG. 1). At each contact location 26-32, a through contact is formed in a contact area 34, 36, 38 and 40, which has the same dimensions as the contact area and is therefore indicated in the following description with the same reference number as the corresponding contact area. It should be noted that the border line of the lower conductor tracks 18-24 in the contact area 34-40 on the one hand by the solid side lines of the upper

Trace 10-16 and the other through the section of the dashed line of the contact areas 34-40, which crosses the upper conductor tracks 10-16, are hidden.

It is pointed out that in the layout shown in FIG. 1, no conductor track has a widened area, although according to the present invention, each of the conductor tracks 10-16 of the upper structural level in the contact area 34-40 has a width which is self-aligned to the width of the Contact area or the contact 34-40 is adapted, as will be explained in more detail below. Specifically, this means that in the event that Fig. 1 would represent a top view of the trace contact arrangement, the solid outline of each trace 10-16 would run along the top structural level at contact location 26-32 of dashed line 34-40 , The reason for the different presentation will be explained in the following.

1 also shows, using double arrows, minimal conductor track widths wl and w2 and minimum distances sl and s2, which are determined by the process technology on which the layout is based and which must be observed when designing the layout. The track widths wl and w2 define the minimum width for tracks of the upper and lower track level, while the minimum distances sl and s2 define minimum distances between adjacent tracks or other features of a track level, ie the upper or the lower. A double arrow also shows a distance s3 of the contact 34, which conductively connects the upper interconnect 10 to the lower interconnect 18, from the adjacent upper interconnect 12. It is recalled that, as has already been mentioned above, the upper conductor track 10 at the contact location 26 has a width according to the invention which is self-adjusted to the width of the contact 34, so that the distance s3 also the distance of the upper conductor track 10 to the adjacent conductor track 12. A distance s4 between adjacent contacts 34 and 36 is also shown in FIG. 1. As can be seen in FIG. 1, the minimum possible distance sl or s2 and the minimum possible conductor width wl and w2 can be used for the arrangement of the conductor tracks 10-24, even if intermetallic contacts 34-40 are provided, and also if 1, the distance between two adjacent upper conductor tracks 10-16 at the contact locations 26-32 is smaller than the minimum width sl, namely s3. As mentioned above, the conductor tracks 10-24 are also shown within the contact regions 34-40 with the minimum conductor track width w1 or w2, although the upper conductor tracks 10-16 at the contact locations 26-32 have a width which is self-adjusted to the contact width according to the invention have, because this ensures in the case of a computer-aided layout design that when checking compliance with the design rules, such as is carried out by a subroutine, no case distinction must be made with regard to the contact points 26-32 when checking the question of whether the Minimum distance sl between features of the upper conductor level has been observed. In the other case, namely that the upper conductor tracks 10-16 would be shown with border lines which run along the dashed lines 34, an error would be caused when checking the compliance with the design rules at the contact points 26-32 because the distances between the contact areas 34-40 and the conductor tracks 10-16 s3 and are therefore smaller than the minimum distance sl.

The reason why the upper conductor tracks 10-16, despite the increased width at the contact points 26-32, which is adapted to the contact width of the intermetallic contacts 34-40, can be set as narrow as if they had the minimum width w1 everywhere, is that the structuring of the conductor tracks 10-16 outside the contact areas 34-40 on the one hand and the structuring of the contacts and the conductor tracks 10-16 within the contact areas 34-40 on the other hand various process steps are carried out. In this way, the spacing of the area of the conductor tracks 10-16 within the contact areas 34-40 is not subject to the process-related minimum spacing condition sl, such as, for example, lithography. The distance s3 of the contact area 34 to the upper conductor track 12 only has to be greater than a minimum distance which is defined by process tolerances, such as, for example, adjustment errors with respect to the upper and lower conductor track levels in the exposure and wide tolerance of the intermetallic contact 34 in the case of exposure and etching. However, these process tolerances are much smaller than the minimum widths wl and w2 and minimum distances sl and s2 of the conductor tracks 10-24, which are caused, for example, by lithography.

For the sake of completeness, it should be pointed out that the distances between the adjacent intermetallic contacts, since they are produced in a common process step, are also subject to compliance with a process-dependent minimum distance S4, which depends on the mask technique used, and which depends on Sl can distinguish.

As has been described in the preceding description of the layout of FIG. 1, the present invention makes it possible to set conductor tracks in a layout as narrowly as is possible taking into account process-related minimum distances s1 or s2, which results in a minimal or reduced space requirements. For certain areas of application in which fixed chip area sizes are specified by certain standards, this means that the area saved can be used to implement additional functions or the like. Furthermore, as shown in FIG. 1, the width of each intermetallic contact is larger than the width of the conductor tracks 10-24 outside the contact locations 26-40, so that the intermetallic contacts are significantly improved in their resistance to electromigration. For integrated circuits, this means consequent invention consequently a reduced chip area and improved electrical properties.

Various exemplary embodiments for producing an intermetallic contact according to the present invention are described below with reference to FIGS. 2-29. Each of these figures shows a cross section on the left side of an upper and a lower conductor track, which are or are to be conductively connected by a respective intermetallic contact, and on the right side an upper and lower metal track, which are not or are not connected to one another should, namely after successive process steps for producing the intermetallic contact. The cross sections thus correspond to cross sections along the section line A in the layout of FIG. 1, if it is assumed that the lower conductor track 20 extends over the section plane A.

The illustrated exemplary embodiments represent process sequences with which an intermetallic contact can be produced in dual damascene technology, and in which the width of the intermetallic contact can be provided to be larger than the minimum widths of the upper and lower metal tracks, whereas, in contrast, the intermetallic contacts are more conventional The type of the intermetallic contact always had to be smaller or equal to the width of the upper and lower metal tracks, as was explained with reference to FIG. 32.

2-8, a first exemplary embodiment for producing an intermetallic contact in accordance with the present invention will first be described. 2 shows a state during the process sequence in which the conductor tracks of the lower conductor level have already been formed and a mask for structuring the upper conductor tracks or the upper conductor level has been applied. FIG. 2 shows a first insulation layer 50, in which the lower conductor track 18 and the lower conductor track 20 of the lower conductor level are structured, for example by means of damascene technology The lower conductor level is generally indicated at 52 and is adjacent to a main side 54 of the first insulation layer 50. As can be seen, the structuring of the lower conductor tracks 18, 20 of the lower conductor level 52 must comply with the minimum distance s2 imposed by the design rules. A second insulation layer 56 has been applied to the first insulation layer 50 or the main side 54, for example by deposition. As indicated by a double arrow, the second insulation layer has a thickness t1. Subsequently, a mask 58 for the structuring of the upper conductor tracks 10 and 12 of the upper conductor level has been applied to a main side 59 of the insulation layer 56 and has been suitably structured, for example by exposure and subsequent development, in order to create openings 60 and 62 at those locations to which the conductor tracks 10 and 12 are to be formed, or to expose the second insulation layer 56 at these locations. The mask 58, such as photoresist, is adjusted relative to the lower conductor level or relative to the lower conductor tracks 18 and 20 or a conductor mask used for structuring the same.

3 shows the state which arises after, for example, by means of an etching step at the exposed locations 60, 62 for the upper conductor level 64, trenches 66, 68 of the depth d1 have been formed in the second insulation layer 56. The depth dl thus defines the layer thickness of the upper conductor planes 64. The mask 58 is then removed using known methods, such as e.g. by means of lacquer stripping, dry or wet etching.

4 shows the state which arises after a mask 72, such as, for example, photoresist, for the formation of the intermediate metal contact 34 has been applied to the structured upper side 59 of the second insulation layer 56 and structured, such as, for example, exposed and developed in order to form an opening 74 in the mask 72, which on the side 59 of the second insulation tion layer 56 defines an exposed contact area. The mask 72 is adjusted either with respect to the lower or the upper conductor level or a lower or an upper conductor mask 52, 64.

As can be seen in FIG. 5, a contact opening 76 is then etched down from the opening 74 in the mask 72 into the second insulation layer 56 down to the lower conductor level 52 or the lower conductor track 18 or the main side 54 , The depth of the etching is therefore d2 = tl - dl. If the overetching time is short, the area of the lower conductor track 18 is opened by overlapping it with the area where the trench 66 (FIG. 4) for the upper conductor track has been formed. A misadjustment of the upper conductor track trench 66 and the lower conductor track 18 to one another consequently leads to a reduced contact area, as will be described in more detail with reference to FIG. 9. At the edge area 78 of the contact opening 76, the opening depth is reduced by the depth d1 in comparison to the area in which the trench 66 has been formed for the upper conductor track.

After etching the contact opening 76, as shown in FIG. 6, the mask 72 is removed again and then, as shown in FIG. 7, a conductive material 78, such as e.g. a metallic material made of copper, aluminum or another metal, applied for the upper conductor level 64 on the side 59 of the second insulation layer 56, e.g. by a deposition process or another suitable process. As can be seen in FIG. 7 on the left side, the applied conductive material 78 fills both the contact opening 76 for the intermetallic contact 34 (FIG. 1) and the trench 66 for the upper interconnect 10 (FIG. 1). The filling of the trench 68 for the upper conductor track 12 can be seen on the right-hand side.

The excess material with a thickness t3 above the side 59 of the second insulation layer 56 becomes as shown in FIG 8 is removed in a subsequent process step, for example by chemical-mechanical polishing, the state shown in FIG. 8 occurring in which both the intermetallic contact 34 and the upper conductor planes 64 and the upper conductor tracks 10 and 12 are completed. As can also be seen in FIG. 8, the conductor tracks 10, 12 are insulated from one another by the removal of the excess conductive material 78 applied.

In FIG. 8, the portion of the conductor track 10 and the portion of the intermetallic contact 34 in the metallic material 78 filled in the contact opening 76 are shown by a dashed line 80 within the contact opening 76. The dashed line 80 thus represents the limit or. 4, and the intermetallic contact 34. As can be seen, the width of the conductor 10 in the contact area is the width of the intermetallic contact 34 adjusted in a self-adjusted manner since the conductor track 10 in the contact area and the intermetallic contact 34 are fixed in a common etching step (FIG. 5).

As has been described above, two adjustments are made during the production of the intermetallic contact, namely that of the mask 58 for the upper conductor level relative to the lower conductor level and that of the mask 72 for the contact opening 76 relative to either the lower or the upper conductor level. Both adjustments are subject to adjustment errors, which, however, are small enough that they do not lead to short circuits taking into account the minimum distances sl and d2. However, due to adjustment errors in the structuring of the upper conductor track 10, problems arise in the formation of the contact opening 76 for the intermetallic contact 34, which are explained in more detail below with reference to FIGS. 9 and 10. FIG. 9 shows the intermetallic contact of FIGS. 2-8 in a state which corresponds to that of FIG. 5. In contrast to the state of FIG. 5, an adjustment error of length Δs has occurred in FIG. 9 when structuring the upper conductor track 10. As in FIG. 5, the etching time and the etching rate are set such that the depth of the etching is d2, with a slight overetching time for opening the lower conductor track 18. As can be seen, the lower conductor track 18 is not completely opened in the contact area, but only in the area in which it overlaps with the structuring or the trench 66 for the upper conductor track 10, since the only depth here is the opening depth of the contact opening 76 to the lower conductor track 18. Due to the incorrect adjustment in the mask 58 (FIG. 2), the contact area, ie the interface between the contact opening 76 or the intermetallic contact on one side and the lower conductor track 18 on the other side, is consequently reduced, as is the case, for example, with 82 can be seen. The contact resistance thus increases depending on the misadjustment during the adjustment of the mask 58 for the upper conductor level 64 (FIG. 2), which leads to an undesired inequality or spread of contact resistance values within an integrated circuit.

The problem shown in FIG. 9 cannot be solved either by increasing the etching time and thus increasing the depth to which the etching is carried out, as will be described with reference to FIG. 10. FIG. 10 also shows a state of the intermetallic contact 34 corresponding to FIG. 5, an adjustment error of the size Δs occurring during the adjustment of the upper conductor level as in FIG. 9. Unlike in FIG. 5 and FIG. 9, the etching time and etching rate are set such that the depth of the etching is t1. This higher etching time exposes the entire lower conductor track 18 in the area of the intermetallic contact, but at the same time an increased etching of the insulation layer 50 in the area next to the lower conductor track 18 occurs in which the trench 66 is created for the upper conductor track 10, but the lower conductor track 18 is not structured, as is indicated at 84 in FIG. 10. As can be seen at 84, a trench is consequently formed to the side of the lower conductor track 18. This topology, which results from the etching next to the lower conductor track 18 and the different etching depth in the edge region of the contact opening, can lead to further problems with barrier tightness and filling behavior in the metal deposition.

With reference to FIGS. 11-18, an exemplary embodiment will now be described, which counteracts the problems of the exemplary embodiment of FIGS. 2-10 that arise due to the incorrect adjustment in the structuring of the upper conductor level by providing an etching stop layer above the lower conductor level.

The following embodiment solves the problems of reducing the contact area depending on the misalignment in the structuring or exposure of the upper conductor level or the topology that occurs at the bottom of the intermetallic contact while increasing the etching time in that a further between the first insulation layer 50 and the second insulation layer 56 Insulation layer 100 is provided. Accordingly, FIG. 11, which shows the intermetallic contact in a state during production which corresponds to that of FIG. 2, shows the insulation layer 50 with the first conductor level 52 and in particular the lower conductor tracks 18 and 20, the further insulation layer 100 which is on the Upper side 54 of the insulation layer 50 is applied, the second insulation layer 56 arranged above the further insulation layer 100 and the mask 58 for structuring the upper conductor level, which is adjusted with respect to the lower conductor level and already defines openings 60, 62.

In two subsequent process steps, as described in the first exemplary embodiment with reference to FIGS. 3 and 4, a trench etching of the upper conductor level 64 μm is carried out in succession to produce the trenches 66 and 68 of the depth d1 for the upper conductor track 10 or 12 (FIG. 1), as shown in FIG. 12, removal of the mask 58 and application of a new mask 72 to form the intermetallic contact or the late contact opening, which has an opening 74 at the contact area, as can be seen in FIG. 13.

In contrast to the first exemplary embodiment, part of the contact opening 76 of the intermediate metal contact is then etched into the second insulation layer 56 using an etching process which, as can be seen in FIG. 14, stops selectively on the further insulation layer 100. As a result, in contrast to the first exemplary embodiment, the second insulation layer 56 can also be in the edge region 102 of the contact opening 76, i.e. where the trench 66 was not located, are completely removed, as a result of which a flat bottom of the contact opening on the further insulation layer 100 is obtained. The further insulation layer 100 consequently serves as an etching stop layer.

As can be seen in FIG. 15, the mask 72 is removed after the formation of the contact opening 76 up to the etching stop layer 100. As can be seen in FIG. 16, after the mask 72 has been removed, an etching process is carried out, by means of which the part of the etching stop layer 100 exposed at the contact opening 76 is opened and the entire lower conductor track 18 is exposed in the region of the intermetallic contact opening 76. The etching process can be selective to the first insulation layer 50 and to the second insulation layer 56, as is the case here. This completes the formation of the contact opening 76.

As can also be seen in FIG. 15, the effective contact area for the lower conductor track 18 is essentially always the same as long as the length x by which the width of the contact opening 76 is relative to the width of the lower conductor track 18 is widened, is sufficient to compensate for incorrect adjustments when adjusting the mask 72.

In accordance with steps 7 and 8 of the first exemplary embodiment, by applying the conductive material 78, as shown in FIG. 17, and subsequently removing the excess of conductive material 78, the intermetallic contact 34 and the upper conductor level 64 or the first and second are connected Conductor 10 or 12 formed.

In addition to eliminating the problem of reducing the contact area depending on the misalignment in the structuring of the upper conductor level and the topology that occurs at the bottom of the intermetallic contact in the case of an extended etching time, as occurred in the first exemplary embodiment, the second exemplary embodiment provides by providing the additional ones Insulation layer 100 also has the advantage that the mask 72 (FIG. 14) can be removed or detached to form the contact opening while the conductor track 18 of the lower conductor level 52 has not yet been exposed (see FIGS. 14 and 15). This is advantageous because the mask 72, e.g. a photoresist layer, usually removed with an oxygen plasma, which strongly oxidizes exposed metal layers. It is pointed out, however, that the removal of the etch stop layer 100 from FIG. 16 could also be carried out before the removal of the mask 72 (FIG. 15), although the process sequence sequence described above is preferred for the reasons described above.

In the exemplary embodiments described above, the thickness of the upper conductor level or of the upper conductor tracks is defined by the etching depth d1 in the insulation layer 56 (cf. FIGS. 3 and 12). The thickness d1 therefore depends directly on the reproducibility of the etching depth and is therefore subject to undesirable fluctuations. An exemplary embodiment for producing an intermetallic contact according to the present invention is described below with reference to FIGS. tion described, in which the second insulation layer 56 by two insulation layers 200, 202, between which an intermediate layer 204 is arranged as an etch stop layer, and by which the thickness of the upper conductor level or upper conductor tracks is independent of any etching rate or etching duration on the thickness of the insulation layer 202 can be set above the intermediate layer 204.

FIG. 19 shows a state during the production of the intermetallic contact, which corresponds to that of FIGS. 2 and 11. In particular, FIG. 19 shows the first insulation layer 50, in which the first conductor level 52 is formed with the conductor tracks 18 and 20, the etching stop layer 100 provided on the upper side 54 of the first insulation layer 50, and the insulation layers replacing the second insulation layer 56 of the first two exemplary embodiments 200, 200, which are arranged on the etching stop layer 100, and between which the intermediate layer 204 is arranged, and the mask 58 for structuring the upper conductor level, which is applied to the insulation layer 202. As described above, the mask 58 is adjusted to the lower conductor level 52 and has two etching openings 60, 62 for the formation of the two upper conductor track trenches. The thickness of the insulation layer 202, the intermediate layer 204, the insulation layer 200 and the etch stop layer 100 are given by way of example in FIG. 19 with the thicknesses d2, d4, d3 and d5.

After the mask 58 for the upper conductor tracks has been applied, as shown in FIG. 19, as shown in FIG. 20, the insulation layer 202 of the thickness d2 is etched using a selective etching process in order to remove part of the trenches 66, 68 for the upper conductor level 64 and in particular for the upper conductor 10 and the upper conductor 12 to form. The etch selectively stops on the intermediate layer 204, which consequently acts as an etch stop layer. Thereafter, as shown in FIG. 21, the mask 58 is removed and, as shown in FIG. 22, the mask 72 for the intermetallic contact is applied to the insulation layer 202 which has an opening 74 for the subsequent formation of the contact opening at the contact area. The insulation layer 202 within the contact area 74 defined by the mask 72 is then removed by means of a further etching process which is selective with respect to the intermediate layer 204, as can be seen in FIG. 23. Further selective etching processes in the contact region 74 are carried out to remove the intermediate layer 204, as can be seen in FIG. 24, and to remove the insulation layer 200, as can be seen in FIG. 25. 23-25 selectively stop on the layer that follows in each case below the layer to be etched, ie the intermediate layer 204, the insulation layer 200 or the etch stop layer 100. After these etching steps, the contact opening 76 is formed except for the removal of the etch stop layer 100 completed.

Thereupon, as can be seen in FIG. 26, the mask 72 is removed and in a further etching process the etching stop layer 100 is opened and the lower conductor track 18 is exposed in the region of the intermetallic contact, whereby the formation of the contact opening 76 is completed, as shown in FIG Fig. 27 is visible. During this etching step, the intermediate layer 204 is also etched in the structured regions in the upper conductor level, in particular in the region of the upper conductor tracks 10 and 12, as a result of which the depth of the trench 68 is increased to d2 + d4. This etching process can be selective for the insulation layer 200 and for the insulation layer 50. As in the second embodiment, it is also possible to remove the mask 72 after opening the etch stop layer 100, but in this case the mask 72 must be detached with the metal surface open and the associated oxidation problems. In the latter case, however, the simultaneous etching of the intermediate layer 204 in the structured areas Chen the upper conductor level can be avoided during the etching of the etch stop layer 100.

Then, as in the previous exemplary embodiments, the openings are filled, i.e. of the contact opening 76 and the trench 66 and 68 for the upper conductor tracks with conductive material 78, as shown in FIG. 28, and then excessly applied conductive material 78 is removed, as shown in FIG. 29. As can be seen, the thickness of the upper conductor level is equal to the thickness of the two layers 202 and 204 and is therefore not subject to fluctuations in the etching rate or duration.

30 and 31 show sectional images of the intermetallic contact 34 from FIG. 1 along plane A and plane B according to a further exemplary embodiment of the present invention. The intermetallic contact shown in FIGS. 30 and 31 corresponds to that which is produced in the production according to FIGS. 19-29, but with a barrier layer 300 directly below the conductor tracks 18, 20 of the lower conductor level and the conductor tracks 10, 12 of the upper conductor level or is provided below the intermetallic contact in order to delimit them laterally and below against the layers 50, 100, 200-204. This barrier layer helps to solve reliability problems in the manufacture of the conductor tracks when the structure is reduced in size. The barrier layer 300 below the upper conductor tracks 10, 12 and the intermetallic contact 34 can be applied, for example, before the step of filling the contact opening in FIG. 28.

The insulation layers 56, 200, 202 and 50 mentioned above can consist of silicon dioxide or of a low-k material, ie an insulation material with a dielectric constant that is smaller than that of silicon dioxide. The insulation layers 100 and 204 mentioned above can be made of silicon nitride, silicon carbide or SiCOH, for example. The managerial levels 52, 64 or the conductor tracks 10, 12 and 18, 20 and the conductive material used for filling can be copper, for example. The barrier layer 200 may, for example, be a multiple layer made of tantalum and tantalum nitride. However, the materials given are only non-exhaustive examples.

With reference to the foregoing description, it should be noted that although the etch steps have been previously shown in the figures to be anisotropic, isotropic or at least etch methods may also be used in which the etch edge of the intermetallic contact is formed such that it is not perpendicular. This results in different dimensions of the intermetallic contact opening at the interface with the upper or lower conductor track. In this case, the adjustment of the contact opening, which can generally be carried out with respect to the upper or lower conductor level, is preferably adjusted to that conductor level in which the diameter or the expansion of the intermetallic contact is greater, since here the distance of the intermetallic contact to the relevant neighboring one Trace is smaller.

Furthermore, it is pointed out that although only etching processes have been used in the foregoing to form the contact opening, other processes can also be used in principle, e.g. Drilling or the like. Furthermore, the invention is not limited to the materials for the layers, etc., which have been mentioned above as examples. In particular, for the individual layers, e.g. the two ladder levels, not the same materials are used.

It is also pointed out that the trench for the upper conductor track, which is to be conductively connected to the lower conductor track, can be carried out before the contact opening is formed, the metal of the upper one The conductor track in the area of the contact area is removed, for example, by means of an additional etching step before the contact opening is formed, in order then to be replaced by the conductive material which is applied when the contact opening is filled. Furthermore, it is possible to only fill the contact opening and then to fill the trenches outside the contact areas in a separate step.

LIST OF REFERENCE NUMBERS

10 trace of the upper trace level 12 trace of the upper trace level 14 trace of the upper trace level 16 trace of the upper trace level 18 trace of the lower trace level 20 trace of the lower trace level 22 trace of the lower trace level 24 trace of the lower trace level 26 contact point 28 contact point 30 contact point 32 contact point 34 contact area / Intermetallic contact 36 contact area / intermetallic contact 38 contact area / intermetallic contact 40 contact area / intermetallic contact 50 first insulation layer 52 lower interconnect level

54 upper main side of the first insulation layer 56 second insulation layer

58 Mask for the upper conductor level

59 upper main side of the second insulation layer 60 opening

62 opening

64 upper conductor level

66 trench

68 trench 72 mask for contact opening

74 contact area

76 contact opening

78 edge area of the contact opening

80 boundary / contact surface 82 offset

84 trench topology 100 etch stop layer 102 edge area of the contact opening

200 insulation layer

202 insulation layer

204 intermediate layer 300 barrier layer

500 tracks of the upper track level

502 trace of the upper trace level

504 trace of the upper trace level

506 trace of the upper trace level 508 trace of the lower trace level

510 trace of the lower trace level

512 trace of the lower trace level

514 trace of the lower trace level

516 contact location 518 contact location

520 contact location

522 contact location

524 widened area

526 widened area 528 widened area

530 widened area

532 widened area

534 widened area

536 widened area 538 widened area

540 intermetallic contact

542 intermetallic contact

544 intermetallic contact

546 intermetallic contact

Claims

claims

1. A method for producing a through contact (34) for producing a conductive connection of a first conductor track (18) and a second conductor track (10), with the following steps:

A) providing an insulation layer (56; 200, 202) with a first and a second (59) main side opposite the same, the first conductor track (18) extending into a contact region (74) on the first main side, and a trench (66) extending to the contact region (74) and having a trench width (i) for the second conductor track (10) is formed in the second main side (59);

B) forming a contact opening (76) in the contact area (74), which extends from the second main side (59) to the first conductor track (18) and into which the trench (66) opens; and

C) filling the contact opening (76) with a conductive material (78) in order to produce the through contact (34) and the second conductor track (10) in the contact area (74),

wherein the step of forming and trenching the second conductor track is carried out using different masks, and the width of the contact opening formed is greater than the trench width (wi), so that after the contact opening has been filled, a conductor track width of the second conductor track (10) in Contact area (74) is adjusted in a self-adjusted manner to the width of the through contact (76).

2. The method according to claim 1, wherein in step C) also the trench for the second conductor track (10) is filled with the conductive material to produce the second conductor track (10).

3. The method according to claim 1 or 2, wherein step A) has the following substeps:

AI) providing a further insulation layer (50);

A2) forming a trench for the first conductor track (18) in a main side (54) of the further insulation layer (50);

A3) filling the trench for the first interconnect (18) with a conductive material to form the first interconnect (18);

A4) applying the insulation layer (56) on the main side (54) of the further insulation layer (50); and

A5) Forming the trench (66) for the second conductor track (10) in the main side (59) of the insulation layer (56) opposite the further insulation layer (50).

4. The method according to claim 3, wherein the sub-step A5) has the following sub-step:

A5a) adjusting the position of the trench (66) for the second conductor track (10) relative to the first conductor track (18).

5. The method according to any one of the preceding claims, wherein step B) has the following sub-step:

Bl) adjusting the position of the contact opening (76) relative to the first conductor track (18) or to the trench (66) for the second conductor track (10).

6. The method according to any one of the preceding claims, wherein in step B) the contact opening (76) is formed such that the size of the through contact (34) is larger than a conductor track width (w2) of the first conductor track (18).

7. The method according to any one of the preceding claims, wherein in step B) the contact opening (76) is formed such that the size of the through contact (34) is greater than a conductor track width (wl) of the trench 10 for the second conductor track (10) is.

8. The method according to any one of claims 5 to 7, wherein step B) has the following substeps:

B2) applying an etching mask (72) on the second main side (59) of the insulation layer (56) such that the second main side (59) is exposed at the contact region (74); and

B3) etching the insulation layer (56) from the second main side (59) to form the contact opening (76).

9. The method according to claim 8, in which in step B3) an etching rate and an etching time are set such that a depth of the etching is a thickness (dl) of the insulation layer (56) minus a depth (dl) of the trench (66) for the second conductor track (10) corresponds.

10. The method according to claim 2, wherein step A) has the following substep:

A6) before sub-step A4), applying an etching stop layer (100),

and in which step B) has the following substeps:

B2 ') applying an etching mask on the second main side (59) of the insulation layer (56) such that the second

Main layer (59) exposed at contact area (74); and B3 ') selective etching of the insulation layer (56) from the second main side (59) to the etching stop layer (100);

B4 ') removing the etching mask (72); and

B5 ') etching the etching stop layer (100) from the second main side (59) to the first conductor track (18).

11. The method according to claim 2, in which step A) instead of sub-step A5) comprises the following sub-steps:

A5 ^" ) applying an intermediate layer (204) on the insulation layer (200);

A6 ^" ) applying a partial insulation layer (202) on the intermediate layer (204); and

A7 ") etching the second partial insulation layer (202) up to the intermediate layer (204) in order to form the trench (66) for the second conductor track (10).

12. The method according to any one of the preceding claims, wherein the interconnect distance of the first interconnect (18) from a first adjacent interconnect (20) outside the contact area (74) and / or the interconnect distance of the second interconnect (10) from a second adjacent one The conductor track (12) outside the contact area (74) essentially corresponds to the minimally possible process track distance between two conductor tracks.

13. through contact for producing a conductive connection of a first conductor track (18) and a second conductor track (10), the first conductor track (18) extending into a contact region (74) on a first main side of an insulation layer (56), and a trench (66) extending to the contact region (74) and having a trench width (wi) for the second conductor track (10) in one the second main side (59) of the insulation layer opposite the first main side, with

a contact opening (76) in the contact area (74) which extends from the second main side (59) to the first conductor track (18) into which the trench (66) for the second conductor track (10) opens, the contact opening and the trench (66) for the second conductor track (10) in the contact area (74) are filled with a conductive material (78) to form the through contact (34) and the second conductor track (10) in the contact area, the contact opening and the Trenches for the second conductor track are formed by means of different masks, and the width of the contact opening formed is greater than the trench width (wi), so that the width of the second conductor track (10) in the contact area is self-adjusted to the width of the through contact (34).