JP2005150493A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device by which the reliability, manufacturing yield, etc., of a semiconductor device can be improved by securing a short margin between a wiring pattern and a via pattern in the groove-first dual damascene method. <P>SOLUTION: The method of manufacturing the semiconductor device includes a step of forming a lower film 3 on interlayer insulating films 1 and 2 formed on lower-layer wiring, a step of forming a wiring groove pattern 5 by etching the lower film 3 in a linear or striped state, and a step of forming an upper film 6 on the lower film 3 having the formed wiring groove pattern 5. The method also includes a step of forming a linear pattern 7 intersecting the wiring groove pattern 5 by etching the upper film 6 in a linear or striped state, and a step of forming openings 8 in the intersecting areas of the wiring groove pattern 5 and linear pattern 7 by etching the interlayer insulating films 1 and 2 by using the lower and upper films 3 and 5 as masks. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device having a multilayer wiring structure.

  In recent years, with the miniaturization of semiconductor devices, circuit delay due to an increase in parasitic capacitance of wiring, deterioration of electromigration resistance of fine wiring, and the like have become problems. Therefore, Cu (copper) having lower electrical resistance than aluminum and higher wiring reliability However, it is used as a wiring material for semiconductor devices. As a method for forming a copper wiring, since so-called dry etching of copper is generally difficult, a so-called damascene process is widely employed, but a dual damascene method is particularly promising from the viewpoint of manufacturing cost (for example, Patent Documents). 1). In the dual damascene method, a wiring groove and a via hole (opening) are formed in an interlayer insulating film in a multilayer wiring structure, and a wiring material is buried in the wiring groove and the via hole at the same time, and then chemical mechanical polishing ( Chemical Mechanical Polishing (hereinafter abbreviated as “CMP”) is a method for removing excess wiring material on the interlayer insulating film. Since the wiring material is embedded and the subsequent CMP process is performed once, there is a cost advantage. high.

  Various methods have been proposed as a method for forming wiring grooves and via holes in the dual damascene method. However, after forming the wiring grooves 61 as shown in FIG. The flow is roughly divided into a groove type flow and a tip hole type flow in which the wiring groove 61 is formed after the via hole 62 is formed as shown in FIG. In addition, Sony Corporation's Sachiko Miyata et al. In the Sekizo-type flow at the Advanced Metallization Conference 1999: Asian Session “A Nobel Integration Approach to A method of using an inorganic film (hard mask film) on an interlayer insulating film as announced under the title of “A Nobel Integration Approach to Organic Low-k Dual Damascene Processing” Has also been proposed. In the example of FIG. 15, the barrier etch stopper film 64 is present between the interlayer insulating films 63, but the barrier etch stopper film 64 may not be used.

Japanese Patent Laid-Open No. 10-261707

  By the way, when a semiconductor device having a multi-layer wiring structure is manufactured by a pre-groove type dual damascene method, (1) lower layer wiring → (2) wiring for forming upper layer wiring in a lithography process which is one of the manufacturing processes. Groove → (3) Via holes for connecting the lower layer wiring and the upper layer wiring are formed in this order. At that time, the wiring groove and the via hole of the upper layer wiring are exposed in accordance with the position of the lower layer wiring. Therefore, the formation positions of these wiring trenches and via holes are in an indirect relationship.

Therefore, there is a possibility that a short margin between the wiring pattern and the via pattern cannot be secured in the semiconductor device using the tip groove type dual damascene method. This is because, if the wiring groove and the via hole are in an indirect relationship, the conductive region of the finally formed wiring layer is the logical sum of the pattern regions of the wiring groove and the via hole. This is because the deviation is 2 ^1/2 times that in the case of direct alignment. This is particularly noticeable when a plurality of wiring layers are arranged in parallel at a narrow pitch in a stripe shape. For example, as shown in FIG. 16, the vias are displaced due to the positional deviation between the wiring grooves and the via holes. When the holes are formed, the partition walls 71 between the adjacent wiring grooves are scraped, and as a result, it is possible that the electric breakdown voltage between the wiring layers 72a and 72b cannot be secured.

These should be avoided because it leads to a decrease in reliability and manufacturing yield of a semiconductor device manufactured by the dual damascene method.
Therefore, the present invention can secure a short margin between a wiring pattern and a via pattern even when a semiconductor device is manufactured by a tip-drum type dual damascene method, thereby improving the reliability of the semiconductor device and the manufacturing yield. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can realize improvement and the like.

  The present invention is a semiconductor device manufacturing method devised to achieve the above object. That is, a semiconductor device configured such that an upper layer wiring is laminated on an upper layer wiring via an interlayer insulating film, and the lower layer wiring and the upper layer wiring are electrically connected by a via portion provided in the interlayer insulating film A method of forming a lower layer film on the interlayer insulating film, and a wiring groove for etching the lower layer film in a line shape or a stripe shape to form the upper layer wiring in the lower layer film A step of forming a pattern, a step of forming an upper layer film on the lower layer film on which the wiring groove pattern is formed, and etching the upper layer film in a line shape or a stripe shape to form the wiring groove pattern on the upper layer film. A step of forming a line pattern that intersects the substrate, and etching the interlayer insulating film using the lower layer film on which the wiring groove pattern is formed and the upper layer film on which the line pattern is formed as a mask Forming an opening in a region where the wiring groove pattern and the line pattern intersect in the interlayer insulating film, and embedding a wiring material in the groove portion and the opening of the wiring groove pattern to form the upper layer wiring and the via Forming a portion.

  In the method of manufacturing a semiconductor device according to the above procedure, the wiring groove pattern and the line pattern are formed by etching into a line shape or a stripe shape, respectively. Here, the “line shape” means a substantially rectangular shape whose longitudinal direction is larger than the width direction on a plane. The “striped shape” refers to a state in which a plurality of line-shaped objects are arranged in parallel. An opening is formed in a region where the wiring groove pattern and the line pattern intersect, and an upper layer wiring and a via portion are formed by embedding a wiring material in the opening and the groove portion of the wiring groove pattern. Therefore, since the opening is formed over the entire width of the groove portion of the wiring groove pattern, it is not affected by the alignment between them, that is, even if a slight misalignment occurs between the wiring groove pattern and the line pattern. Thus, a sufficient conduction region between the upper layer wiring and the via portion can be secured. Moreover, since both the wiring groove pattern and the line pattern are formed in a line shape or a stripe shape having a one-dimensional period in the line width direction, it is easy to obtain shape stability. Therefore, it is possible to form fine upper layer wiring and via portions with high dimensional accuracy while facilitating the dimensional controllability of the groove portions and openings of the wiring groove pattern.

  According to the present invention, even a fine upper layer wiring and a via portion can be formed with high dimensional accuracy while ensuring a sufficient conduction region. Even in the case of manufacturing, it is possible to form a wiring pattern with a fine dimension, and it is very suitable for application to manufacturing a highly integrated semiconductor device or the like.

  A method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

  The manufacturing method described in this embodiment is for manufacturing a semiconductor device having a multilayer wiring structure. That is, a method of manufacturing a semiconductor device configured such that an upper layer wiring is laminated on a lower layer wiring via an interlayer insulating film, and the lower layer wiring and the upper layer wiring are electrically connected by a via portion provided in the interlayer insulating film It is. Furthermore, the present invention is for manufacturing a semiconductor device having such a structure by a tip-drum type dual damascene method. That is, (1) lower layer wiring → (2) wiring groove for forming upper layer wiring → (3) via hole for connecting lower layer wiring and upper layer wiring → (4) upper layer wiring and via portion (wiring groove and This is a method for manufacturing a semiconductor device in the case of forming in the order of embedding of wiring material in via holes. Here, the characteristic points of the present invention, specifically, only the steps (2) to (4) described above will be described, and the other steps are substantially the same as those in the prior art, and the description thereof will be omitted.

1 to 7 are schematic views showing an example of an outline of a method for manufacturing a semiconductor device of the present invention.
In the manufacturing method of the present embodiment, first, as shown in FIG. 1A, a first interlayer insulating film 1 and a second interlayer insulating film 2 are formed on a semiconductor substrate (not shown) on which a lower layer wiring is formed. Are formed, a first inorganic film 3 to be a hard mask film is formed thereon, and a second inorganic film 4 to be a lower layer film is further formed thereon. Then, after the second inorganic film 4 is laminated, the second inorganic film 4 is etched into a line shape or a stripe shape by using a lithography technique and a dry etching technique. Thereby, as shown in FIG.1 (b), the line pattern 5 of the line form or stripe form extended in one direction is formed in the 2nd inorganic film | membrane 4. As shown in FIG. This line pattern 5 is for forming an upper layer wiring. Hereinafter, this line pattern is referred to as a “wiring groove pattern”.

  Thereafter, a resist film 6 serving as an upper layer film is formed and laminated on the second inorganic film 4 on which the wiring groove pattern 5 is formed. Further, the resist film 6 is etched into a line shape or a stripe shape in a direction intersecting with the wiring groove pattern 5 by using a lithography technique and a dry etching technique. As a result, as shown in FIG. 1C, a line or stripe line pattern 7 extending in a direction different from the wiring groove pattern 5 is formed on the resist film 6. Hereinafter, this line pattern is simply referred to as “line pattern”.

  These wiring groove pattern 5 and line pattern 7 are formed so as to correspond to the arrangement of via holes to be formed. That is, as shown in FIG. 1D, the region where the wiring groove pattern 5 and the line pattern 7 intersect is assumed to coincide with the formation position of the via hole 8 as will be described in detail later.

  The formation of the interlayer insulating films 1, 2, the inorganic films 3, 4 and the resist film 6 and the formation of the wiring groove pattern 5 and the line pattern 7 may be realized using a known technique. In forming the wiring groove pattern 5 and the line pattern 7, a known dimensional accuracy improvement technique such as a halftone phase shift mask, a Levenson phase shift mask, an assist pattern, or OPC (Optical Proximity Correction) may be applied. Conceivable.

  After the formation of the line pattern 7, as shown in FIG. 1E, the second inorganic film 4 in which the wiring groove pattern 5 is formed and the resist film 6 in which the line pattern 7 is formed are used as a mask. An etching process is performed on the first inorganic film 3. By this etching process, the first inorganic film 3 is removed in a region where the patterns 5 and 7 are overlapped, that is, in a region where the wiring groove pattern 5 and the line pattern 7 intersect. Therefore, after this etching process, the first inorganic film 3 has a pattern (hereinafter referred to as “via pattern”) corresponding to the formation position of a quadrilateral via hole (opening) 8 as shown in FIG. Will be formed.

  After the via pattern is formed on the first inorganic film 3, the second interlayer insulating film 2 is then etched using the first inorganic film 3 mask on which the via pattern is formed. By this etching process, as shown in FIG. 1 (f), the via pattern constituted by the via hole 8 is also transferred to the second interlayer insulating film 2. Note that the resist film 6 has disappeared due to this etching process.

  Thereafter, the first inorganic film 3 is etched using the second inorganic film 4 as a mask. As a result, the wiring groove pattern 5 is transferred to the first inorganic film 3 as shown in FIG. Further, an etching process is performed on the first interlayer insulating film 1 using the first inorganic film 3 in which the wiring groove pattern 5 is formed and the second interlayer insulating film 2 in which the via pattern is formed as a mask. As a result, the via pattern constituted by the via hole 8 is also transferred to the first interlayer insulating film 1 as shown in FIG. After that, the second interlayer insulating film 2 is etched using the first inorganic film 3 on which the wiring groove pattern 5 is formed as a mask. As a result, the wiring groove pattern 5 is also transferred to the second interlayer insulating film 2 as shown in FIG.

  After the via pattern is formed in the first interlayer insulating film 1 and the wiring groove pattern 5 is formed in the second interlayer insulating film 2, the barrier metal is formed on the via hole 8 and the inner wall of the wiring groove constituting each of them. Then, a seed layer is formed, a wiring material 9 made of Cu is embedded in the via hole 8 and in the wiring groove by a plating method, and further etched into the upper portion of the second interlayer insulating film 2 by CMP to remove excess wiring material Remove. As a result, a copper wiring having a dual damascene wiring structure as shown in FIG. 2D is completed.

As described above, in the method of manufacturing the semiconductor device having the dual damascene wiring structure described in the present embodiment, the via hole 8 is formed in the region where the wiring groove pattern 5 and the line pattern 7 intersect, and the via hole 8 and the wiring The wiring material 9 made of Cu is embedded in the groove portion of the groove pattern 5 to form the upper layer wiring and the via portion. For this reason, the via hole 8 is formed over the entire width of the groove portion of the wiring groove pattern 5, so that it is not affected by the alignment between them, that is, the wiring groove pattern 5 and the line pattern 7 are slightly positioned. Even if a shift occurs, a sufficient conduction region between the upper wiring and the via portion can be secured. Moreover, since both the wiring groove pattern 5 and the line pattern 7 are formed in a line shape or a stripe shape having a one-dimensional period in the line width direction, it is easy to obtain shape stability. Therefore, it is possible to form fine upper layer wiring and via portions with high dimensional accuracy while facilitating the dimensional controllability of the groove portions of the wiring groove pattern 5 and the via holes 8.
Therefore, according to the manufacturing method according to the present embodiment, even a fine upper layer wiring and via portion can be formed with high dimensional accuracy while sufficiently securing a conduction region. Even when a semiconductor device having a wiring structure is manufactured, it is possible to form a wiring pattern with a fine dimension, which is very suitable for application to manufacturing a highly integrated semiconductor device or the like.

  Here, the case where the interlayer insulating films 1 and 2 are two layers is taken as an example for ease of processing, but the interlayer insulating film is not necessarily two layers, and may be only one layer. Absent. In that case, since the pattern etching for the interlayer insulating film is a single layer, it is conceivable to control the processing depth so as to stop the etching in the middle of the layer by controlling the time.

  In addition, when an amine component is contained in the interlayer insulating film, if the amine component leaks out, the acid in the resist film 6 may be deactivated, and pattern formation may not be performed properly. It is desirable to form the first inorganic film 3 using the material to be used. For example, a SiN (silicon nitride) film, a TEOS (tetraethoxy silane) film, a SiO (silicon oxide) film, or the like formed by plasma CVD (Chemical Vapor Deposition) technology corresponds to this.

  By the way, in the manufacturing method of this embodiment, the via hole 8 is formed by intersecting the wiring groove pattern 5 and the line pattern 7 so as to overlap each other. Therefore, as shown in FIG. 3A, when the width of the groove portion in the wiring groove pattern 5 is sufficiently larger than the via hole 8a to be formed, the line pattern 7 is formed so as to overlap the wiring groove pattern 5. Thus, as shown in FIG. 3B, the size of the finally formed via hole 8 b becomes substantially equal to the groove width of the wiring groove pattern 5. Thus, if the final via hole 8b is larger than the via hole 8a to be formed, that is, larger than the necessary size, there is a risk of short-circuiting with the lower layer wiring that should not be conducted. Should be avoided. From this, when the via hole 8 is formed by overlapping the line pattern 7 on the wiring groove pattern 5, it is considered that the wiring groove pattern 5 and the line pattern 7 are described as follows.

  For example, as shown in FIG. 4A, the distance W between the edge position of the via hole 8a to be formed and the edge position of the groove part in the wiring groove pattern 5 is the minimum width dimension of the groove part that can be formed. If it is less than twice, as shown in FIG. 4B, the groove width (shape) of the wiring groove pattern 5 is set to the wiring groove pattern so that the edge position of the groove portion overlaps the edge position of the via hole. 5 is corrected at the design stage. In this way, even when the via pattern 8 is formed by overlapping the line pattern 7 on the wiring groove pattern 5, it is finally formed in order to ensure a sufficient conduction region without being affected by the positional deviation. It is possible to prevent the occurrence of a short-circuit due to the enlarged via hole 8b.

  On the other hand, for example, as shown in FIG. 5A, the distance W between the edge position of the via hole 8a to be formed and the edge position of the groove portion in the wiring groove pattern 5 is the minimum width dimension of the groove portion that can be formed. If it is more than twice, as shown in FIG. 5 (b), the wiring groove pattern 5 is designed at the design stage so as to form the pillar pattern 10 made of an insulating film in the groove portion of the wiring groove pattern 5. To fix it. Furthermore, the length of the line pattern 7 is made not to exceed the outer edge position of the pillar pattern 10. In this way, even if the via hole 8 is formed by overlapping the line pattern 7 on the wiring groove pattern 5 in order to ensure a sufficient conduction region without being affected by the positional deviation, it is finally formed. It is possible to prevent the occurrence of a short-circuit due to the enlarged via hole 8b.

  However, the purpose of forming the via hole 8 by superimposing the line pattern 7 on the wiring groove pattern 5 is to prevent a short circuit due to a positional shift between the adjacent wiring and the via portion, as already described. Therefore, as shown in FIG. 6, a plurality of wiring layers are not arranged in parallel at a narrow pitch, but in a place where there is no possibility of short-circuiting even if a slight misalignment occurs, a method similar to the conventional method should be used. It may be. That is, even when processing is performed on the same layer, depending on the wiring groove pattern and the shape (size) of the via hole to be formed, the manufacturing method described in the present embodiment, and the manufacturing method similar to the conventional one, It is conceivable to properly use these.

  Even in the case where via holes are formed by the same method as in the prior art, a line or stripe line pattern 7 may be used depending on the formation pattern of the lower layer wiring. In that case, as shown in FIG. 7A, the line pattern 7 is arranged so that the direction in which the lower layer wiring 11 extends and the longitudinal direction thereof coincide. In this way, as shown in FIG. 7B, the finally formed via hole 8b becomes larger than the design size, but even if a slight misalignment occurs, the lower layer wiring 11 extends in the extending direction. Since it is made larger, no short circuit occurs.

Next, a method for manufacturing a semiconductor device according to the present invention will be described in detail with a specific example with reference to FIGS.
In Example 1 described as the first specific example, first, as shown in FIG. 8A, a SiN film 23 is formed on a semiconductor substrate 22 on which a first-layer copper wiring 21 to be a lower-layer wiring is formed. The SiO film 24 to be the first interlayer insulating film 1 is formed to a thickness of 350 nm, and then the polyallyl ether organic polymer film 25 to be the second interlayer insulating film 2 is 150 nm. The film is formed with a thickness. Then, on the organic polymer film 25, a SiO film 26 to be the first inorganic film 3 is formed with a thickness of 180 nm, and a SiN film 27 to be the second inorganic film 4 is formed with a thickness of 100 nm.

  Thereafter, as shown in FIG. 8B, an organic antireflection film 28 is applied on the SiN film 27 with a thickness of 70 nm, and a positive chemically amplified resist film 29 is applied with a thickness of 400 nm. Then, the wiring groove pattern is exposed and transferred to the positive chemically amplified resist film 29 by using a KrF excimer laser lithography technique. As a result, the portion of the positive chemically amplified resist film 29 that becomes the wiring groove is removed by development, and the wiring groove pattern 5 is formed. The lithography conditions at this time can be considered as follows.

Exposure apparatus: KrF excimer laser reduction projection type scanner (reduction ratio 1/4, NA = 0.75)
Illumination shape: Ring zone (σin / σout = 0.50 / 0.75)
Alignment: Match lower layer wiring Resist: Acetal positive chemical amplification resist (film thickness 400nm)
Reticle: Cr reticle Developer: TMAH (Tetramethyl ammonium hydroxide) 2.38%

  A part of the design data of the wiring groove pattern 5 to be exposed and transferred at this time is shown in FIG. As shown in the figure, the minimum width of the wiring is 160 nm, and the minimum space between the wirings is 160 nm. Note that the wiring groove pattern 5 in the illustrated example is one in which a plurality of line-shaped wiring grooves extending in one direction including the formation region of the via hole 8 are regularly arranged in parallel.

Thereafter, as shown in FIG. 8D, reflection is performed using an ECR (electron cyclotron resonance) plasma etching apparatus and an etching gas (CHF ₃ / Ar / O ₂ ) using the positive chemically amplified resist film 29 as a mask. The prevention film 28 and the SiN film 27 are etched to remove the positive chemically amplified resist film 29. As a result, the wiring groove pattern 5 is formed in the SiN film 27.

  Then, as shown in FIG. 8E, an organic antireflection film 30 is applied on the SiN film 27 on which the wiring groove pattern 5 is formed (thickness 140 nm from the SiO film 26). A chemically amplified resist film 31 is applied to a thickness of 400 nm, and a stripe-like line pattern extending in a direction perpendicular to the wiring groove pattern 5 is exposed and transferred onto the positive chemically amplified resist film 31. As a result, the line pattern 7 is formed on the positive chemically amplified resist film 31. The lithography conditions at this time can be considered as follows.

Exposure apparatus: KrF excimer laser reduction projection scanner (reduction ratio 1/4, NA = 0.75, σ = 0.70)
Alignment: Match lower layer wiring Resist: Acetal positive chemical amplification resist (film thickness 400nm)
Reticle: Cr reticle Developer: TMAH 2.38%

  Further, FIG. 8F shows the layout of the line pattern 7 to be exposed and transferred at this time. As shown in the figure, the line pattern 7 is formed by regularly arranging a plurality of line-shaped wiring grooves extending in one direction including the formation region of the via hole 8, and in the formation region of the via hole 8. It is orthogonal to the wiring groove pattern 5.

  After the formation of the line pattern 7, as shown in FIG. 9A, the antireflection film 30 and the SiO film 26 are etched using the positive chemically amplified resist film 31 as a mask. The etching conditions at this time can be considered as follows.

Etching apparatus: ECR plasma etcher Antireflection film etching: Ar / O ₂ , 30% over SiO film etching: C5F8 / Ar / O ₂ , 30% over

  Thereafter, as shown in FIG. 9B, the organic polymer film 25 is etched using ammonia gas. By etching at this time, the conditions of the positive chemically amplified resist film 31 and the antireflection film 30 are also removed at the same time. Further, as shown in FIG. 9C, the SiO film 24 is etched. As a result, a via pattern constituted by a planar quadrangular via hole 8 is formed in the SiO film 24. Further, the wiring groove pattern 5 is formed on the SiO film 26 using the SiN film 27 as a mask. Next, as shown in FIG. 9D, the organic polymer film 25 is etched using the SiN film 27 as a mask, and the SiN film 23 is further etched as shown in FIG. 9E. At this time, a part of the upper surface of the SiN film 27 is etched back.

  Then, as shown in FIG. 9 (f), a Ta (tantalum) film (not shown) as a barrier metal is formed to a thickness of 25 nm on the inner wall of the etched portion, and a Cu seed film (however, (Not shown) is formed, Cu32 is electrolytically embedded in the formed via hole 8 and the groove portion of the wiring groove pattern 5, and the upper surface thereof is polished to the middle of the SiO film 26 by a CMP technique, and a SiN film is used as a cap film. 33 is deposited to a thickness of 70 nm. Thereby, the copper wiring (upper layer wiring) and the copper via plug (via portion) are formed at the same time.

Here, in the procedure composed of the steps as described above, a case will be considered in which a positional deviation occurs in the line pattern 7 for forming the via hole 8 in the lithography step described with reference to FIG.
For example, as shown in FIG. 10A, when the position of the line pattern 7 is shifted along its longitudinal direction, that is, when it is shifted in the width direction of the wiring groove pattern 5 orthogonal to the line pattern 7, Since the via hole 8 is formed at the position where the line pattern 7 and the wiring groove pattern 5 overlap, the via hole 8 is formed at a desired position (position as designed) without being affected by the positional deviation of the line pattern 7. Will be.
On the other hand, as shown in FIG. 10B, when the position of the line pattern 7 is shifted in the width direction, that is, when the position is shifted along the longitudinal direction of the wiring groove pattern 5 orthogonal to the line pattern 7, The position where the via hole 8 is formed also moves by the amount shifted. However, since the moving direction is the longitudinal direction of the wiring groove pattern 5 and not the width direction, even if a plurality of wiring layers are arranged in parallel at a narrow pitch, the via hole 8 (via portion) is adjacent to the same layer. Never get close to the wiring. Therefore, the electric withstand voltage between the wiring layers can be kept sufficiently, and there is no problem as long as the positional deviation amount is within an allowable range.
That is, in any of the cases shown in FIGS. 10A and 10B, the via hole 8 and the wiring groove pattern 5 are in the indirect alignment relationship, but the via hole 8 is adjacent to the same layer. Therefore, the electric withstand voltage between the wiring layers can be sufficiently maintained.

11 and 12 are plan views showing a specific example of the pattern layout.
The shape and size of the wiring groove pattern and the line pattern may be determined in consideration of the position and shape of the via hole to be formed and the lower layer wiring. Specifically, as shown in FIG. 11, not only is the wiring groove pattern 5 and the line pattern 7 intersected at the formation position of the via hole 8, but the groove width of the wiring groove pattern 5 is set to the via hole 8. It is conceivable that the pillar pattern 10 is generated in the groove portion of the wiring groove pattern 5, or the longitudinal direction of the line pattern 7 is made to coincide with the direction in which the lower layer wiring 11 extends.
FIG. 12 shows a case where the formation position of the line pattern 7 is displaced by 50 nm on the upper side and 50 nm on the right side with respect to the formation position of the wiring groove pattern 5. Even if such misalignment occurs, if the shape and size of the wiring groove pattern 5 and the line pattern 7 are appropriately determined, and the via holes 8 are formed so as to overlap with each other, the FIG. As shown in FIG. 12, the formed via portion 12 does not protrude from the wiring groove pattern 5, and it is possible to prevent occurrence of a short circuit due to misalignment.

Next, a second specific example, Example 2, will be described with reference to FIGS. In the first embodiment described above, the case where the interlayer insulating film is a two-layered structure of the SiO film 24 and the organic polymer film 25 is described as an example. However, here, a case where only one layer is formed will be described.
In Example 2, first, as shown in FIG. 13A, a SiCN (carbon-doped silicon nitride film) film 43 is formed to a thickness of 50 nm on a semiconductor substrate 42 on which a first-layer copper wiring 41 serving as a lower wiring is formed. Then, a SiOCH film 44 as a low dielectric constant interlayer insulating film is formed with a thickness of 300 nm. Then, a TEOS film 45 to be the first inorganic film 3 is formed on the SiOCH film 44 with a thickness of 80 nm, and a SiCN film 46 to be the second inorganic film 4 is formed with a thickness of 50 nm.

  Thereafter, as shown in FIG. 13B, an organic antireflection film 47 is applied on the SiCN film 46 to a thickness of 80 nm, and a positive chemically amplified resist film 48 is applied to a thickness of 400 nm. Then, the wiring groove pattern is exposed and transferred to the positive chemically amplified resist film 48 using ArF excimer laser lithography. As a result, the portion of the positive chemically amplified resist film 48 that becomes the wiring groove is removed by development, and the wiring groove pattern 5 is formed. The lithography conditions at this time can be considered as follows.

Exposure device: ArF excimer laser reduction projection scanner (reduction ratio 1/4)
Exposure wavelength: 193nm
Image side numerical aperture of projection lens: 0.80
Numerical aperture on the illumination side of the projection lens: 0.75
Illumination shape: Ring zone (inner radius / outer radius = 0.50 / 0.75)
Alignment: Match lower layer wiring Mask: Halftone phase shift mask (background transmittance 6%)
Resist: Acrylic positive chemically amplified resist (thickness 250 nm)
Antireflection film: Organic antireflection film (80 nm thickness)
Developer: TMAH 2.38%

  FIG. 13C shows part of the design data of the wiring groove pattern 5 that is exposed and transferred at this time. As shown in the figure, the minimum width of the wiring is 100 nm, and the minimum space between the wirings is 100 nm. Note that the wiring groove pattern 5 in the illustrated example is one in which a plurality of line-shaped wiring grooves extending in one direction including the formation region of the via hole 8 are regularly arranged in parallel.

Thereafter, as shown in FIG. 13 (d), using the positive chemical amplification resist film 48 as a mask, using an ECR plasma etching apparatus and an etching gas (CHF ₃ / Ar / O ₂ ), the antireflection film 47 and the SiCN The film 46 is etched, and the positive chemically amplified resist film 48 is removed. As a result, the wiring groove pattern 5 is formed in the SiCN film 46.

  Then, as shown in FIG. 13E, a novolac resin film 49 is applied with a thickness of 350 nm on the SiCN film 46 on which the wiring groove pattern 5 is formed, and an SOG (Spin On Glass) film 50 is further formed with a thickness of 100 nm. Finally, an acrylic chemical amplification type positive resist film 51 having a thickness of 200 nm is applied thereon. Then, the stripe-shaped line pattern 7 extending in the direction orthogonal to the wiring groove pattern 5 is exposed and transferred onto the positive resist film 51. As a result, the line pattern 7 is formed on the positive resist film 51. The lithography conditions at this time can be considered as follows.

Exposure device: ArF excimer laser reduction projection scanner (reduction ratio 1/4)
Exposure wavelength: 193nm
Image side numerical aperture of projection lens: 0.80
The numerical aperture on the illumination side of the projection lens: 0.70
Alignment: Match lower layer wiring Mask: Halftone phase shift mask (background transmittance 6%)
Resist: Acrylic positive chemical amplification resist (thickness 200 nm)
Developer: TMAH 2.38%

  FIG. 13F shows the layout of the line pattern 7 to be exposed and transferred at this time. As shown in the figure, the line pattern 7 is formed by regularly arranging a plurality of line-shaped wiring grooves extending in one direction including the formation region of the via hole 8, and in the formation region of the via hole 8. It is orthogonal to the wiring groove pattern 5.

After the formation of the line pattern 7, as shown in FIG. 14A, the SOG film 50 is etched using C ₅ F ₈ / Ar / O ₂ gas using the positive resist film 51 as a mask. Further, the novolac resin film 49 is etched using Ar / O ₂ gas with the SOG film 50 as a mask. By this etching, the positive resist film 51 is lost. Then, using the novolac resin film 49 and the SiCN film 46 as a mask, the TEOS film 45 is etched using C ₅ F ₈ / Ar / O ₂ gas. As a result, a planar quadrangular via hole 8 is formed in the TEOS film 45 in a region where the wiring groove pattern 5 and the line pattern 7 overlap.

  Subsequently, using the novolac resin film 49 and the SiCN film 46 as a mask, the SiOCH film 44 is etched using trimethylsilane gas. Then, when the novolac resin film 49 is removed, a via pattern constituted by the via holes 8 is formed in the SiOCH film 44 as shown in FIG.

  Thereafter, as shown in FIG. 14C, the TEOS film 45 is etched using the SiCN film 46 as a mask, and the wiring groove pattern 5 is transferred to the TEOS film 45. Then, as shown in FIG. 14D, using the SiCN film 46 as a mask, the SiOCH film 44 is etched to half the thickness, and the wiring groove pattern 5 is transferred. Further, as shown in FIG. 14E, the underlying SiCN film 43 is also etched. At this time, the upper SiCN film 46 is etched back.

  Then, as shown in FIG. 14 (f), a Ta film (not shown) as a barrier metal is formed to a thickness of 20 nm on the inner wall of the etched portion, and further a Cu seed film (not shown). Cu52 is electrolytically plated and buried in the groove portions of the formed via hole 8 and wiring groove pattern 5, the upper surface thereof is polished partway through the TEOS film 45 by CMP technology, and the SiCN film 53 is formed as a cap film by 50 nm. The film is formed with a thickness. Thereby, the copper wiring (upper layer wiring) and the copper via plug (via portion) are formed at the same time.

  Even in the procedure consisting of the above steps, as in the case of the first embodiment, the via hole 8 and the wiring groove pattern 5 are in the same layer adjacent to each other even though the via hole 8 and the wiring groove pattern 5 are in an indirect alignment relationship. Since it does not approach the wiring, the electric withstand voltage between the wiring layers can be maintained sufficiently. In other words, the shape and size of the wiring groove pattern 5 and the line pattern 7 are appropriately determined, and the via holes 8 are formed so as to intersect with each other so that the line pattern 7 is displaced. However, the formed via hole 8 does not protrude from the wiring groove pattern 5, and it is possible to prevent occurrence of a short circuit due to misalignment.

  In addition, although Example 1 and 2 mentioned above demonstrated in detail, giving the Example of this invention, this invention is limited to these Examples (especially film-forming material, its film thickness, etc.). It goes without saying that it is not a thing.

It is a schematic diagram (the 1) which shows an example of the outline | summary of the manufacturing method of the semiconductor device of this invention. It is a schematic diagram (the 2) which shows an example of the outline | summary of the manufacturing method of the semiconductor device of this invention. It is a schematic diagram (the 3) which shows an example of the outline | summary of the manufacturing method of the semiconductor device of this invention. It is a schematic diagram (the 4) which shows an example of the outline | summary of the manufacturing method of the semiconductor device of this invention. FIG. 6 is a schematic diagram (part 5) illustrating an example of an outline of a method for manufacturing a semiconductor device of the present invention. It is a schematic diagram (the 6) which shows an example of the outline | summary of the manufacturing method of the semiconductor device of this invention. It is a schematic diagram (the 7) which shows an example of the outline | summary of the manufacturing method of the semiconductor device of this invention. It is explanatory drawing (the 1) which shows Example 1 of this invention concretely. It is explanatory drawing (the 2) which shows Example 1 of this invention concretely. It is explanatory drawing (the 3) which shows Example 1 of this invention concretely. It is a top view (the 1) which shows one specific example of the pattern layout to which this invention is applied. It is a top view (the 2) which shows a specific example of the pattern layout to which this invention is applied. It is explanatory drawing (the 1) which shows Example 2 of this invention concretely. It is explanatory drawing (the 2) which shows Example 2 of this invention concretely. It is explanatory drawing which shows the outline | summary of the general dual damascene method. It is explanatory drawing which shows the trouble in the dual damascene method by the flow of the conventional leading groove type.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... 1st interlayer insulation film, 2 ... 2nd interlayer insulation film, 3 ... 1st inorganic film (hard mask film) 4 ... 2nd inorganic film (lower layer film), 5 ... Wiring groove pattern, 6 ... Resist film (upper layer film), 7 ... line pattern, 8 ... via hole, 9 ... wiring material, 10 ... pillar pattern, 11 ... lower layer wiring

Claims (4)

Manufacturing of a semiconductor device configured such that an upper layer wiring is laminated on a lower layer wiring through an interlayer insulating film, and the lower layer wiring and the upper layer wiring are electrically connected by a via portion provided in the interlayer insulating film A method,
Forming a lower layer film on the interlayer insulating film;
Etching the lower layer film in a line or stripe form to form a wiring groove pattern for forming the upper layer wiring in the lower layer film;
Forming an upper layer film on the lower layer film on which the wiring groove pattern is formed;
Etching the upper layer film in a line or stripe form to form a line pattern intersecting the wiring groove pattern in the upper layer film; and
A region where the wiring groove pattern of the interlayer insulating film intersects the line pattern by etching the interlayer insulating film using the lower layer film on which the wiring groove pattern is formed and the upper layer film on which the line pattern is formed as a mask Forming an opening in
A step of embedding a wiring material in the groove and the opening of the wiring groove pattern to form the upper layer wiring and the via portion. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a groove width of the wiring groove pattern is set so that an edge position of a groove portion of the wiring groove pattern overlaps with an edge position of an opening to be formed. The method for manufacturing a semiconductor device according to claim 1, wherein the wiring groove pattern includes a pillar pattern disposed in a groove portion of the wiring groove pattern. The method of manufacturing a semiconductor device according to claim 1, wherein the line pattern is formed so that a longitudinal direction thereof coincides with a direction in which the lower layer wiring extends.