US20080197494A1 - Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same - Google Patents
Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same Download PDFInfo
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- US20080197494A1 US20080197494A1 US12/068,712 US6871208A US2008197494A1 US 20080197494 A1 US20080197494 A1 US 20080197494A1 US 6871208 A US6871208 A US 6871208A US 2008197494 A1 US2008197494 A1 US 2008197494A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
- FIGS. 8A and 8B show a sectional view and a plan view, respectively, of a semiconductor device of a related art.
- a lower-layer interconnect 102 and an upper-layer interconnect 104 are connected by a via material or a via wire 106 (thereafter it is simply called a via).
- the via 106 is buried in a via hole.
- the via 106 is in contact with an end portion of the upper-layer interconnect 104 .
- FIGS. 8A and 8B only the interconnects and the via hole are shown and insulating films on the periphery of the interconnects and the via are omitted.
- the upper-layer interconnect 104 and the via 106 are formed by the dual damascene process. That is, after the formation of a trench for the upper-layer interconnect 104 and a hole for the via 106 by etching, the upper-layer interconnect 104 and the via 106 are formed by burying copper in the trench and the hole.
- the region where the via 106 is present is indicated by hatch lines.
- the via 106 has the shape of a square as plan viewed.
- Patent Documents 1 and 2 can be mentioned as related arts.
- Patent Document 1 Japanese Patent Laid-Open No. 2005-327898
- Patent Document 2 Japanese Patent Laid-Open No. 2002-124575
- FIG. 9A is an SEM photograph (a plan view) showing the appearance of upper-layer interconnects and via when there is scarcely any positional displacement.
- FIG. 9B is an SEM photograph showing the appearance of upper-layer interconnects and via when there is a positional displacement of approximately 20 nm.
- the interconnect width and interconnect intervals of the upper-layer interconnects are both approximately 90 nm.
- the length of the upper-layer interconnect is approximately 330 nm.
- the positional relationship between the upper-layer interconnects 112 and the via 114 in these photographs is schematically shown in FIG. 10 .
- FIG. 11 is an SEM photograph (a sectional view) showing the appearance of the void 118 occurring within the via 114 in the vicinity of a lower-layer interconnect 116 .
- a semiconductor device has an interconnect and a via material.
- the via material is provided under the interconnect and is in contact with an end portion of the interconnect.
- the interconnect and the via are made of copper as one piece.
- the via material has a top surface coupled to a bottom surface of the interconnect. Top surface has a first length parallel with a longitudinal direction of the interconnect and a second length parallel with a direction perpendicular to the longitudinal direction, and the first length is larger than the second length.
- the via material is formed so as to be elongated in a longitudinal direction of the interconnect. As a result of this, the area of a region where the via and the interconnect overlap is expanded. Therefore, during manufacturing it is possible to ensure a large margin for the relative positional displacement between the trench for the first interconnect and the hole for the via material.
- a method of manufacturing a semiconductor device includes forming, by the dual damascene process, an interconnect and a via material, the via material being provided under the first interconnect and being in contact with an end of the interconnect.
- the via material is formed to comprise a first length along with a longitudinal direction of the interconnect and a second length along with a direction perpendicular to the longitudinal direction and a maximum length of the first length is larger than a maximum length of the second length.
- This manufacturing method can ensure the same effect as described just before.
- a semiconductor device having high reliability and a manufacturing method of such semiconductor device are realized.
- FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention
- FIG. 2 is a plan view showing interconnects and a via hole in FIG. 1 ;
- FIGS. 3A to 3L are process drawings showing an embodiment of a manufacturing method of a semiconductor device according to the present invention.
- FIG. 4 is a plan view showing a comparative example of the embodiment
- FIG. 5 is a plan view to explain a modification of the embodiment
- FIG. 6 is a plan view to explain a modification of the embodiment
- FIG. 7 is a plan view to explain a modification of the embodiment.
- FIGS. 8A and 8B are a sectional view and a plan view, respectively, of a semiconductor device of a related art
- FIGS. 9A and 9B are SEM photographs to explain a problem of the related art.
- FIG. 10 is a plan view to explain a problem of the related art.
- FIG. 11 is an SEM photograph to explain a problem of the related art.
- FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.
- a semiconductor device 1 is provided with an interconnect 10 (a first interconnect) and a via 20 .
- An interconnection or an interconnect wiring can be used as the interconnect.
- the interconnect 10 is an M2 interconnect, i.e., an interconnect of the second layer from below in the semiconductor device 1 .
- the via 20 is provided under the interconnect 10 and is in contact with an end portion of the interconnect 10 .
- the interconnect 10 and the via 20 have a dual damascene structure. That is, the interconnect 10 and the via 20 are made of copper as one piece. A barrier metal film 52 is provided so as to collectively cover the interconnect 10 and the via 20 . The interconnect 10 and the via 20 are formed in an interlayer dielectric film 46 .
- An interconnect 30 (a second interconnect) is provided under the via 20 .
- the interconnect 30 is an M1 interconnect, i.e., an interconnect of the lowest layer in the semiconductor device 1 .
- the interconnect 30 is connected to the interconnect 10 via the via 20 .
- a barrier metal film 54 is provided so as to cover this interconnect 30 .
- the interconnect 30 is formed in an interlayer dielectric film 44 .
- the interlayer dielectric film 44 is formed on a semiconductor substrate 42 .
- the semiconductor substrate 42 is for example a silicon substrate.
- Between the interlayer dielectric film 44 and the interlayer dielectric film 46 is provided an etching stopper film 48 .
- the etching stopper film 48 is for example an SiCN film.
- FIG. 2 is a plan view showing the interconnects 10 , 30 and the via 20 in FIG. 1 .
- FIG. 1 is an A-A′ sectional view of FIG. 2 .
- an end surface of the via 20 on the interconnect 10 side is indicated by hatch lines.
- a maximum length d 1 in a longitudinal direction (a transverse direction in FIG. 2 ) of the interconnect 10 is larger than a maximum length d 2 in a direction perpendicular to the longitudinal direction.
- the maximum length d 2 is substantially equal to the width of the interconnect 10 .
- FIG. 2 shows an ideal positional relationship between the interconnect 10 and the via 20 , i.e., a positional relationship obtained when there is no positional displacement.
- the above-described end surface of the via 20 has the shape of a rectangle having a long side parallel to the longitudinal direction of the interconnect 10 . Therefore, the maximum length d 1 and the maximum length d 2 are equal to the length, respectively, of the long side and short side of the rectangle.
- the shape of the section of the via 20 parallel to the above-described end surface is substantially constant. That is, the sectional shape of the via 20 is substantially constant regardless of the height from the semiconductor substrate 42 .
- This method includes a step of forming the interconnect 10 and the via 20 by the dual damascene process.
- the interlayer dielectric film 44 is formed on the semiconductor substrate 42 ( FIG. 3A ).
- the resist film 62 is patterned.
- a trench 32 for the interconnect 30 is formed ( FIG. 3A ).
- a copper film 30 a is formed so as to bury the trench 32 ( FIG. 3C ).
- the barrier metal film 54 and copper film 30 a that are present outside the trench 32 are removed by CMP (chemical mechanical polishing).
- the interconnect 30 is formed ( FIG. 3D ).
- the interlayer dielectric film 46 is formed above the interlayer dielectric film 44 via the etching stopper layer 48 ( FIG. 3E ).
- a hole 22 for the via 20 is formed by selectively etching a prescribed region of the interlayer dielectric film 46 ( FIG. 3F ).
- the hole 22 for the via 20 is formed before the formation of a trench for the interconnect 10 . That is, the via-first process is adopted.
- a BARC (bottom anti-reflection coating) film 64 is formed so as to bury the hole 22 ( FIG. 3G ).
- the resist film 66 is patterned ( FIG. 3H ).
- a trench 12 for the interconnect 10 is formed by etching the interlayer dielectric film 46 using this resist film 66 as a mask, and thereafter the resist film 66 is removed ( FIG. 3I ).
- the BARC film 64 remaining within the hole 22 is removed ( FIG. 6A ). Furthermore, the etching stopper film 48 present in the bottom portion of the hole 22 is removed by etching ( FIG. 3K ). Subsequently, after the formation of the barrier metal film 52 on the whole surface of the interlayer dielectric film 46 , a copper film 10 a is formed so as to collectively bury the trench 12 and the hole 22 ( FIG. 3L ). After that, a barrier metal film 52 and the copper film 10 a that are present outside the trench 12 and the hole 22 are removed by CMP. As a result of this, the interconnect 10 and the via 20 are simultaneously formed and the semiconductor device 1 shown in FIG. 1 is obtained.
- the end surface of the via 20 on the interconnect 10 side is formed so as to be elongated in the longitudinal direction of the interconnect 10 .
- the area of a region where the via 20 and the interconnect 10 overlap is expanded. Therefore, during manufacturing it is possible to ensure a large margin for a relative positional displacement between the trench 12 for the interconnect 10 and the hole 22 for the via 20 . For this reason, the alignment manufacturing limit of dual damascene is improved.
- the alignment manufacturing limit refers to an upper limit value of the amount of positional displacement that is allowed for ensuring a necessary yield. According to this embodiment, the semiconductor device 1 having high reliability and a manufacturing method of thereof are realized.
- the maximum length d 1 (see FIG. 2 ) of the via 20 be not less than twice the maximum length d 2 .
- the area of the via 20 as plan viewed increases by the amount of elongation of the via 20 in the longitudinal direction of the interconnect 10 .
- the quantity of light that comes in from the mask of the via 20 during exposure increases and, therefore, a lithography margin expands.
- the via 20 is in contact with an end portion of the interconnect 10 .
- Even a slight positional displacement results in a reduction of the area of a region where the via 20 and the interconnect 10 overlap. Therefore, the usefulness of this embodiment that enables a large margin for positional displacement to be ensured becomes especially high.
- the interconnect 10 and the via 20 are made of copper as one piece. In this case, electric resistance can be reduced compared to a case where a barrier metal film is interposed between the two layers.
- the maximum length d 2 of the above-described end surface of the via 20 is substantially equal to the width of the interconnect 10 . For this reason, when there is no positional displacement, the whole via 20 is to be accommodated under the interconnect 10 . As a result of this, it is possible to ensure a sufficient gap between an interconnect in close proximity to the interconnect 10 and the via 20 .
- Patent Document 1 discloses a via hole having a protrusion. Concretely, a protrusion is formed in an upper part of the via hole. For this reason, in this via hole, the upper portion provided with the via hole and other portions have different sectional shapes. Therefore, in forming this via hole, it is necessary to perform etching by two stages, resulting in an increase in the number of manufacturing steps. In addition, it becomes necessary to perform the control of etching depth and hence process control becomes difficult. Moreover, because it becomes necessary to use two masks for this etching, the cost of manufacturing also rises. In this respect, according to this embodiment, it is possible to form the hole 22 for the via 20 by single-stage etching, and therefore, these problems can be avoided.
- the interconnect 10 and the via 20 are formed by the via-first process.
- the via-first process that is, when the trench 12 for the interconnect 10 is formed before the formation of the hole 22 for the via 20 , it is difficult to pattern the resist film for the via 20 as desired. This is because the resist film is formed on a rough surface (the bottom surface of the trench 12 ).
- the via-first process the patterning of the resist film for the via 20 becomes easy and, therefore, the via 20 can be satisfactorily formed.
- the above-described problem i.e., the problem of the burying imperfection of copper in the dual damascene process becomes more conspicuous. Therefore, the usefulness of this embodiment that enables a large margin for positional displacement to be ensured becomes especially high. According to this embodiment, even in the 65-nm generation and beyond, it is possible to satisfactorily perform the formation of the interconnect 10 and the via 20 by the dual damascene process without the introduction of an expensive lithography device.
- the present invention is not limited to the above-described embodiment but various modifications are possible.
- the case where the planar shape of the interconnects 10 , 30 and the via 20 is rectangular was shown as an example.
- the planar shape of these may also be shapes other than the rectangle.
- the maximum length d 1 in the longitudinal direction of the interconnect 10 and the maximum length d 2 in a direction perpendicular to this longitudinal direction are defined as follows. That is, as shown in FIG. 8 , the lengths of the sides of a rectangle capable of including the above-described end surface of the via 20 , which has the smallest area (the rectangle R 1 ), become the above-described maximum length d 1 , d 2 . However, it is defined that the rectangle R 1 has a side parallel to the longitudinal direction (the transverse direction in FIG. 5 ) of the interconnect 10 , and the length of a side parallel to the longitudinal direction is the maximum length d 1 and the length of a side perpendicular to the longitudinal direction is the maximum length d 2 .
- the via 20 is in contact with the end portion of the interconnect 30 was shown as an example. As shown in FIG. 7 , however, the via 20 may also be in contact with the middle part of the interconnect 30 (a portion other than the end portion).
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Abstract
A semiconductor device has an interconnect and a via material. The via material is provided under the interconnect and is in contact with an end portion of the interconnect. The interconnect and the via are made of copper as one piece. The via material has a top surface coupled to a bottom surface of the interconnect. The top surface has a first portion parallel with a longitudinal direction of the interconnect and a second portion parallel with a direction perpendicular to the longitudinal direction, and the first portion is larger than the second portion.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
- 2. Description of Related Art
-
FIGS. 8A and 8B show a sectional view and a plan view, respectively, of a semiconductor device of a related art. In asemiconductor device 100, a lower-layer interconnect 102 and an upper-layer interconnect 104 are connected by a via material or a via wire 106 (thereafter it is simply called a via). Thevia 106 is buried in a via hole. Thevia 106 is in contact with an end portion of the upper-layer interconnect 104. Incidentally, inFIGS. 8A and 8B , only the interconnects and the via hole are shown and insulating films on the periphery of the interconnects and the via are omitted. - The upper-
layer interconnect 104 and thevia 106 are formed by the dual damascene process. That is, after the formation of a trench for the upper-layer interconnect 104 and a hole for thevia 106 by etching, the upper-layer interconnect 104 and thevia 106 are formed by burying copper in the trench and the hole. - In
FIG. 8B , the region where thevia 106 is present is indicated by hatch lines. As is apparent from this figure, thevia 106 has the shape of a square as plan viewed. - Incidentally,
Patent Documents 1 and 2 can be mentioned as related arts. - [Patent Document 1] Japanese Patent Laid-Open No. 2005-327898
- [Patent Document 2] Japanese Patent Laid-Open No. 2002-124575
- In the dual damascene process, however, during etching there may sometimes occur a relative positional displacement between a trench for an interconnect and a hole for a via, reducing the area of a region where the two overlap. If the area of this region is too small, a burying imperfection occurs when the copper is buried in the above-described trench and hole.
-
FIG. 9A is an SEM photograph (a plan view) showing the appearance of upper-layer interconnects and via when there is scarcely any positional displacement. On the other hand,FIG. 9B is an SEM photograph showing the appearance of upper-layer interconnects and via when there is a positional displacement of approximately 20 nm. The interconnect width and interconnect intervals of the upper-layer interconnects are both approximately 90 nm. The length of the upper-layer interconnect is approximately 330 nm. The positional relationship between the upper-layer interconnects 112 and thevia 114 in these photographs is schematically shown inFIG. 10 . - If there is a positional displacement as shown in
FIG. 9B , then avoid 118 due to a burying imperfection of copper may sometimes occur as shown inFIG. 11 .FIG. 11 is an SEM photograph (a sectional view) showing the appearance of thevoid 118 occurring within thevia 114 in the vicinity of a lower-layer interconnect 116. - A semiconductor device has an interconnect and a via material. The via material is provided under the interconnect and is in contact with an end portion of the interconnect. The interconnect and the via are made of copper as one piece. The via material has a top surface coupled to a bottom surface of the interconnect. Top surface has a first length parallel with a longitudinal direction of the interconnect and a second length parallel with a direction perpendicular to the longitudinal direction, and the first length is larger than the second length.
- In this semiconductor device, the via material is formed so as to be elongated in a longitudinal direction of the interconnect. As a result of this, the area of a region where the via and the interconnect overlap is expanded. Therefore, during manufacturing it is possible to ensure a large margin for the relative positional displacement between the trench for the first interconnect and the hole for the via material.
- A method of manufacturing a semiconductor device, includes forming, by the dual damascene process, an interconnect and a via material, the via material being provided under the first interconnect and being in contact with an end of the interconnect. The via material is formed to comprise a first length along with a longitudinal direction of the interconnect and a second length along with a direction perpendicular to the longitudinal direction and a maximum length of the first length is larger than a maximum length of the second length.
- This manufacturing method can ensure the same effect as described just before.
- According to the present invention, a semiconductor device having high reliability and a manufacturing method of such semiconductor device are realized.
- The above and other exemplary aspects, advantages and features of the present invention will be more apparent from the following description of certain exemplary embodiments taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention; -
FIG. 2 is a plan view showing interconnects and a via hole inFIG. 1 ; -
FIGS. 3A to 3L are process drawings showing an embodiment of a manufacturing method of a semiconductor device according to the present invention; -
FIG. 4 is a plan view showing a comparative example of the embodiment; -
FIG. 5 is a plan view to explain a modification of the embodiment; -
FIG. 6 is a plan view to explain a modification of the embodiment; -
FIG. 7 is a plan view to explain a modification of the embodiment; -
FIGS. 8A and 8B are a sectional view and a plan view, respectively, of a semiconductor device of a related art; -
FIGS. 9A and 9B are SEM photographs to explain a problem of the related art; -
FIG. 10 is a plan view to explain a problem of the related art; and -
FIG. 11 is an SEM photograph to explain a problem of the related art. -
FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. Asemiconductor device 1 is provided with an interconnect 10 (a first interconnect) and a via 20. An interconnection or an interconnect wiring can be used as the interconnect. In this embodiment, theinterconnect 10 is an M2 interconnect, i.e., an interconnect of the second layer from below in thesemiconductor device 1. The via 20 is provided under theinterconnect 10 and is in contact with an end portion of theinterconnect 10. - The
interconnect 10 and the via 20 have a dual damascene structure. That is, theinterconnect 10 and the via 20 are made of copper as one piece. Abarrier metal film 52 is provided so as to collectively cover theinterconnect 10 and the via 20. Theinterconnect 10 and the via 20 are formed in aninterlayer dielectric film 46. - An interconnect 30 (a second interconnect) is provided under the via 20. In this embodiment, the
interconnect 30 is an M1 interconnect, i.e., an interconnect of the lowest layer in thesemiconductor device 1. Theinterconnect 30 is connected to theinterconnect 10 via the via 20. Abarrier metal film 54 is provided so as to cover thisinterconnect 30. Theinterconnect 30 is formed in aninterlayer dielectric film 44. Theinterlayer dielectric film 44 is formed on asemiconductor substrate 42. Thesemiconductor substrate 42 is for example a silicon substrate. Between theinterlayer dielectric film 44 and theinterlayer dielectric film 46 is provided anetching stopper film 48. Theetching stopper film 48 is for example an SiCN film. -
FIG. 2 is a plan view showing theinterconnects FIG. 1 .FIG. 1 is an A-A′ sectional view ofFIG. 2 . InFIG. 2 , an end surface of the via 20 on theinterconnect 10 side is indicated by hatch lines. As is apparent from this figure, for the above-described end surface of the via 20, a maximum length d1 in a longitudinal direction (a transverse direction inFIG. 2 ) of theinterconnect 10 is larger than a maximum length d2 in a direction perpendicular to the longitudinal direction. The maximum length d2 is substantially equal to the width of theinterconnect 10. Incidentally,FIG. 2 shows an ideal positional relationship between theinterconnect 10 and the via 20, i.e., a positional relationship obtained when there is no positional displacement. - In this embodiment, the above-described end surface of the via 20 has the shape of a rectangle having a long side parallel to the longitudinal direction of the
interconnect 10. Therefore, the maximum length d1 and the maximum length d2 are equal to the length, respectively, of the long side and short side of the rectangle. The shape of the section of the via 20 parallel to the above-described end surface is substantially constant. That is, the sectional shape of the via 20 is substantially constant regardless of the height from thesemiconductor substrate 42. - With reference to
FIGS. 3A to 3L , a description will be given of an example of a manufacturing method of thesemiconductor device 1 as an embodiment of a method of manufacturing a semiconductor device according to the present invention. This method includes a step of forming theinterconnect 10 and the via 20 by the dual damascene process. Precisely speaking, first, theinterlayer dielectric film 44 is formed on the semiconductor substrate 42 (FIG. 3A ). Subsequently, after the application of a resistfilm 62 to theinterlayer dielectric film 44, the resistfilm 62 is patterned. And by etching theinterlayer dielectric film 44 using this resistfilm 62 as a mask, atrench 32 for theinterconnect 30 is formed (FIG. 3A ). Subsequently, after the formation of thebarrier metal film 54 on the whole surface of theinterlayer dielectric film 44, acopper film 30 a is formed so as to bury the trench 32 (FIG. 3C ). - Next, the
barrier metal film 54 andcopper film 30 a that are present outside thetrench 32 are removed by CMP (chemical mechanical polishing). As a result of this, theinterconnect 30 is formed (FIG. 3D ). Next, theinterlayer dielectric film 46 is formed above theinterlayer dielectric film 44 via the etching stopper layer 48 (FIG. 3E ). After that, ahole 22 for the via 20 is formed by selectively etching a prescribed region of the interlayer dielectric film 46 (FIG. 3F ). As described above, in this embodiment, thehole 22 for the via 20 is formed before the formation of a trench for theinterconnect 10. That is, the via-first process is adopted. - Next, a BARC (bottom anti-reflection coating)
film 64 is formed so as to bury the hole 22 (FIG. 3G ). Subsequently, after the application of a resistfilm 66 to theinterlayer dielectric film 46, the resistfilm 66 is patterned (FIG. 3H ). And atrench 12 for theinterconnect 10 is formed by etching theinterlayer dielectric film 46 using this resistfilm 66 as a mask, and thereafter the resistfilm 66 is removed (FIG. 3I ). - Next, the
BARC film 64 remaining within thehole 22 is removed (FIG. 6A ). Furthermore, theetching stopper film 48 present in the bottom portion of thehole 22 is removed by etching (FIG. 3K ). Subsequently, after the formation of thebarrier metal film 52 on the whole surface of theinterlayer dielectric film 46, acopper film 10 a is formed so as to collectively bury thetrench 12 and the hole 22 (FIG. 3L ). After that, abarrier metal film 52 and thecopper film 10 a that are present outside thetrench 12 and thehole 22 are removed by CMP. As a result of this, theinterconnect 10 and the via 20 are simultaneously formed and thesemiconductor device 1 shown inFIG. 1 is obtained. - The advantage of this embodiment will be described. In this embodiment, the end surface of the via 20 on the
interconnect 10 side is formed so as to be elongated in the longitudinal direction of theinterconnect 10. As a result of this, the area of a region where the via 20 and theinterconnect 10 overlap is expanded. Therefore, during manufacturing it is possible to ensure a large margin for a relative positional displacement between thetrench 12 for theinterconnect 10 and thehole 22 for the via 20. For this reason, the alignment manufacturing limit of dual damascene is improved. The alignment manufacturing limit refers to an upper limit value of the amount of positional displacement that is allowed for ensuring a necessary yield. According to this embodiment, thesemiconductor device 1 having high reliability and a manufacturing method of thereof are realized. - Incidentally, from the standpoint of sufficiently expanding the area of a region where the via 20 and the
interconnect 10 overlap, it is preferred that the maximum length d1 (seeFIG. 2 ) of the via 20 be not less than twice the maximum length d2. - Furthermore, in this embodiment, the area of the via 20 as plan viewed increases by the amount of elongation of the via 20 in the longitudinal direction of the
interconnect 10. As a result of this, the quantity of light that comes in from the mask of the via 20 during exposure increases and, therefore, a lithography margin expands. - The via 20 is in contact with an end portion of the
interconnect 10. In this case, even a slight positional displacement results in a reduction of the area of a region where the via 20 and theinterconnect 10 overlap. Therefore, the usefulness of this embodiment that enables a large margin for positional displacement to be ensured becomes especially high. - The
interconnect 10 and the via 20 are made of copper as one piece. In this case, electric resistance can be reduced compared to a case where a barrier metal film is interposed between the two layers. - The maximum length d2 of the above-described end surface of the via 20 is substantially equal to the width of the
interconnect 10. For this reason, when there is no positional displacement, the whole via 20 is to be accommodated under theinterconnect 10. As a result of this, it is possible to ensure a sufficient gap between an interconnect in close proximity to theinterconnect 10 and the via 20. - In this connection, as a technique for increasing the area of a region where the via 20 and the
interconnect 10 overlap, for example as shown inFIG. 4 , it is also conceivable to elongate the above-described end surface of the via 20 in a direction perpendicular to the longitudinal direction of theinterconnect 10. This figure shows a plane similar to that ofFIG. 2 . In this case, however, the via 20 sticks out from under theinterconnect 10 and, therefore, the gap between an interconnect in the same layer as theinterconnect 10 in close proximity to aninterconnect 10 and the via 20 decreases. This produces harmful effects, such as the phenomenon that theinterconnect 10 and the above-described interconnect in close proximity thereto cannot be arranged with a minimum gap, and the degree of freedom of design becomes narrow. - The shape of a section of the via 20 parallel to the above-described end surface is substantially constant. In contrast to this,
Patent Document 1 discloses a via hole having a protrusion. Concretely, a protrusion is formed in an upper part of the via hole. For this reason, in this via hole, the upper portion provided with the via hole and other portions have different sectional shapes. Therefore, in forming this via hole, it is necessary to perform etching by two stages, resulting in an increase in the number of manufacturing steps. In addition, it becomes necessary to perform the control of etching depth and hence process control becomes difficult. Moreover, because it becomes necessary to use two masks for this etching, the cost of manufacturing also rises. In this respect, according to this embodiment, it is possible to form thehole 22 for the via 20 by single-stage etching, and therefore, these problems can be avoided. - The
interconnect 10 and the via 20 are formed by the via-first process. In contrast to this, in the case of the trench-first process, that is, when thetrench 12 for theinterconnect 10 is formed before the formation of thehole 22 for the via 20, it is difficult to pattern the resist film for the via 20 as desired. This is because the resist film is formed on a rough surface (the bottom surface of the trench 12). In this respect, according to the via-first process, the patterning of the resist film for the via 20 becomes easy and, therefore, the via 20 can be satisfactorily formed. - Incidentally, in the 65-nm generation and beyond (the minimum interconnect width is not more than 65 nm), the above-described problem, i.e., the problem of the burying imperfection of copper in the dual damascene process becomes more conspicuous. Therefore, the usefulness of this embodiment that enables a large margin for positional displacement to be ensured becomes especially high. According to this embodiment, even in the 65-nm generation and beyond, it is possible to satisfactorily perform the formation of the
interconnect 10 and the via 20 by the dual damascene process without the introduction of an expensive lithography device. - The present invention is not limited to the above-described embodiment but various modifications are possible. In the above-described embodiment, the case where the planar shape of the
interconnects - When the planar shape of the via 20 (the shape of the end surface on the
interconnect 10 side) is not rectangular, the maximum length d1 in the longitudinal direction of theinterconnect 10 and the maximum length d2 in a direction perpendicular to this longitudinal direction are defined as follows. That is, as shown inFIG. 8 , the lengths of the sides of a rectangle capable of including the above-described end surface of the via 20, which has the smallest area (the rectangle R1), become the above-described maximum length d1, d2. However, it is defined that the rectangle R1 has a side parallel to the longitudinal direction (the transverse direction inFIG. 5 ) of theinterconnect 10, and the length of a side parallel to the longitudinal direction is the maximum length d1 and the length of a side perpendicular to the longitudinal direction is the maximum length d2. - In the above-described embodiment, the case where the longitudinal direction of the
interconnect 10 and the longitudinal direction of theinterconnect 30 are perpendicular to each other was shown as an example. As shown inFIG. 6 , however, these longitudinal directions may also be parallel to each other. - In the above-described embodiment, the case where the via 20 is in contact with the end portion of the
interconnect 30 was shown as an example. As shown inFIG. 7 , however, the via 20 may also be in contact with the middle part of the interconnect 30 (a portion other than the end portion). - The present invention has been described based on the above examples, but the present invention is not limited only to the above examples, and includes various kinds of alterations and modifications that could be achieved by a person skilled in the art within the scope of the invention of each of claims of this application as a matter of course.
- Further, it is noted that, applicant's intent is to encompass equivalents of all claim elements, even if amended later during prosecution.
Claims (23)
1. A semiconductor device, comprising:
an interconnect; and
a via material which is provided under an end of the interconnect and includes a surface in contact with a surface of the interconnect;
wherein said surface of said via material comprises a first portion along a longitudinal direction of said interconnect and a second portion along a direction perpendicular to said longitudinal direction, and a maximum length of said first portion is larger than a maximum length of said second portion.
2. The semiconductor device according to claim 1 , wherein the surface of the via material includes a rectangle shape having a long side parallel to the longitudinal direction of the interconnect.
3. The semiconductor device according to claim 1 , wherein the maximum length of said second portion is substantially equal to a width of the interconnect.
4. The semiconductor device according to claim 1 , wherein the maximum length of said first portion is not less than twice the maximum length of said second portion.
5. The semiconductor device according to claim 1 , wherein the surface of the via material includes an oval shape having a long side parallel to the longitudinal direction of the interconnect.
6. The semiconductor device according to claim 1 , wherein the interconnect comprises a first interconnect, and the semiconductor device further comprises a second interconnect which is provided under the via material to be connected to said first interconnect via the via material.
7. The semiconductor device according to claim 1 , wherein the interconnect and the via material being integrally formed copper.
8. The semiconductor device according to claim 6 , wherein the longitudinal direction of the second interconnect is perpendicular to the longitudinal direction of the first interconnect.
9. The semiconductor device according to claim 6 , wherein the longitudinal direction of the second interconnect is parallel to the longitudinal direction of the first interconnect.
10. A method of manufacturing a semiconductor device, comprising:
forming, by a dual damascene process, an interconnect and a via material, said via material being provided under the interconnect and being in contact with an end of the interconnect,
wherein said via material is formed to comprise a first portion along a longitudinal direction of said interconnect and a second portion along a direction perpendicular to said longitudinal direction, and a maximum length of said first portion is larger than a maximum length of said second portion.
11. The method of manufacturing a semiconductor device according to claim 10 , wherein the forming of the interconnect and the via material comprises:
forming a hole for the via material; and
forming a trench for the interconnect.
12. A semiconductor device, comprising:
a first wiring running in a first direction and including a copper;
a second wiring formed under said first wiring; and
a via wiring including a copper, arranged at an end portion of said first wiring, and formed between said first and second wirings, to connect said first and second wirings together therethrough, said via wiring having a top surface connected to a bottom surface of said first wiring, said top surface of via wiring having a shape defined by a first portion in parallel with said first direction and a second portion in parallel with a second direction perpendicular to said first direction, and a maximum length of said first portion being larger than a maximum length of said second portion.
13. The semiconductor device as claimed in claim 12 , wherein said shape comprises a rectangular shape.
14. The semiconductor device as claimed in claim 12 , wherein said shape comprises an oval shape.
15. The semiconductor device as claimed in claim 12 , wherein an edge of said end portion of said first wiring is aligned with an edge of said via wiring.
16. The semiconductor device as claimed in claim 15 , wherein a length of said first portion is more than twice as long as a length of said second portion.
17. The semiconductor device as claimed in claim 12 , further comprising a barrier metal film formed on superficies of said first wiring and said via wiring, said barrier metal film being absent between said top surface of said first wiring and said bottom surface of said via wiring.
18. The semiconductor device as claimed in claim 12 , wherein said second wiring includes copper and runs in said second direction and includes an end portion connected to said via wiring.
19. The semiconductor device as claimed in claim 12 , wherein said second wiring includes copper and runs in said first direction and includes an end portion connected to said via wiring.
20. The semiconductor device as claimed in claim 12 , wherein said second wiring includes copper and runs in said second direction and includes an intermediate portion connected to said via wiring.
21. The semiconductor device as claimed in claim 12 , wherein said second wiring includes a top surface defined by a length and width, said length of said second wiring is longer than said width of said second wiring, and said first length of said via wiring is larger than said width of said second wiring.
22. The semiconductor device as claimed in claim 21 , wherein said surface of said first wiring has a length and a width, said length of said first wiring is longer than said width of said first wiring, and said first length of said via wiring is larger than said width of said first wiring.
23. The semiconductor device according to claim 22 , wherein said maximum length of said second portion of said via wiring is substantially equal to said width of the first wiring.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/067,472 US8802562B2 (en) | 2007-02-19 | 2013-10-30 | Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same |
US14/316,085 US20140306345A1 (en) | 2007-02-19 | 2014-06-26 | Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007-038361 | 2007-02-19 | ||
JP2007038361A JP2008205122A (en) | 2007-02-19 | 2007-02-19 | Semiconductor device and its manufacturing method |
Related Child Applications (1)
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US14/067,472 Continuation US8802562B2 (en) | 2007-02-19 | 2013-10-30 | Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same |
Publications (1)
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US20080197494A1 true US20080197494A1 (en) | 2008-08-21 |
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Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
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US12/068,712 Abandoned US20080197494A1 (en) | 2007-02-19 | 2008-02-11 | Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same |
US14/067,472 Active US8802562B2 (en) | 2007-02-19 | 2013-10-30 | Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same |
US14/316,085 Abandoned US20140306345A1 (en) | 2007-02-19 | 2014-06-26 | Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same |
Family Applications After (2)
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US14/067,472 Active US8802562B2 (en) | 2007-02-19 | 2013-10-30 | Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same |
US14/316,085 Abandoned US20140306345A1 (en) | 2007-02-19 | 2014-06-26 | Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same |
Country Status (2)
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US (3) | US20080197494A1 (en) |
JP (1) | JP2008205122A (en) |
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US20140322910A1 (en) * | 2012-05-01 | 2014-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Via-free interconnect structure with self-aligned metal line interconnections |
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CN102216392B (en) | 2008-08-08 | 2014-12-10 | 日本合成化学工业株式会社 | Resin composition, melt-molded article, multi-layered structure, and process for production of resin composition |
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Also Published As
Publication number | Publication date |
---|---|
US8802562B2 (en) | 2014-08-12 |
US20140306345A1 (en) | 2014-10-16 |
JP2008205122A (en) | 2008-09-04 |
US20140057432A1 (en) | 2014-02-27 |
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