TW200300286A - Package enclosing multiple packaged chips - Google Patents

Package enclosing multiple packaged chips Download PDF

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Publication number
TW200300286A
TW200300286A TW091132963A TW91132963A TW200300286A TW 200300286 A TW200300286 A TW 200300286A TW 091132963 A TW091132963 A TW 091132963A TW 91132963 A TW91132963 A TW 91132963A TW 200300286 A TW200300286 A TW 200300286A
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TW
Taiwan
Prior art keywords
circuit board
package
packaged
integrated circuit
wafers
Prior art date
Application number
TW091132963A
Other languages
English (en)
Inventor
Soon-Shin Shee
Leilei Zhang
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of TW200300286A publication Critical patent/TW200300286A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73253—Bump and layer connectors
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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    • H01L2924/1626—Cap-in-cap assemblies
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Description

200300286 玖、發明說明 【發明所屬之技術領域】 本發明係關於積體電路裝置的封裝，更特別地是關於 將多個積體電路晶片封裝於單一封裝內。 【先前技術】 包含多個積體電路晶粒的多晶片封裝係半導體業所熟 知。多晶片封裝可包含多個晶粒已安裝於其上的薄印刷電 路板。各晶粒係打線接合於印刷電路板，且印刷電路板係 裝附於具有外部接腳的封裝基材。接著將封蓋施加於此封 裝。或者，多晶片封裝可包含具有表面金屬線之有支撐作 用的電絕緣基板，其中晶粒係裝附於該電絕緣基板。 第1圖表示建置於印刷電路板上之先前技藝多晶片封 裝的剖面側視圖。二個晶粒D1與D2同時機械且電性裝附 於電路板B1。機械連接係由糊膠E1與E2所提供。電連接 係藉由諸如W1至W4之接合線完成。電路板B1爲包含圖 樣化導電層L1至L4的四層電路板。該圖式係經簡化，以 助於瞭解。在第1圖中，晶粒D1的焊墊P1係電連接至晶 粒D2的焊墊P3。該連接係穿經接合線W1、接點C1、通孔 V51、L4之線路L41、通孔V41、L3之線路L31、通孔V43 、L4之線路L43、通孔V53、接點C3、接合線W3，而終止 於焊墊P3。焊墊P4連接至外部焊料球SB6。該連接係穿經 接合線W4、接點C4、通孔V54、線路L44、通孔V44、線 路L34、通孔V34、線路L24、通孔V24、線路L14、通孔 200300286 V14’而到達焊料球SB6。市售電路板通常具有較所示更爲 辛复的％電線路圖案及更多的導電線路。 #爲所熟知的是覆晶多晶片封裝（其中幾個裸露晶粒 胃有纟旱料凸塊裝附於其輸入/輸出焊墊）係反覆並裝附於大 白勺晶f立，接著將裸露晶粒彼此互連，並將晶粒連接至印刷 。其次，使用打線接合或焊料凸塊將大晶粒上的周 邊金觸裝附於封裝的引腳。 $ 2圖表示該種結構。在第2圖中，多晶片模組封裝 6() (MCVi package)包含設有階梯式通孔64的雙層印刷電 61，該階梯式通孔64的開口在印刷電路板底部。通孔 64的尺寸係使得當MCM疊塊17的矽基板18置於通孔64 11方時’基板18端部會與通孔重疊，而晶片19, 20則適於 64中。焊料重熔交連69將接合指（bond finger) 67電 _接至接點68。當裝配此裝置時，並無保護晶片19, 20的 封裝衬料。在裝配後，矽膠29將晶片與矽基板間及矽基板 ±的接合指與印刷電路板上的接點間之交連進行保護性地 包覆。見Degani等人的美國專利第5,646,828號，其對於該 種封裝有進一步的說明。 多晶片模組（MCM，multi-chip module)通常包含混合 之數種位於晶片中的未封裝晶粒。例如，Terry Costlow於 1997 年 4 月 14 日在 Electronic Engineering Times 所發表之 標題爲、、MCM Houses Pentium with MMX Technology"的文 章說明一種包含Pentium中央處理單元、PCI晶片組、RAM 晶片及其他晶片的封裝。這些裸露晶粒係裝附於交連基板 200300286 上，而該交連基板係藉由形成薄導電膜於印刷電路板層上 並將其圖樣化而形成。該基板提供外部連接至模組，並變 成包覆該混合晶粒之單一封裝的一部分。 多晶片封裝的一目的在於使用最小且最短的金屬線路 或金屬片於晶片間，以便在晶片間具有最快的傳遞。另一 個目的在於縮小多晶片模組的尺寸。爲達成這些目的，個 別晶片置於MCM前通常未個別進行封裝。 MCM封裝的價格通常相當高，因爲需要製造期間的裸 露晶片處理成本及將晶粒裝配於MCM中的成本。通常，各 晶粒係於其仍爲晶圓的一部分時進行測試，之後，將不合 格晶粒拋棄，並將合格晶粒留著使用。然而，標準晶圓測 試不足以檢測存在於成品中的所有缺陷。晶粒中的部分缺 陷無法藉由探針測試進行檢測。測試後將晶粒進行進一步 處理時就發生其他缺陷。在部分狀況下，通過晶圓測試的 該晶粒僅有約80%在最終封裝測試時發現實際上爲合格的 。這些缺陷大幅降低最終製品的良率。例如，倘若多晶片 封裝係使用四個晶片形成，其在安裝於多晶片封裝之後將 有80%爲合格的，所以封裝的良率可能不會超過 0.8χ〇.8χ〇.8χ〇.8= 40%。因此，不完整的未封裝晶片測試對 於良率有明顯的損害，因而降低獲利。用於裸露晶粒階段 決定合格晶粒的完整測試方法係如此昂貴，以致不具競爭 力。 MCM額外的成本問題在於將晶粒裝附於多晶片封裝基 板爲昂貴的。晶片必須與其裝附的電路板精確對齊，以使 200300286 接合線正確對齊。該對齊較單晶片封裝的對齊更爲困難， 因爲通常僅有晶片的一個邊或角落靠近其裝附之電路板的 一個邊或角落。此外，必須將至少部分的接合線裝附在電 路板〈而非將接合線裝附於比較大間距的引腳架〉，以用 於將訊號輸送至封裝中的其他晶片；且電路板必須具有微 細間距，以允許高密度交連。因此，裝配步驟期間所造成 的故障將進一步降低良率。 業界需要較不昂貴之形成高複雜性多晶片封裝的方法 【發明內容】 根據本發明，多封裝結構包含位於封裝中的封裝。個 別晶片係封裝於諸如晶片尺寸級封裝的小型封裝中。通常 ，係於晶圓與封裝階段進行這些晶片的測試。這些晶片現 爲其封裝所保護，並將使經最終封裝的裝置不易發生故障 。接著將經個別封裝的晶片裝配於MCM基板上，並接著進 行測試、封裝及最終測試。 本發明的製程係於經個別封裝的小型晶片封裝於最終 封裝之前便進行測試。當個別處理與封裝晶片時，便可以 廉價的方式測試晶片。例如，測試經封裝晶片的成本可僅 爲測試未封裝晶片的10%。因此，相較於先前技藝的結構 ，藉由本發明可明顯降低MCM的成本，因爲在MCM裝配 前便可完整測試個別的晶片，因而提高良率。 本發明使得將晶片裝配成最終封裝變得更加穩健。處 200300286 理經封裝晶片較處理習知MCM裝配所需的裸露晶粒更爲容 易。經封裝晶片的間距較裸露晶粒上的焊墊間距爲大。因 此，將個別晶片與外MCM封裝連接變得更爲容易。本發明 的裝配流程係類似於其他的標準封裝表面安裝製程。因此 ，可使用現有的表面安裝裝配線，而無須新的資本投資。 使用亦可用於諸多其他製品之現有的裝配製程將大幅降低 裝配成本。 小型晶片尺寸封裝的高度很小，以使這些經封裝晶片 得以適當地裝配於另一個封裝中。再者，因爲封裝尺寸非 常接近裸露晶粒的尺寸，所以在將數個晶粒安裝於最終封 裝之前，將個別晶粒包覆於封裝中所需的面積甚小。 【實施方式】 第3a圖與第3b圖表示根據本發明之多封裝模組的上 視圖與側視圖。所示的具體實例包含安裝於多封裝電路板 314上的三個封裝晶片311，312, 313。晶片311, 313係封裝 於球柵陣列封裝中，而晶片312則封裝於薄塑膠四方扁平 型封裝。在一實施例中，該三個晶片包含FPGA、RAM及 微處理器。任何該種個別晶片的組合皆可使用本發明，只 要個別晶片置於小外形尺寸的表面安裝封裝中。 MCM晶片314包含焊塊319，而僅有一些焊塊319表 示於第3b圖中。FPGA晶片311下表面上的焊料凸塊311a 及延伸自DSP微處理器晶片312側面的引腳312a係連接至 相應的焊塊319。該焊塊接著經由MCM晶片314中的薄層 200300286 而連接至其他焊塊；該其他焊塊接著連接至其他晶片上的 引腳，或連接至接著連接至封裝外部之焊料凸塊314a之一 的引腳，因而在第3a或3b圖之封裝外部的點與晶片 311〜313之一內部的點之間提供通路。 爲提高導熱性，在金屬封蓋316定位與裝附前，可將 熱油脂317施加於晶片311-313上表面。 相較於以裸露晶粒製做的MCM封裝，本發明的另一個 優點爲可將晶片311-313個別移除、修復、取代或升級，而 無須拋棄MCM封裝的其餘部分。 第4圖表示用於製造第3圖之MCM的製程步驟。圖式 的上半部表示用於製造、測試、封裝及測試三個個別晶片 311，312, 313的平行步驟。如步驟401-406所示，在晶圓上 製造晶片311，在晶圓上進行測試，切割成爲個別晶片，將 合格者封裝於封裝中〈最好爲晶片尺寸的封裝〉，以及進 行最終測試。該最終測試爲完整的測試，且仍較在未封裝 晶粒上進行之已知合格晶粒測試便宜許多。在各測試階段 ，僅有合格晶粒會移至下個階段。因此，在步驟406，僅合 格的晶片311會輸送至MCM裝配器。步驟411-416僅提供 合格的晶片312至裝配器，且步驟421-426僅提供合格的晶 片313至裝配器。 亦將MCM電路板314提供於裝配器，其中有三個晶片 將置於該MCM電路板314中。步驟431-433顯示MCM電 路板的製造與測試，且僅有合格的MCM電路板會輸送至裝 配器。 200300286 在步驟441進行裝配。在該步驟中，將三個晶片3u， 312, 313審慎地對著相應之MCM電路板314的焊塊進行安 置。該步驟較由未封裝晶片形成MCM來得容易且更可靠， SS該焊料凸塊或引腳彼此間的間距較大，且較裝附於裸 露晶片上之晶粒裝附焊墊的焊墊或焊料凸塊爲大。（爲詳 細起見，見第5圖至第8圖的說明）。步驟442與444表 示封裝密封前、後所進行的測試。在封裝密封前，得以藉 由施加測試訊號至封裝的外部引腳或焊料球，而進行診斷 測試（diagnostic probe testing)及產品測試。在另一個實施 例中，省略步驟442，而在封裝步驟443完成後進行所有的 MCM測試。 第5a圖至第5d圖示範用於將經封裝的晶片安裝於裸 露電路板（其將形成部分的外部封裝）之較佳製程中的步 驟。如第5a圖所示，該製程始於裸露電路板601。如第5b 圖所示，將焊料糊膠602施加於裸露電路板601，該焊料糊 膠602的施加位置爲經封裝之晶片的焊料球將裝附於電路 板601的位置。如第5c圖所示，將經封裝的晶片611, 612 對著電路板601放置，以使得經封裝之晶片611，612的焊 料球603與焊料糊膠602對齊。其次，如第5d圖所示，將 總成置於重熔烤箱中，並升至足以熔解焊料糊膠602與焊 料球603 (或者在另一個實施例中爲相當於焊料球603的金 屬接腳）的溫度，而在焊料球603與電路板601中的導體 (未表示於圖式中）之間形成永久電連接。這些電導體可 將晶片611，612彼此連接，並可將晶片611，612連接至未 12 200300286 示於圖式中的外部焊料球。 第6圖示範用於形成第5a圖至第5d圖之內部結構的 製程步驟。在步驟701中，將裸露電路板裝載於夾具中。 在步驟702中，將網板置於裸露電路板上並施加焊料糊膠 ，而在網板的開口處將焊料糊膠接觸並施加於電路板上。 其次，在步驟703中，將經封裝的晶片對著電路板放置， 以使晶片下表面的焊料球與焊料糊膠圖案對齊。接著將該 結構置於重熔烤箱中，並加熱至焊料糊漿充分熔解爲止， 而對經封裝之晶片的焊料球與電路板形成良好的電性與機 械連接。在該結構冷卻後，在步驟705中，將該結構進行 淸洗而移除可能堆積的任何碎片。最後，在步驟706中， 進行目視檢測。該製程係與廣泛使用於電子業的標準表面 安裝製程相容。該球柵陣列封裝製程無須使用特殊的設備 〇 第7a圖至第7d圖示範當完成圍繞內部封裝的外部封 裝時，連續階段的結構。第7a圖表示如第5a圖至第5d圖 所製備的結構。如第7b圖所示，在電路板601的外緣施加 一圈黏著劑801，用於容納並裝附封蓋。如第7c圖所示’ 安置封蓋802，以使其邊緣與黏著劑801的邊緣接觸。依據 所選擇的黏著劑而定，藉由加熱或等待或二者同時進行而 將黏著劑固化。最後，如第7d圖所示，將焊料球803裝附 於電路板601，而完成外部封裝。 第8圖表示用於形成第7a圖至第7d圖所示之最終封 裝的製程步驟。在步驟901中，將裝附有經封裝之晶片的 13 200300286 電路板安置於夾具中。在步驟902中，將電路板外緣施加 黏著劑珠粒。在步驟903中，將封蓋定位，以便將經封裝 的晶片密封，並使封蓋邊緣座落於黏著劑中。在步驟904 中，將黏著劑固化，以使其在封蓋與電路板之間形成牢固 的連接。通常在步驟905中將標印置於封蓋上，以辨識經 裝配的封裝；而在另一個具體實例中，可於封蓋裝附於電 路板之前，便將標印置於封蓋上。其次，在步驟906中， 將做爲外部電接觸的焊料球裝附於電路板上。 下個步驟907係將電路板分割。在一較佳製程中，所 形成的電路板爲用於裝附數組經封裝之晶片與封蓋之具有 線路的長條。倘若電路板係以該方式製做，則在步驟907 中將其切割成個別的封裝。最後，在步驟908中，進行最 終電性與機械測試，及最終目測檢視；以及將完成的封裝 包裝而運送至消費者。 封蓋裝附、標印及焊料球裝附步驟係塑膠球柵陣列總 成製程中的標準步驟。 已說明用於完成與使用本發明的數個具體實例。然而 ，本發明不應僅限於在此所示的具體實例，而應包含熟諳 此技藝者對前揭說明明顯可爲的變化。 【圖式簡單說明】 (一）圖式部分 第1圖表示由個別晶片電連接至球柵陣列封裝下表面 的先前技藝多晶片模組。 200300286 第2圖表示形成於美國專利第5,646,828號〈Degani等 人〉所示之印刷電路板通孔中的先前技藝多晶片模組。 第3a圖與第3b圖表示根據本發明之多封裝模組的上 視圖與側視圖。 第4圖表示用於形成根據本發明之多封裝模組的步驟 〇 第5a圖至第5d圖表示根據較佳具體實例之用於將晶 片安裝在裸露電路板〈爲外部封裝〉的步驟。 第6圖圖示用於形成第5a圖至第5d圖之內部結構的 製程步驟。 第7a圖至第7d圖圖示當完成圍繞內部封裝的外部封 裝時，連續階段的結構。 第8圖表示用於形成第7a圖至第7d圖所示之最終封 裝的製程步驟。 (二）元件代表符號 薄層4 多晶片模組疊塊Π 矽基板18 晶片19，20 矽膠29 多晶片模組封裝60 雙層印刷電路板61 階梯式通孔64 接合指67 200300286 接點68 焊料重熔交連69 經封裝的晶片311〜313 焊料凸塊311a 引腳312a 多封裝電路板314 焊料凸塊314a 電路線315 金屬封蓋316 熱油脂317 焊塊319 多晶片模組3 2 0 裸露電路板601 焊料糊膠602, 602a 焊料球603 經封裝的晶片611，612 黏著劑801 封蓋802 焊料球803 電路板B1 接點 Cl，C3, C4 晶粒Dl，D2 糊膠El，E2 導電層L1〜L4 16 200300286 線路 L14, L24, L31，L34, L41，L43, L44 焊墊 Pl，P3, P4 焊料球 SB1，SB2, SB6, SB7 通孑L V14, V24, V34, V41，V43, V44, V51，V53, V54 接合線W1〜W4
17

Claims (1)

  1. 200300286 拾、申請專利範圍 1. 一種多封裝模組，其包含： 數個經個別封裝的積體電路晶片，各該經個別封裝的 積體電路晶片含有數個導電性接點； 線路結構，該導電性接點係裝附其上；以及 封裝，其包覆該經個別封裝的積體電路晶片與該線路 結構，並含有由其內部延伸至外部且電連接至某些該導電 性接點的電性引腳。 2. 如申請專利範圍第1項之多封裝模組，其中該導電 性接點位於該經個別封裝之積體電路晶片的一表面。 3 ·如申g靑專利範圍第1項之多封裝模組，其中該導電 性接點包含焊料凸塊。 4·如申請專利範圍第1項之多封裝模組，其中該導電 性接點包含延伸自該經個別封裝之積體電路晶片之邊緣的 引腳。 5· —種用於形成多封裝模組的方法，包含下列步驟： 製造將要被封裝於單一模組中的數個晶粒； 以至少〜次晶粒測試來測試該晶粒； 將通過[該晶粒測試的晶粒封裝成經封裝的晶片； 以晶片測試來測試該經封裝的晶片； 將一組經封裝的晶片裝附於MCM電路板，藉此將該組 經封裝的晶片進行交連；以及 將該組經封裝的晶片包覆於含有該MCM電路板的外封 裝中。 18 200300286 6 · —種用於製造包覆數個半導體封裝之半導體纟彳％ _ 方法，包含下列步驟： 將數個經封裝的積體電路晶片裝附於電路板； 將封蓋裝附於電路板，並藉此包覆該數個經封裝的積 體電路晶片；以及 將數個焊料球裝附於電路板。 7 ·如申g靑專利範圍第6項之方法’其中將數個經封裝 的積體電路晶片裝附於電路板的步驟包含： 將一焊料糊膠圖案施加於裸露電路板； 將該數個經封裝的積體電路晶片對著該焊料糊膠圖_ 放置，以使得各積體電路晶片的各接腳接觸於焊料糊0區 域；以及 將該經封裝的積體電路晶片與電路板加熱，以使得言亥 焊料糊膠對該接腳與電路板流動，而將該接腳電性且機Μ 地連接至該電路板。 8. 如申請專利範圍第6項之方法，其中將封蓋裝附於 該電路板並藉此包覆該數個經封裝的積體電路晶片的步驟 包含： 將黏著劑施加於電路板的至少一個邊緣； 將該封蓋置於該數個半導體封裝上，以使得該封蓋接 觸該黏著劑；以及 將該黏著劑固化。 9. 如申請專利範圍第8項之方法，在將數個焊料球裝 附於電路板的步驟之前，更包含以適當的標籤將該封蓋進 200300286 行標印的步驟。 10.如申請專利範圍第6項之方法，在將數個焊料球 裝附於電路板的步驟之後，更包含將該電路板分割的步驟 拾壹、圖式 如次頁
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