TH6559B - A microcomputer system that uses a positional compensation mechanism to increase the capacity of the hidden memory it can accommodate. - Google Patents

Abstract

Increasing the capacity of the secret memory that the secret memory controller can support. This can be achieved by shifting the relationship between the processor output signal terminal and the input signal terminal of the secret memory controller and by doubling the size of the secret memory line accordingly in some case An additional logic device creates a hidden memory loop to retrieve a number of bytes equal to the size of the new line size from memory regardless of the width of the data line. A false memory read causes a hidden memory cycle to be initiated, and another logic device generates a memory location signal that the processor does not generate. The hidden memory controller cannot see the hidden memory cycle because the READY signal is inhibited from changing until the end of the hidden memory cycle and both normal memory cycles.

Claims (14)

1. A multi-wire microcomputer system consists of a central processing unit (CPU) and a secret memory subsystem, which are interconnected via CPU local area lines. The secret memory subsystem comprises a secret memory controller and secret memory. System line factors connect the secret memory controller's circuitry to a number of random access memory and addressable operation units. If the CPU has CPU output address channels and the secret memory controller has input address channels, factors connect some CPU output address channels to some secret memory controller input address channels, causing some CPU output address channels to connect to mismatched input address channels of the secret memory controller. 2. A multi-wire microcomputer system as described in Claim 1, which also includes a logic factor for generating address signals which generate address signals into the aforementioned random access memory, and a factor which connects at least one of the CPU's address output channels to the said logic factor for generating address signals. 3. A multi-wired microcomputer system as described in Claim 1 or Claim 2, where the secret memory controller is a secret memory controller 82385 and where such secret memory has a capacity of at least 64 kilobytes. 4. A multi-wire microcomputer system as described in claim 2, where the input address signal, the logic factor for generating such address signal, is generated to such random access memory, differs from the address signal at the output address channel of the central processing unit. 5. A multi-wired microcomputer system as described in Claim 1, which also includes a logic factor for generating address signals which generate address signals into the secret memory, and a factor which connects at least one address signal output channel of the central processing unit to the logic factor for generating address signals. 6. A multi-wire microcomputer system as described in claim 5, where the logic factor for generating such address signals also generates address signals into such random access memory. 7. A multi-wire microcomputer system as described in claim 6, where the input address signal, the logic factor for generating such address signal, is generated to such random access memory, differs from the address signal at the output address channel of the central processing unit. 8. A multi-wire microcomputer system as described in claim 5, where the input address signal, the logic factor for generating such address signal, is generated to the secret memory, differs from the address signal at the output address channel of the central processing unit. 9. A multi-line microcomputer system consisting of a central processing unit (CPU) and a secret memory subsystem interconnected by CPU local line connections. The secret memory subsystem comprises an 82385 secret memory controller and secret memory. The CPU comprises CPU output address factors; factors that connect some CPU output addresses to the 82385 secret memory controller input addresses; factors that connect the CPU output addresses to mismatched 82385 secret memory controller input addresses; system line factors that connect the 82385 secret memory controller to random access memory and a number of addressable operations; address signal generation logic factors that generate address signals to the secret memory; factors that connect at least one CPU output address factor to the address signal generation logic factor; and factors that connect the CPU output addresses to the secret memory, in the case where the secret memory has a capacity of at least 64 kilobytes. 10. A multi-wire microcomputer system as described in claim 9, where the input address signal, the logic factor for generating such address signal, is generated to the secret memory, differs from the address signal at the output address channel of the central processing unit. 11. A multi-wire microcomputer system as described in claim 9, where the logic factor for generating such address signals generates address signals into such random access memory. 12. A multi-wire microcomputer system as described in claim 11, where the input address signal, the logic factor for generating such address signal, is generated to such random access memory, differs from the address signal at the output address channel of the central processing unit. 13. A multi-wire microcomputer system as described in claims 11 or 2, which also includes a hidden cycle initiation factor connected to the said central processing unit and to the said secret memory controller and will react to failed reads of secret memory specified by the said secret memory controller by initiating a hidden cycle read of the memory. 14. Multi-wired microcomputer systems as described in claim no. or no. 2, where the CPU output signal channels A3 to A30 are connected to the input signal channels CCA2 to CCA29 of the said memory controller, and the CPU output signal channel A2 is connected to the logic factor for generating such signal channels.