TH6430B - A process and a device for transferring data between two data processors, each driven by an independent clock signal. - Google Patents

Abstract

Methods and devices used to transfer data sets from transmitter storage (REG 1) to receiver storage (REG 2) between sending and receiving devices. Which are driven by the first clock signal (CL 1) and the second (CL2) respectively. The signal, which is assigned a status (WR1) with two different absolute values, is sent from the sender side to the receiver side. Which later the state of this signal will be changed differently from the one sent from the transmitter side. This state-defined signal is exchanged by a logic circuit. To initiate a write signal (WR 2), this results in a successful recording to the receiver's storage (REG2) and the write signal is interrupted by the receiver side clock (CL2).

Claims (1)

1. Procedures for transfer of datasets in parallel from transmitter storage (REG1) to receiver storage (REG 2) between sending and receiving devices. They are driven by the first clock (CL1) and the second (CL2), respectively, which operate independently of each other. This transfer is due to the fact that the receiver's storage is triggered by the signal. Written which state (WR1) is assigned, it can be assumed to be 2 exact signals for use alternately and sent from transmitter side to receiver side. Where the state of the written signal will change when the transfer of data from the transmitter side is initiated, the status signal will be adjusted by the logic circuit together with the clock on the receiver side. To perform the following functions: (a) Makes the start of the write signal (WR 2) align with the clock signal range on the receiver side (b) prevents the writing signal from being stopped by the timing of the clock signal on the instrument side. Get (CL 2) to assist. 2. Procedures for transferring data sets in parallel from the sender's storage. (REG1) to the receiver's storage unit (REG 2) between the sending and receiving devices. Which are driven by the first clock signal (CL1) and the second (CL2), respectively, operate independently of each other. This transfer is due to the receiver's storage being impulsed by a claim write signal. 1. A special feature is given that on the transmitter side, there is also a first logic circuit (F1), which performs the function of transmitting a designated signal (WR1) to the receiver at the time of the transfer of data. The signal generator (WR1) used can be assumed with two exact signals to be used alternately. The receiver has a second logic circuit (D2, X2, F2) which is activated by a change in the signal state (WR1) and by the receiver's clock. To force the write signal (WR2) to start in accordance with that clock range. This writing contract is fed to the receiver's storage (REG 2) to trigger the storage (REG 2) to start with the start of a certain second clock signal (CL2) and when the interval The second clock signal the next stroke occurs The write signal fed to the receiver (REG 2) will be interrupted by the second logic circuit (D2, X2, F2).