SU997257A1

SU997257A1 - Frequency divider

Info

Publication number: SU997257A1
Application number: SU813329666A
Authority: SU
Inventors: Александр Сергеевич Витер; Валерий Богданович Дудыкевич
Original assignee: Львовский Ордена Ленина Политехнический Институт Им.Ленинского Комсомола
Priority date: 1981-08-20
Filing date: 1981-08-20
Publication date: 1983-02-15

Description

(54) ДЕЛИТЕЛЬ ЧАСТОТЫ(54) FREQUENCY DIVER

I Изобретениеотноситс к импульсной технике и предназначено дл использовани , например, в частотноимпульсных устройствах обработки информации.I The invention relates to a pulse technique and is intended for use, for example, in frequency-pulse information processing devices.

Известен делитель частоты, содержащий элемент CJioжeни -Бычитaни , сумматор 1.Known frequency divider containing the element of CJiozheni-Cum, the adder 1.

Устройство характеризуетс нёдосTaiTO4Ho высокой точностью работьг.The device is characterized by high precision workodes.

Наиболее близким техническим ре-, шением к изобретению вл етс .делитель частоты, содержащий элемент сложени -вычитани , входыкоторого подключены к выходам коммутатора, входы которого соединены с выходами элемента ИЛИ, входы которого соединены через задержки с выходом сумматора, вход которого соединен с .выходом делител частоты 2..The closest technical solution to the invention is a frequency divider containing an addition-subtraction element, the inputs of which are connected to the outputs of the switch, the inputs of which are connected to the outputs of the OR element, whose inputs are connected through delays to the output of the adder, the input of which is connected to the output frequency divider 2 ..

Недостатком этого устройства вл етс наличие значительной погрешности , обусловленной флюктуацией частоты входных импульсов, котора зависит от числа разр дов делител частоты. .A disadvantage of this device is the presence of a significant error due to the fluctuation of the frequency of the input pulses, which depends on the number of bits of the frequency divider. .

Цель изобретени - повышение точности работы за счет уменьшени погрешности от неравномерности час;тоты следовани импульсов.The purpose of the invention is to improve the accuracy of operation by reducing the error due to unevenness of the hour;

Поставленна цель достигаетс тем, что делитель частоты, coRet A.щий коммутатор, элемент сложени вычитани частот, элемент задержки, введен накапливающий сумматор, выход которого через элемент задержки ; подключен к входу, элемента сложени вычитани частот, выход которого к тактовым входам коммутатора, информационные входы которого соединены с ширами установки коэффициента делени , а выходы - с соответствующими входами накапливающего сумматора .The goal is achieved by the fact that a frequency divider, a switch A. switch, a subtraction addition element, a delay element, an accumulator is added, the output of which is through a delay element; connected to the input, a subtraction addition element, whose output to the clock inputs of the switch, whose information inputs are connected to the widths of the division factor setting, and the outputs to the corresponding inputs of the accumulating adder.

На чертеже приведена структурна электрическа схема устройства.The drawing shows a structural electrical circuit of the device.

Устройство содержит коммутатор 1, элемент 2 сложени -вычитани частот, элемент 3 задержки, накапливающий сумматор 4, информационные шины 5.The device contains a switch 1, an element 2 of addition and subtraction of frequencies, an element 3 of delay, accumulating adder 4, information buses 5.

Устройство работает следующим образом.The device works as follows.

Claims

In the initial state, the accumulating adder is in the zero position, and on the information buses. 5, the number N is supplied, which determines the predetermined division factor. The number Hz can take values from 1 to, where n is the number of binary bits of the control code of the number Hc). At the output of the adder 4, there is no signal, therefore, it goes through the delay element 3 to the add-subtract frequency element 2. The input frequency f passes through the element 2 without change. Each pulse of the input sequence of the .fy cell, which is fed to the clock input of the switch 1, carries the number N ,. to the accumulating adder where it is added to the previous value of the code installed in it. In case the total value of the number recorded in adder 4 exceeds its capacity .N г-j, it will overflow. At the moment of accumulating accumulator 4 on its output An impulse appears, which through the delay element 3 is fed to one of the inputs of the element 2 of the subtracting-subtraction frequency. Element 3 provides the delay of the pulse coming from the adder 4 for a time equal to the pulse width of the input frequency. To the pulse sequence, the frequency f is added or one pulse is subtracted from it. -1 frequency of pulses at the output of accumulating adder 4, which forms a pulsed feedback flow fpc, is determined by the frequency at the input of switch 1 and the control code of the number N c and is equal to f bbiyNu, ° s NW, the pulse frequency at the output of the adding element The subtraction, which is the output frequency of the controlled divider, is equal to r-4. From the rest x -: Substituting the value of i from expression 1, we get fjkNvM From the last expression, it is seen that the pulse frequency at the output of the controlled divider depends on the code N numbers supplied on tires 5. setting the division ratio. ., The range of variation of the division ratio depends on the operation mode of the addition-subtraction element. In the case of positive feedback (element 2 operates in the summation mode), the division factor changes from 1 to 1 / Nj, when Nj changes from O to N -1. In the case of negative feedback (element 3 operates in the subtraction mode), the range of variation of the deposition coefficient is two. In the case of using the frequency of the output frequency, the frequency of the feedback pulses is based on the predictions (1 and (2) we get the next dependence i - - NU. - The use of both outputs, the addition and subtraction element, allows to expand the functionality of the device. The error due to the non-uniformity of the pulses following the output of the proposed frequency divider with a variable division factor during the negative the specific feedback (element 2 operates in the subtraction mode) is determined by the expression d., J ± ibjLl 1 J VN% Nty, | de 1 y „+ Hz) - the fractional part of the expression enclosed in brackets, M is the number of input pulses within one cycle (1 - M g i; -1 operation of the device. From the expression (4} it follows that the absolute error from the non-uniformity of pulses at the output of the proposed divider does not exceed ± 1, regardless of the number of bits. As the comparison of expressions (4) and (5, in the device, the error is almost independent of the number of bits. Thus, the inclusion of a parallel-type accumulating adder in the device and changing the connections between the elements of the device allows to reduce the error due to non-uniformity of the output pulses, which improves the accuracy of the device. The invention The frequency divider containing a switch. An element of addition-subtraction of frequencies, a delay element, which is so that, in order to improve the accuracy of work, a accumulating adder is entered into it, the output is connected through the delay element through the element add the subtraction of frequencies, the output of which to the clock inputs of the switch, the information inputs of which are connected to the buses of setting the division factor, and the outputs - with the corresponding inputs of the accumulating adder .. Sources of information taken into account Knowledge in examination 1. Gusev et al. Fundamentals of pulsed and digital technology. M., Soviet Radio, 1975, p. 403, fig. 14-48.

2. USSR author's certificate g 308523, cl. H 03 K 23/00, 10.12.69.