SU1218395A1 - Device for implementing fast fourier transform - Google Patents

Description

The invention relates to computing and is intended; the CTN is a spectral display of electrical signals represented in digital form on a time scale. The use of the device is associated with digital processing of electrical signals with a time-varying cut-off frequency, which include such signals as, for example, a speech signal in communication equipment, hydro signals, sound and radar, navigation and telemetry.

The aim of the invention is to improve the speed of the device when processing signals with variable cutoff frequency.

Figure 1 shows the FFT algorithm; n and fig. 2 - functional device diagram; fig.Z - block of elements And; figure 4 - block counters; on fig.Z - block elements SH; Fig. 6 illustrates a controlled frequency divider; 7 shows a control unit; on Fig - the second decoder; figure 9 is the first decoder figure 10 is the third decoder.

A device for implementing an FFT contains a memory block 1, an arithmetic unit 2, a permanent memory block 3, an AND 4 block of elements, a block of counters 5 an OR 6 block of blocks, a controlled frequency divider 7, a control block 8, a second decoder 9, a first decoder 10, the third decoder II. Input 12 is the information input of the device, input 13 is the start input, input 14 is the input of the cutoff frequency sensor input, input 15 is the clock input.

The block 4 of the elements AND contains the first elements AND-NOT 16, the second elements AND-NOT 17, the third elements AND-NOT 18, the elements AND 19, the element. HE 20. Inputs 21-24 are inputs to block 4, and output 25 to outputs of block 4.

Block 5 of the counters 26, inputs 27-30 are the inputs of block 5, and output 31 contains the output of block 5.

Block 6 of the elements OR contains elements OR-NO 32 and elements OR 33. Inputs 34-36 are the inputs of block 6, and output 37 is the output of block 6.

The controlled frequency divider 7 contains elements AND 38, elements

183952

I-11K 39 and 40, the elements And 41 and MU. triggers 43. Inputs 44-46 vnpyu 1 - with the inputs of block 7, and output 47 - output of block 7.

c. Control block 8 contains counters 48-52, AND-NOT 53-55 elements, HE 56-58 elements, 59-61 one-shot, AND 62 element, EXCLUSIVE OR 63 element node, elements

IQ OR 64, element IS-NE 65, node of elements NOT 66, element NOT 67. Inputs 68-73 are the inputs of block 8, and outputs 74-78 are the outputs of block 8. The decoder 9 contains the decoder

15 79 with input 80 and output 81.

The decoder 10 contains the decoder 82 and the elements NOT 83. Input 84 is the input of the decoder 10, and outputs 85-86 are outputs of the decoder 20 Pa 10.

The third decoder 1 contains the decoder 87, the elements of HE 88, the element AND-NOT 89, the one-shot 90. The input 91 is the input of the third decoder 11, and the outputs 92-94 - the outputs of the third decoder 11.

The calculation of the FFT according to the algorithm shown in Fig. 1 is carried out as follows.

Initially, the FFT is computed from two points X (o) and X (8), then from four points X (0) and X (8), X (4) and X (12), but without repeating the calculation of the basic operations from the previous number of FFT points, then from eight points X (0),

35 x (8), x (4), x (2), x (2), x (10), x (6) x (14), only the additional basic operations that occur during the transition from the four-point FFT are calculated to the eight point, and

 then from all sixteen points X (0) X (8), X (4), X (12), X (2), X (10), X (6), XU4), X (1), X (9 ), X (5), X (13), X (3), X (11), X (7), X (15), but again, only the additional basic operations needed for sixteen points are calculated. FFT without repeating previously calculated basic operations from an 8-point FFT. The basic operations that are calculated when moving to the next number of FFT points and named as additional are located in the FFT algorithm (Fig. 1) as an angle. In Figure 1, the basic operations included in the respective angle have the same number of circles. The number of circles in the base operation determines the angle number of the FFT algorithm. You3

The FFT is calculated by the algorithm shown in Fig. 1 by calculating the angle, with a sequential increase in the number of the upp, starting from one for two points and ending with the number of the angle for N points of the Fourier transform. The number of the calculated angle coincides with the number of the largest iteration, calculated on this angle, and, therefore, the number of the largest angle coincides with the number of iterations n for N FFT points (n log / N), corresponding to the maximum cutoff frequency.

The end of the calculation of the FFT is determined by the end of the calculation of the FFT of the number of points determined by the corresponding cutoff frequency of the input random signal in a given time interval. The results of the spectrum calculation after the end of the FFT calculation are (Fig. 1) in the upper nodes of the algorithm or the initial memory cells of the FFT device.

The number of spectral component values is equal to the number of time samples from which the FFT is obtained for the current cut-off frequency of the input random signal.

So, for an N-point FFT corresponding to the maximum cut-off frequency fcp.Mqn, we obtain the following sequence of calculating the FFT and the location of the spectral components

If the cut-off frequency in the current time interval coincides with the maximum cut-off frequency Gsr.makg, the FFT calculation is carried out according to the above principle, starting from two points, then four points, and ending with calculating from N points, at the hiM iteration, the number of spectral components is N.

If the cutoff frequency fcp in the current time interval is two times less than the maximum cutoff frequency f,

cf.

FFT calculation

ends from d / 2 points on (n-1) -th iteration, the spectral components are in the initial N / 2 nodes of the algorithm or memory cells of the FFT device.

Similarly, if the cut-off frequency fcp is four times less than the maximum cut-off frequency fcp.Ke and the FFT calculation ends from N / 4 points on the (n-2) -th iteration, the spectral components are

15

20

25

18395.

in the initial N / 4 nodes of the algorithm

or memory cells of the FFT device.

This goes on and on, for example, if the cut-off frequency is eight times less than the maximum cut-off frequency fcp. the FFT calculation ends from the N / 8 points on the (n-3) -th iteration, the spectral components are located at the initial N / 8 nodes of the ale, Q, Q orit or memory locations of the FFT device.

The device works as follows.

The input 12 of the device (Fig. 2) receives signal samples in binary inverse order, which are recorded in memory block 1. In block 3, the com parity coefficients of the coefficients are recorded, arranged in order of their numbers.

The arithmetic unit 2 receives two operand values from the input of memory unit 1, and the complex coefficient values from another input from block 3. The arithmetic unit 2 performs calculations of the two-point FFT, whose output results are recorded in memory block I at the previous addresses of the memory cells.

Block 4 prepares the initial value of the address of the operand to be loaded into block 5 of the address of the first operand.

In block 5, a calculation is performed of the 35 subsequent address values of the first operand by adding a unit, resetting to zero and pre-recording.

In block 6, based on the value 40 of the address of the first operand and the iteration number, the value of the address of the second operand is determined. In addition, the signal arriving at the input of block 6 performs the sequential output of 45 addresses of the first and second operands to the input of block 1 of the memory.

In divider 7, the coefficient address is calculated using the organization

50 counts of the next coefficient address for the corresponding counter position, determined by the iteration number.

Control unit 8 performs

55 sequence control signals to the appropriate blocks in the process of calculating the FFT.

thirty

Descrambler 9 by angle number

determines the number of iterations and the start of the 1 address of the corner.

Descriptor 10 determines the number of basic operations in the FFT base block by iteration number.

The third decoder 11, by the number of iterations to perform at a given angle, determines the number of basic blocks of FFT and control signals during the transition to the calculation of the last iteration of a given angle.

An example. Calculating the fourth angle of a sixteen point FFT.

The starting load address for the fourth corner is equal to eight when entering each iteration, the number of iterations is equal to four, the first three iterations load the initial address eight, and the fourth (last) iteration in the angle always loads the zero address. The number of base blocks in the first iteration is four, in the second iteration two, in the third and fourth iterations in one base unit.

The number of basic operations of point-to-point FFT in the base unit is one at the first iteration, two at the second iteration, four at the third iteration, and eight basic operations at the fourth iteration.

After the completion of the calculation of the base operation after the third angle from the output of the control unit, a signal is received, which in block 5 records the initial value of the address of the first operand, and divider 7 resets the coefficient address value to zero. This signal from the output of control block 8 appears always at the beginning of the calculations of the new base unit.

At the last fourth iteration, the output of block 5 from the output of the third decoder receives a reset signal to the zero address of the first operand, and this is the initial setting of the address of the first operand for the last iteration at each angle.

The input to block 5 from the output of block 4 receives the initial value of the address recorded in block 5 at the start of calculations of the new basic block with a signal from the output of block 8 of the control. The formation of the initial value of the address in block 4 is performed on the basis of the current value.

addresses of the first operand arriving at its input, and the iteration number arriving at another input. The initial value of the address when moving from the first iteration of each corner to the second, from the second to the third, etc. up to the penultimate iteration of the angle is formed by the number of the angle fed to the input of block 4 from the output of the first decoder. The formation of the initial address is controlled from the output of the control unit 8 by the input of the block 4. The control signal received at the input of the block 4 passes the initial value of the address corresponding to the number of the angle from the output of the first decoder to the block 4 at the output of block 4. This control signal appears every time a transition is made from the first iteration to the second, from the second to the third, and so on. until the penultimate iteration of this angle inclusive, i.e. when the address is loaded in block 5, arising when calculating the first base unit for the second, third, etc. to the penultimate iteration of this angle. Dd of the rest of the basic blocks included in the iteration of the given angle, except for the first basic block, the initial value of the address in block 4 is formed by the current address value of the first operand entering the input from the output of block 5 and the iteration number entering the other input from the output of the second decoder.

The divider 7 calculates the coefficient address for each basic point-to-point FFT operation. From the output of control block 8 to the input of divider 7, a reset signal arrives at zero, this happens every time calculations are started in the base block of the BS, which corresponds to the choice of the W coefficient from the zero cell of the block 3. The input of the divider 7 receives a signal from the output of the second a decoder that controls the switching of the counting input of the divider -7. I

Under the influence of the control input, the counting input in divider 1 is connected to the corresponding counter bits to perform the counting of the address of the subsequent coefficient in the base unit. The switching of the counting input in the divider 7 is carried out depending on the iteration number, starting with the highest numbers of the counter for the first iteration and ending with the shortest counter for the last iteration.

The input of the control unit 8 is given a trigger signal, which determines the start of the device by calculating the FFT. To the other input of the control unit 8, the cut-off frequency signal is dropped, which determines the required value of the number of iterations to be performed for a random input signal in a considered period of time. The cut-off frequency signal to the input of control unit 8 must arrive before the time point at which the FFT calculations for the corresponding cut-off signal value must be completed. For example, if the cut-off frequency signal fcp is determined by the inequality ep. max f cf fcp

g /

where cf. max corresponds to the calculation of seven iterations, then in this case the cut-off frequency signal fcp is equal to seven and should arrive no later than the end of the calculation of the last basic operation in the seventh angle of the FFT calculation.

For the cutoff frequency signal, defined by the inequality .Mox

c

FFT calculations must be completed at the sixth corner, so the cut-off frequency signal input to the control block B is six and must arrive no later than the end of the calculation of the last basic operation at the sixth angle.

Similarly, .ps.,

8, H the cut-off frequency signal is five,

 avg max avg signal frequency

168

slice is four.

At the third input 15 of the control unit 8, clock pulses are received with a period equal to the execution time of the basic operation in the arithmetic unit 2.

The fourth input of the control unit 8 from the output of the decoder 10 is given a signal that determines the value of the number of basic operations in the base unit, which depends on the iteration number. The fifth input of the control unit 8 from the output of the third decoder 11 receives a signal, the specific value of the number of basic units

o

at iteration. The sixth input of the control unit 8 from the output of the third decoder 11 receives a blocking signal at the last iteration in the angle to ensure the formation of the initial value of the address in block 4 from the current value of the address of the first operand and the iteration number when the next FFT angle is calculated. The second output of the control- ing unit 8 receives a signal from an angle counter, which is distributed in the decoder 9 on the appropriate bit and determines the number of the FFT calculation angle.

The third output of the control unit 8 receives a signal from an incremental iteration counter, which in the decoder 10 is distributed over the corresponding bit and determines the iteration number.

The fourth output of the control unit 8 receives a signal from the decrement iteration counter, which in the third decoder 1I is distributed over the corresponding bit and determines the number of remaining iterations in the FFT calculation unit.

The result of the FFT calculation for the corresponding value of the cut-off frequency signal is in the cells of memory block 1, starting with zero and ending with cell number W. The value of NL is determined depending on the value of the cutoff frequency signal, for f cfmake fcp ftp.MQKC I N-tj: 2

0

0

five

Sr.max, cf. max i -v-z.

fsr mdks ftp

8. .L

N

Claims (1)

Invention Formula five 0 A device for implementing a fast Fourier transform containing a memory block, the first output of which is connected to the input of operands of the arithmetic unit, the output of which is connected to the information input of the memory block, the output of the fixed memory block is connected to the input of the coefficients of the arithmetic block, and the information input of the block The memory is an information input of the device, a control unit and three decoders, characterized in that, in order to improve speed in processing signals with variable cutoff frequency , the block of elements OR, the block of elements AND, the block of counters and a controlled frequency divider are entered into it, the input of which division factor is combined with the first inputs of the block of elements AND and the block of elements OR is connected to the first output of the first decoder, the output of the second decoder is connected to the second the course of the block of elements I, the output of which is connected to the information input of the block of counters, the information output of which is connected to the third input of the block of elements I and the second input of the block of elements IL, the output of which is connected to the address The input of the memory unit, the second output of which is connected to the third input of the OR unit, the output of the controlled frequency divider is connected to the address input of the permanent memory unit, and the control unit contains seven reversible counters, three single vibrators, an EXCLUSIVE OR element node, the node NOT elements, four AND-NOT elements, four NOT elements, two OR elements and an AND element whose output is connected to the first inputs of the first, second and third AND-NOT elements and the counting input of the first reversing counter, the input of which is It is connected to the output of the first one-shot, the start input of which is combined with the second inputs of the first, second, and third NAND elements and connected to the zero output of the second reversible counter, the subtraction input of which is combined with the input of the third reversible counter and connected to the output of the second one-vibration, input which start is combined with the third inputs of the first and second elements AND-NOT and is connected to the zero output of the fourth reversible counter, the input of which is subtracted is connected to the output of zero zero eversivnogo counter whose subtracting input is connected to the output of the third odnovibratra, the start input of which is combined with the fourth input nejpBoro ale that AND-NO and connected to the output of down counter zeroing sixth subtractor whose input is connected to the output of the seventh-zeroing rever0 five 0 five 0 five 0 five 0 five sivny counter, the counting input of which is combined with the counting input of the sixth reversible counter and connected to the output of the first element NOT, the input of which is connected to the output of the first element AND-NOT, the output of the second element AND-NOT connected to the input of the second element NOT, the output of which is connected to the counting the inputs of the fourth and the fifth reversible counters, the output of the third element AND-NOT is connected to the zeroing input of the third reversible counter and the input of the third element NOT, the output of which is connected to the counting input of the second counter, information the output of which is combined with the first input of the EXCLUSIVE OR element node and connected to the information output of the first reversible counter, first, second and tr, this output of the EXCLUSIVE OR node node is connected respectively to the first input of the first OR element, first and second inputs of the second OR element, output which is connected to the second input of the first element OR, the output of which is connected to the first input of the element AND, the information output (except the first digit) of the fifth reversible counter is combined with the information one the output of the fourth reversible counter and connected to the input of the node elements NOT, the output of which is connected to the first input of the fourth element AND – NOT, the output of which is connected to the input of the fourth element NOT, and the output of the first discharge of the fifth reversible counter connected to the second input of the fourth element I- NOT, the second input of the AND element is the device start input, the input of the device cutoff frequency is the second input of the EXCLUSIVE OR element node, the subtraction input of the seventh reversible counter combined with counting moves counter unit and controllable frequency divider and a clock input is the device, the second output of the first decoder is connected to the data inputs of the sixth and sedmog reversible counters per-. the third and third outputs of the third decoder are connected respectively to the zeroing input of the counter unit and the third input of the fourth NAND, and the third output of the third decoder is connected to the informational inputs of the fourth and fifth reversible counters, the third one-vibrator output is connected to the zeroing input of the controlled frequency divider and the write enable entry of the block of counters, the information outputs of the first, second and third reversible counters are connected to the inputs of the second, third and first decoders respectively, and the output the fourth AND-NOT connected to the fourth input of the block elements I. 1218395 ff .2 4 0 47 Jl