RU2535467C1 - Adaptive digital differentiating and predicting device - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: result is achieved by adaptive digital differentiating and predicting device, which comprises: a smoothing unit, a single-channel subunit of smoothing from the adder and register, the subunit of deviation ratio setting, the subunit of valid deviations, the subunit of unit incrementation, the subunit of control of dynamic characteristic, the information, the first control and timing inputs of the device; the timing node of the prediction unit, the prediction unit comprising the subunits of the quadratic and linear prediction, the control node of prediction dynamics, two subunits of calculation of second derivatives and the adaptation unit, in order to improve the forecast accuracy in the control node of prediction dynamics the clock rate divider (CRD) is integrated for recovery of time setting (interval) of the prediction.

EFFECT: improving the accuracy of prediction at the stage of recovery of the predetermined time of prediction after completion of the transitional operating regime of the device and its entry to a new steady regime.

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Description

The invention relates to automation and computer technology and can be used to predict stationary and non-stationary random processes, improve the quality and accuracy of control in digital control systems and guidance of various (including ballistic) objects.

A digital prediction device is known (RF patent No. 2459241, MTZh G06F 17/00, 08/20/2012, bull. No. 23), which contains a smoothing unit and a forecast unit, which includes: three subtractors, a prediction dynamics control unit, two quadratic subunits, and linear forecasts. The device is functionally limited.

The closest in technical essence to the claimed device is the adaptive digital predictive device selected as a prototype (RF patent No. 2451328, IPC G06F 15/00, 05.20.2012, bull. No. 14), containing a smoothing unit and a forecast unit, which includes : three subtractors, a prediction dynamics control unit, two subblocks of quadratic and linear forecasts, two subblocks of calculating the second lead-in at the (n-1) th and (n-2) th calculation points of the input process history and the adaptation block.

This device, like its analogs, works, as a rule, in two modes: stationary and transitional (dynamic). The latter can be caused, for example, by starting (turning on) the device, accelerating, bending, switching from one stationary mode to another, etc., i.e. an almost abrupt change in the input process. Naturally, in this mode, the forecast operation is excluded and restored with the beginning of a new stationary mode by successively increasing the forecast time to the specified setting. At this stage of recovery, the prototype is characterized by a significant decrease in the accuracy of the forecast.

The technical problem for the proposed device is to increase the accuracy of the forecast at the stage of restoring the specified forecast time after the transition mode of the device and its transition to a new stationary mode.

во второй (n-1)-й расчетной точке предыстории входного процесса из блока инверторов и сумматора, второй субблок расчета второй производной $$\left({\text{y}}_{\text{n-2}}^{\text{''}}\right)$$

в третьей (n-2)-й расчетной точке предыстории входного процесса из двух последовательно соединенных сумматоров, субблок квадратичного прогноза, содержащий два последовательно соединенных сумматора, на оба входа слагаемых первого сумматора которого заведены, соответственно, информационные выходы первого и второго субблоков расчета вторых производных, а выход первого сумматора подключен к первому входу второго сумматора, второй вход которого соединен с выходом субблока линейного прогноза, блок адаптации, содержащий элемент ИСКЛЮЧАЮЩЕЕ ИЛИ, на оба входа которого заведены шины знаковых разрядов выходных сумматоров обоих субблоков расчета вторых производных, инвертор, первый и второй элементы И, триггер и мультиплексор, оба информационных входа которого подключены к выходам субблоков квадратичного и линейного прогнозов, а выход мультиплексора является первым информационным выходом устройства, узел управления динамикой прогноза (УУДП), содержащий регистр ввода уставки времени прогноза, вход которого является вторым управляющим входом устройства, задающим интервал прогноза, компаратор, инвертор, элемент И и счетчик восстановления уставки, информационный выход которого заведен на адресные шины мультиплексоров всех трех вычитателей, первый вход элемента И подключен к выходу инвертора, а выход - к счетному входу счетчика восстановления, шина сброса в «0» которого соединена с выходом второго элемента И СУДХ блока сглаживания (U₀), для решения поставленной задачи в узел управления динамикой прогноза введен делитель тактовой частоты (ДТЧ) восстановления уставки, содержащий элемент задержки, элемент И, элемент ИЛИ и счетчик, счетный вход которого подключен к выходу третьего элемента И СУДХ блока сглаживания (U_a) и через элемент задержки - к первому входу элемента И ДТЧ, второй вход которого соединен с информационным выходом n-го разряда счетчика, выход элемента И заведен на второй вход элемента И УУДП и на второй вход элемента ИЛИ, первый вход которого подключен к выходу второго элемента И СУДХ блока сглаживания (U₀), а выход элемента ИЛИ соединен с шиной сброса в «0» счетчика.Therefore, in an adaptive digital differentiating and predictive device, which includes: a smoothing unit containing an adder, first and second reversible counters, a single-channel smoothing subunit from a series-connected adder and a register, a subunit for defining the deviation ratio, containing a register, counter and delay element, a subunit actual deviations, containing a block of inverters, two comparators and an element And, a subunit of unit increments, containing two elements And and an inverter, a subunit of control dynam physical characteristic (SUDH), containing two pulse shapers, an OR element, a counter, three AND elements and a mode trigger, the information output of the smoothing unit, information, the first control and clock inputs of the device; a timing unit of a forecast block comprising a delay element, a trigger, a pulse generator, an AND element, and a shift register; a prediction block containing the first, second and third subtracters, each of which contains a register memory block, a multiplexer, an inverter block and an adder, a linear prediction block from one adder, the output buses of which are mountingly shifted one bit toward the lower digits, the first calculation subunit second derivative $$\left({\text{y}}_{\text{n-1}}^{\text{''}}\right)$$

in the second (n-1) -th calculation point of the history of the input process from the block of inverters and the adder, the second sub-block of the calculation of the second derivative $$\left({\text{y}}_{\text{n-2}}^{\text{''}}\right)$$

in the third (n-2) -th calculation point of the input process history of two series-connected adders, a quadratic prediction subunit containing two series-connected adders, the information outputs of the first and second subunits of calculating the second derivatives are connected to both inputs of the terms of the first adder and the output of the first adder is connected to the first input of the second adder, the second input of which is connected to the output of the linear prediction subunit, an adaptation block containing the element EXCLUSIVE OR, on both inputs of which the busbars of the sign bits of the output adders of both subunits of calculating the second derivatives are connected, an inverter, the first and second elements of AND, a trigger and a multiplexer, both information inputs of which are connected to the outputs of the subunits of quadratic and linear forecasts, and the multiplexer output is the first information output the device, the forecast dynamics control unit (PDS), comprising a register for inputting the forecast time setting, the input of which is the second control input of the device defining the interval of node, comparator, inverter, AND element and setpoint recovery counter, the information output of which is connected to the address buses of the multiplexers of all three subtractors, the first input of the And element is connected to the inverter output, and the output to the counting input of the recovery counter, whose reset bus is “0” which connected to the output of the second element AND SUDH of the smoothing unit (U ₀ ), to solve the problem, a clock divider (DTCH) for setting the restoration containing the delay element, element And, element t OR and a counter, the counting input of which is connected to the output of the third AND SUDH element of the smoothing unit (U _a ) and through the delay element, to the first input of the And DTCH element, the second input of which is connected to the information output of the n-th category of the counter, the output of the And element is wound up to the second input of the AND SLE element and the second input of the OR element, the first input of which is connected to the output of the second element AND SUDH of the smoothing unit (U ₀ ), and the output of the OR element is connected to the reset bus at “0” of the counter.

The invention is illustrated by drawings, which depict: in Fig.1 - a block diagram of the proposed device; figure 2 is a block diagram of a smoothing unit; figure 3 is a block diagram of a single-channel anti-aliasing subunit; Fig. 4 is a block diagram of a timing unit of a forecast block; figure 5 is a block diagram of a forecast block; 6 and 7 are tables of the results of modeling the operation of the device at the stage of restoring the specified forecast time after the transition mode is completed and it enters a new stationary mode for a linear input random process; on Fig and 9, respectively, for non-linear (quadratic).

The predictor operator formulas are known that are obtained analytically using approximating polynomials at four points (ordinates) of the history of the input random discrete process using the least squares method (Milne V.E. Numerical analysis. M.: IL, 1951, p. 212). The prediction operator for an approximating polynomial of the second degree (quadratic) for four historical points has the form:

$$y_{P+\mathrm{one}}=\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$\mathrm{four}$}\right.\left(9y_P-3y_{P-\mathrm{one}}-5{\mathrm{at}}_{P-2}+3{\mathrm{at}}_{P-3}\right),\left(\text{one}\right)\left[\text{KB4}\right]$$

or according to the empirical formula (as a first approximation):

$${\mathrm{at}}_{P+\mathrm{one}}=\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$\mathrm{four}$}\right.\left(8{\mathrm{at}}_P-2{\mathrm{at}}_{n-\mathrm{one}}-\mathrm{four}{\mathrm{at}}_{n-2}+2{\mathrm{at}}_{n-3}\right)\text{. (2)}\left[\text{KB4}\right]$$

The prediction operator for an approximating polynomial of the first degree (linear) for four historical points has the form:

$${\mathrm{at}}_{P+\mathrm{one}}=\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$2$}\right.\left(2{\mathrm{at}}_P+{\mathrm{at}}_{P-\mathrm{one}}-{\mathrm{at}}_{P-3}\right)\text{, (3)}\left[\text{LN4}\right]$$

where y _p - the first (current) calculated point (ordinate);

y _p-1 , y _p-2 , y _p-3 - respectively, the second, third and fourth design points (ordinates) of the three-level history of the input smoothed discrete sequence. In numerical analysis, this is a system of equally spaced points with a step h; in real time, h is the interval between points (ordinates), i.e. forecast time (depth) (H).

By analogy with the methods of calculating finite differences for numerical differentiation and extrapolation, we denote:

Δy ₂ = (2y _p -y _p-1 ) - as the biodiversity of the first level of the history of the input discrete sequence, i.e. the difference between the doubled current and previous ordinates of the process;

Δy ₂ = (2y _p-1 -y _p-2 ) - biodiversity of the second level of history;

Δy ₃ = (2y _p-1 -y _p-3 ) - biodiversity of the third level of history.

Known formulas for numerical differentiation for equally spaced points expressed in terms of the function values at these points (J. Pollard. A Handbook of Computational Methods of Statistics. M .: FS, 1982, p. 62), in particular, for four points we have:

$${\mathrm{at}}_{n-\mathrm{one}}^{\text{'}\text{'}\text{'}\text{'}}=\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$h^2$}\right.\left({\mathrm{at}}_n-2{\mathrm{at}}_{n-\mathrm{one}}+{\mathrm{at}}_{n-2}\right)\text{, (four)}$$

$${\mathrm{at}}_{n-2}^{\text{'}\text{'}\text{'}\text{'}}=\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$h^2$}\right.\left({\mathrm{at}}_{n-\mathrm{one}}-2{\mathrm{at}}_{n-2}+{\mathrm{at}}_{n-3}\right)\text{. (5)}$$

After transforming equations (2), (3) and (4) with the aim of simplification and taking into account biodiversity, we obtain the following empirical expressions for the numerical differentiation formulas and the quadratic and linear prediction operators:

$${\mathrm{at}}_{n-\mathrm{one}}^{\text{'}\text{'}\text{'}\text{'}}=\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$h^2$}\right.\left({\mathrm{at}}_n-2{\mathrm{at}}_{n-\mathrm{one}}+{\mathrm{at}}_{n-2}\right)=\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$h^2$}\right.\left({\mathrm{at}}_n-\Delta {\mathrm{at}}_2\right)\text{, (6)}$$

$${\mathrm{at}}_{n-2}^{\text{'}\text{'}\text{'}\text{'}}=\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$h^2$}\right.\left({\mathrm{at}}_{n-\mathrm{one}}-2{\mathrm{at}}_{n-2}+{\mathrm{at}}_{n-3}\right)\text{, (7)}$$

$${\mathrm{at}}_{n+\mathrm{one}}=\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$2$}\right.\left(\Delta {\mathrm{at}}_{\mathrm{one}}+\Delta {\mathrm{at}}_3\right)\text{, (8)}\left[\text{LN4}\right]$$

$${\mathrm{at}}_{n+\mathrm{one}}=\Delta {\mathrm{at}}_{\mathrm{one}}+\Delta {\mathrm{at}}_2-\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$2$}\right.\left(\Delta {\mathrm{at}}_3+{\mathrm{at}}_{n-\mathrm{one}}\right),\left[\mathrm{TO}\mathrm{AT}\mathrm{four}\right]$$

or

$${\mathrm{at}}_{n+\mathrm{one}}={\mathrm{at}}_{n+\mathrm{one}}\left[LN\mathrm{four}\right]+\left[{\mathrm{at}}_{n-\mathrm{one}}^{\text{'}\text{'}\text{'}\text{'}}\right]+\left[{\mathrm{at}}_{n-2}^{\text{'}\text{'}\text{'}\text{'}}\right]\text{, (9)}\left[\text{KB4}\right]$$

The proposed device implements prediction and differentiation operators according to formulas (6), (7), (8) and (9), the main elements of the circuit being an adder and an inverter unit, and multiplying the coefficients by the terms is carried out by the corresponding mounting shifts of the latter buses when entering into the adder . Such operations on the block diagram (see figure 5) are indicated by a circle.

The device contains (see Fig. 1) a smoothing block 1, a forecast block 2 and an adaptation block 3. The smoothing block 1 (see RF patent No. 2444123, IPC H03H 17/04, 02.27.2012, bull. No. 6) contains (see 2) an adder 4, a subunit 5 of actual deviations, comprising a block of inverters 6, two comparators 7.1 and 7.2 and an element And 8, a first reversible counter 9, a subunit 10 for setting the deviation ratio, comprising a register 11, a counter 12 and a delay element 13, subunit 14 of unit increments, comprising an inverter 15 and two elements And 16.1 and 16.2, a second reversible counter 17, a dynamic control subunit 18 a characteristic comprising two pulse shapers 19.1 and 19.2, an OR element 20, a counter 21, three AND elements 22.1, 22.2, 22.3 and a mode 23 trigger; information input 24 of the smoothing unit and the device, the first control 25 and clock (f _T ) 26 inputs of the device and the smoothing unit; single-channel smoothing subunit 27 (according to ed. St. USSR No. 748417, class G06F 15/32, 1980), comprising (see FIG. 3) adder 28 connected in series and register 29; information output 30. The timing unit 31 of the forecast block contains (see FIG. 4) a delay element 32, a trigger 33, a pulse generator (f _G ) 34, an And 35 element and a shift register 36. Prediction block 2 (see FIG. 5) contains the first 37, second 38 and third 39 subtracters, each of which contains a block of register memory 40 from (A) series-connected registers 41, a multiplexer 42, a block of inverters 43 (assuming that the multiplexer does not have inverse outputs) and an adder 44; a quadratic prediction subunit 45 containing the first 46 and second 47 adders, the output of the latter is the information output of the subunit; a linear prediction subunit 48 comprising an adder 49; prediction dynamics control unit (UPDF) 50, which contains a register 51 for input and storage of the forecast time settings, input 52 of which is the second control input of the device that sets the forecast time Н = АТ (Т - device operation cycle, А - maximum memory register address 41 of block 40 ), a comparator 53, an inverter 54, an AND 55 element, a set point recovery counter 56, a set point recovery clock divider 57 comprising a counter 58, a delay element 59, an And 60 element, and an OR element 61; a subunit 62 for calculating the second derivative in the second (n-1) -th calculation point of the input process history, consisting of a block of inverters 63, an adder 64 and a second information output 65 of the device, a subunit 66 for calculating the second derivative in the third (n-2) -th calculation an input process history point comprising a first adder 67, a second adder 68, and a third information output 69 of the device. The adaptation unit 3 contains (see FIG. 5) an EXCLUSIVE OR element 70, an inverter 71, two AND elements 72.1 and 72.2, a trigger 73, a multiplexer 74, and a first information output 75 of the device.

The cycle of the device consists of 5 cycles. The smoothing unit 1 operates in two modes: stationary and dynamic (transitional), and all operations are performed in it in one (1st) cycle. In stationary mode, the unit smooths the input random discrete process, the deterministic basis (median) of which can have a constant, linear or non-linear (quadratic) character of change in time. The smoothing unit 1 (see figure 2) implements the following modification of the operator of signature exponential smoothing:

$${\mathrm{at}}_n={\mathrm{at}}_{n-\mathrm{one}}+sign\left[\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$K$}\right.\left(x_n-{\mathrm{at}}_{n-\mathrm{one}}\right)\right]\text{, (10)}$$

where x _n and y _n are the input and output discrete;

α = 1 / K is the smoothing parameter, K is the adaptation parameter;

Δx _n = (x _n -y _n-1 ) - current deviations from the median of the process.

As a criterion for the effectiveness (accuracy) of smoothing, the ratio d between zero and actual deviations Δx _{n is} chosen. The latter form the current unit increments of both signs of the output discretes in accordance with the signature function in (10):

sign [Δx _n / K] = 0 for [Δx _n -K] <0 (Δx _n are zero deviations),

sign [Δx _n / K] = 1 for [Δx _n -K]> 0 (Δx _n are real deviations).

In stationary mode (D = 0 - a sign of mode), block 1 smooths the input random sequence of discrete to the level specified by the relation d (real range d = 7 ÷ 190), which is entered before the device starts from input 25 into register 11 of subunit 10 of the deflection ratio . The latter is a controllable frequency divider, for example, at d = 7, the output of the direct transfer of counter 12 is every seventh clock pulse from input 26, which, through delay element 13, overwrites the inverse code d from register 11 to counter 12 (for the next divider cycle) and subtracts “1” from the first reverse counter 9 containing the adaptation parameter code K.

The adaptive smoothing process is as follows. Let (for a certain code K in counter 9), the variance of the input discrete process increase, i.e. the number of actual deviations Δx _n (of both signs) increased. After comparing them with the adaptation parameter K at the output of the comparator blocks 7.1 and 7.2 of the subunit 5 (playing the role of negative feedback), logical “1” is set (the mode of operation of the comparators: [Δx _n > K] = “1”, [Δx _n <K] = "0") received at the input of element And 8. Since in the stationary mode the trigger of mode 23 is in the state "0" (D = 0), then from its inverse output to the first input of element And 8 of subunit 5, a logical "one". A high level of the signal at all inputs of the And 8 element allows the passage of clock pulses from input 26 to the summing input of the first reverse counter 9 (the K code in the last increases) and to the second inputs of the And 16.1 and 16.2 elements of the subunit of unit increments 14. The signal from the output of one of them (depending on the sign of the deviation) is fed to the summing (or subtracting) input of the second reverse counter 17 of the smoothing result, i.e. the signature function (10) is implemented. The growth process of K will lead to a decrease in the number of actual deviations and will continue until a dynamic equilibrium sets in, i.e. the number of pulses received from subunit 10 to the subtracting input of counter 9 will be equal to the number of pulses received at its summing input from subunit 5, and the variance of the output smoothed discrete sequence will remain unchanged (for d = 7: there must be seven zero deviations per actual deviation) .

Transient (dynamic) mode can be caused by starting, accelerating, bending, switching from one stationary mode to another, etc., i.e. an almost abrupt change in the process. To smooth the input discrete sequence in transient (dynamic) modes (D = 1), a single-channel smoothing subunit 27 is used (see Fig. 3), which implements the following exponential smoothing operator: y _n = ½ (x _n + y _n-1 ), those. with a minimum degree of smoothing and, accordingly, with a minimum phase shift (delay) of the output discrete. Subunit 27 operates in both modes, is initiated by clock pulses from input 26 to register 29, but is used only in transition (dynamic) mode. For a stationary random process, the probability of a series, for example, of m = 8 (eight) deviations from the median (deterministic basis) of a single sign in a row, in accordance with the geometric law of probability distribution, is:

P (x = m) = (½) ^{m + 1} = 1 / 512≈0.002,

those. so small that the appearance of such a series can be considered the beginning of a transitional regime. Subunit 18 captures such a series and works as follows. Since for the stationary mode the deviations of different signs are most likely, when the sign in the adder 4 changes from “plus” to “minus” and vice versa, the pulse shapers 19.1 or 19.2 are triggered and through the element OR 20 they reset counter 21 and trigger 23 to “0” (D = 0). In dynamic mode (the shapers 19 do not work), eight pulses will certainly come to the counter 21 (for example, 4-bit) from the clock input 26. At the output of the high-order bit of the counter 21, a logical “1” will be set, the high signal level of which will ensure passage through the first element And 22.1 clock pulse, which sets the trigger of mode 23 to "1" (D = 1). The last signal from the inverse output will block the operation of the subunit 5 of the actual deviations and, accordingly, the subunit of 14 unit increments, and by the high level of the direct output signal it will allow the discretization from the single-channel smoothing subunit 27 to the second reversal counter 17 of the smoothing result through the second element And 22.2.

At the end of the transition mode, in the adder 4, deviations of different signs will inevitably occur, which will lead to the operation of the pulse shapers 19 and, accordingly, to the switching of the trigger of mode 23 to the state “0” (stationary smoothing mode, D = 0).

Forecasting operations are performed in three cycles, respectively, 2nd, 3rd and 4th. They are formed by a series of three clock pulses from the clock node 31 (see figure 4). A clock pulse from input 26 resets trigger 33 and writes “1” to the least significant bit of the shift register 36. The same clock pulse, delayed by delay element 32, sets trigger 33 to “1”, thereby allowing pulses from generator 34 to pass through element I 35 into the shift register 36, on the tires of the least significant bits of which ("a", "b", "c", "d") the above series appears (moreover, f _Г >> f _Т ). In the 2nd step, the ordinate of the current (first) calculated point y _p is recorded in the first register 41 of the block 40 of the register memory of the first subtractor 37. At the same time, all previous ordinates are overwritten (shifted) to neighboring registers 41 (i.e., the background of the input process is formed ) At the address input of the multiplexer 42 from the counter 56 restore the settings receives the address code (A) of the ordinate of the history recorded before starting the device from the second control input 52 in the register 51 for input and storage of the forecast time settings (H = AT). In accordance with this address, the ordinate from the output of the multiplexer 42 (already as the second calculation point y _p-1 ) through the inverter block 43 is fed to the input of the second term of the adder 44, the first term of which is doubled the ordinate of the previous calculation point y _p . The output of the adder of the first subtractor 37 establishes the biodiversity of the 1st level of the history of the input discrete sequence. In the 3rd and 4th steps, operations are performed similar to those described above, but already for the second 38 and third 39 subtracters, the outputs of which are set, respectively, biodities of the 2nd and 3rd levels of history. All adders in the device are combination. At the end of the 4th cycle, at the output of subunit 45, in accordance with the empirical formula (9), a quadratic (non-linear) prediction estimation code for a non-stationary discrete input sequence is set, and at the output of subunit 48, in accordance with formula (8), a linear prediction estimation code for a stationary or a slowly varying input discrete sequence, at the output 65 of the subunit 62, in accordance with formula (6), is the code for evaluating the second derivative at the second (n-1) -th calculation point of the input process history, and at the output of 64 subunit 61, in accordance with formula (7) - the code for evaluating the second derivative at the third (n-2) -th calculation point of the input process history.

In the 5th step, the signal from the output (“g”) of the shift register 36 of the clock unit 31, depending on the combination of the signs of the second derivatives, sets the trigger 73 of the adaptation unit 3 to the state “1” (quadratic forecast) or to “0” (linear forecast) . The direct output of the trigger 73, as the address input of the multiplexer 74, provides the selection and transmission to the device output 75 of the corresponding forecast estimation code.

The prediction dynamics control unit 50 is designed to exclude the prediction operation in dynamic (transient) modes (D = 1) of the device operation by resetting to “0” the counter 56 for restoring the setpoint and the counter 58 for the clock divider 57 with a clock signal (U ₀ ) from the control subunit 18 dynamic characteristic of the smoothing block. The zero address of the counter 56 on the address buses of all three multiplexers 42 of the subtractor will ensure the calculation and installation of the current discrete code y _{n of a} minimally smoothed input process at the outputs of both prediction subunits 45 and 48.

With the transition of the device to the stationary mode of operation (D = 0), the trigger of mode 23 of the subunit 18 will allow the passage of clock pulses from input 26 through the open element And 22.3, divider 57, element And 55 to the counting input (U _a ) counter 56 restore settings. The growth of the address code h in this counter (h = aT, a = 1, 2, 3, ... A), i.e. the restoration of the set forecast time H will continue with each cycle until it becomes equal to the set h = H set in the storage register 51. The comparator 53 (operating mode: [H = h] → “1”, [Н ≠ h] → “0”) in this case, through the key 54 and the element And 55 will close the counter input of the counter 56.

If at the stage of restoring the setpoint, for example, for Н = 4 (see tables in Figs. 6 and 8), do not use divider 57 (division ratio K = 1), then the forecast setpoint will be restored by the 4th cycle (N = 4 ), however, the forecast error (Δ _CR ) before the 11th cycle (N = 11) of the recovery will be significant. It is due to the fact that the ordinates of three levels of the process history, in which information from the previous (transitional) mode is still located, are involved in the calculations of the forecast operators at this stage.

If, at the stage of restoring the setpoint (see tables in Figs. 7 and 9), a divider 57 is used (division ratio K = 4: the output of the 3rd digit of counter 58 is connected to element 60), then although the rate of restoration of the setpoint is slightly increased ( ends at the 13th cycle, N = 13), the forecast error decreases (2 ÷ 2.5) times due to the use of fresh information from all levels of the history in the calculations of forecast operators in the new stationary mode.

Claims (1)

An adaptive digital differentiating and predicting device, which includes: a smoothing unit containing an adder, first and second reversible counters, a single-channel smoothing subunit from a series-connected adder and register, a subunit for defining the deviation ratio, containing a register, counter and delay element, a subunit of actual deviations containing a block of inverters, two comparators and an element And, a subunit of unit increments, containing two elements And and an inverter, a subunit of control of dynamic x teristics (sudha) comprising two of the pulse, an OR gate, a counter, three AND gates and the trigger mode, a smoothing information output unit information, the first control inputs and the timing device; a timing unit of a forecast block comprising a delay element, a trigger, a pulse generator, an AND element, and a shift register; a prediction block containing the first, second and third subtracters, each of which contains a register memory block, a multiplexer, an inverter block and an adder, a linear prediction block from one adder, the output buses of which are mountingly shifted one bit toward the lower digits, the first calculation subunit second the derivative (y ′ ′ _n-1 ) at the second (n-1) calculation point of the history of the input process from the inverter unit and the adder, the second subunit of the calculation of the second derivative (y ′ ′ _n-2 ) in the third (n-2) - th calculation point of the history of the input percent csa from two series-connected adders, a quadratic prediction subunit containing two series-connected adders, on both inputs of the terms of the first adder which are connected, respectively, the information outputs of the first and second subunits of the calculation of the second derivatives, and the output of the first adder is connected to the first input of the second adder, the second the input of which is connected to the output of the linear prediction subunit, an adaptation block containing an EXCLUSIVE OR element, on both inputs of which buses of significant discharges are wound the output adders of both subunits of the calculation of the second derivatives, the inverter, the first and second elements of I, a trigger and a multiplexer, both of which information inputs are connected to the outputs of the subunits of quadratic and linear forecasts, and the output of the multiplexer is the first information output of the device, the unit for forecast dynamics control (УУД), containing a register for entering the forecast time setting, the input of which is the second control input of the device that sets the forecast interval, comparator, inverter, AND element, and recovery counter a set point, the information output of which is connected to the address buses of the multiplexers of all three subtractors, the first input of the AND element is connected to the output of the inverter, and the output is connected to the counting input of the recovery counter, the reset bus to “0” of which is connected to the output of the second element AND of the SUDH of the smoothing unit ( U ₀ ), characterized in that in the forecast dynamics control unit a clock frequency divider (DTCH) of setting recovery is introduced, containing a delay element, an AND element, an OR element, and a counter, the counting input of which is connected to the output of the third electric of the AND SUDH element of the smoothing unit (U _a ) and through the delay element to the first input of the And DTCH element, the second input of which is connected to the information output of the n-th category of the counter, the output of the And element is connected to the second input of the And U-DO element and to the second input of the OR element the first input of which is connected to the output of the second AND SUDH element of the smoothing unit (U ₀ ), and the output of the OR element is connected to the reset bus at “0” of the counter.

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