RU2622851C1 - Adaptive digital predictive device - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: in the predictive unit of the adaptive digital predictive device containing two subtractors, the averaging combiner, the first derivative subblock, the process speed increment count sub-block and the forecast code correction circuit on the dynamics, an additional sub-block for correction of the prediction code in stationary modes is entered. At the same time, the arithmetic operations of calculation of predicted parameters (for example, lead-in) were replaced by mounting shifts of the components' tires, which increased the device's performance by an order of magnitude.

EFFECT: doubling the predicting time with a given analytical buffer history of the process.

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Description

The invention relates to automation and computer technology and can be used to smooth and predict stationary and non-stationary random processes, improve the quality and accuracy of control in digital guidance systems for various (including ballistic) objects: missiles, bombs and ATGMs.

A digital predictive and differentiating device is known (RF patent No. 2515215, IPC G06F 17/17, 02/06/2013, bull. No. 13), containing a smoothing unit and a forecast unit, which includes: two subtractors, a forecast dynamics control unit, two subunits quadratic and linear forecasts and the subunit of calculating the first derivative at the (n-1) th calculation point in the history of the input smoothed process. The device is functionally limited.

The closest in technical essence to the claimed device is the adaptive digital predictive and differentiating device selected as a prototype (RF patent No. 2517322, IPC G06F 17/17, 05/21/2013, bull. No. 15), containing a smoothing unit and a forecast unit, in the composition the latter includes: two subtractors, a forecast dynamics control unit, two sub-blocks of quadratic and linear forecasts, a sub-block for calculating the first lead-in at the (n-1) -th calculation point of the input process history and an adaptation block. The device has a relatively large amount of equipment and is also functionally limited.

In practice, by the nature of the change in time, discrete random processes (SPs) can be divided into two types (modes): steady (stationary) and transient (hereinafter “dynamics"). The first is characterized by the steady-state velocity of the median (deterministic basis) of the joint venture, the second is non-linear and takes a relatively short time to transition the median of the joint venture to a new steady-state speed. The spectrum of regime change in the speed of the median SP can occupy a rather large range: from slowly varying to high speeds (almost a jump).

In the prototype, as well as in analogs, the best approximation of the analytical operators of quadratic and linear forecasts is implemented based on approximating polynomials in 3 points (ordinates) of a two-level buffer for storing the history of the input random discrete process using the least squares method, and the forecast time interval (depth) h is half of the time (B _t ) of the storage of ordinates in the history buffers B _t = 2h. For example, the forecast for Н = h = 10 sec requires the storage of information about the process in the history buffer for the period B _t = 2Н = 2h = 20 sec, and with the onset of dynamics (transition to a different velocity of the median SP) new (fresh) information ( at _n ) it arrives only at the 1st level of the history buffer, at the second (at _n-1 , at _n-2 ) the data of the old mode are stored: of course, the obtained current forecast discretes for this period are significantly different from realities and cannot be used. The forecast can be considered reliable only after filling both history buffers with information in a new steady state.

The technical problem for the proposed device is to expand the functionality by doubling the real time (depth) of the forecast with the same amount of historical memory buffer, without any damage to the accuracy of the forecast, i.e. (see the example above) now, when setting H = 2h = 20 sec, the information storage time (the memory size of the history buffers) remains unchanged B _t = 2h = 20 sec, and not B _t = 2Н = 40 sec in accordance with the analytical calculation formulas forecast.

Therefore, in an adaptive digital predictive device, which includes a smoothing unit containing m = 32 series-connected channels, a register and a multiplexer, and the outputs of each m = 1, 2, 4, 8, 16, and 32nd channels are connected to the information inputs of the multiplexer whose address input is connected to the output of the register, the input of the latter is connected to the second control input of the device to set the degree (efficiency) of smoothing k = 0, 1, 2, 3, 4 or 5 (m = 2 ^k ), and the input of the first channel is information input (x _n) unit, and a unit about Noz, comprising first and second subtracters, each of which includes a memory buffer register, the multiplexer, and an adder unit inverters, the input of the first subtracter connected to the output of multiplexer smoothing unit; a quadratic prediction calculation subunit comprising two adders and an inverter, the output of the second adder being the output of the subunit; a subunit for calculating a linear forecast from one adder, the output buses of which are the output of the subunit; the averaging adder discrete outputs of the sub-blocks of the quadratic and linear forecasts, the output buses of which are mountingly shifted to the right (towards the lower bits) by one bit; a prediction dynamics control unit comprising a prediction time setting input register, the input of which is the first control input of the device defining a forecast interval, an inverter, a counter and a multiplexer, the output buses of the prediction time setting input register being connected directly to the first input of the multiplexer, mountingly shifted to the right by three discharge - to the second input of the multiplexer and mountingly shifted to the left by one bit through the inverter - to the counter input, the output of the multiplexer is connected to the address inputs of the multiplex lexors of both subtractors; a subunit of calculating the first derivative from one adder, the output of which is the output of the subunit with the code of the first derivative (y ' _n-1 ) at the second (n-1) -th calculation point of the input process history buffer; a timing unit of a forecast block comprising a delay element, a trigger, a pulse generator, an AND element, and a shift register; a dynamic prediction code correction scheme comprising three adders and a multiplexer; a subunit of counting process speed increments containing a scheme for generating the absolute value of the first derivative (y ' _n-1 ), two series-connected storage registers of the current y' _n-1 [(wT)] and the previous y ' _n-1 [(w-1) T)] process speed samples, two parallel channels (for increasing and decreasing) for calculating the process speed increment, each of which includes a comparator, two AND elements and a four-digit increment counter, an OR element, and a mode trigger, with the output of the first And element in each channel connected to the counter input counter and to the reset bus at “0” of the counter of another channel, the output of the OR element is connected to the installation input at “1” of the mode trigger and to the write bus of the counter of the forecast dynamics control unit, and the direct transfer output of this counter is connected to the reset bus to “0” a trigger whose direct (“1”) output is connected to the address inputs of the multiplexers of the dynamics control unit and the correction scheme for the forecast code for the dynamics, the output of the subunit of calculating the first derivative through the circuit for generating its absolute value is connected to the input of the first register of the subunit of counting p increments, and the outputs of both registers are connected respectively to the inputs of the comparators of both channels, to solve the problem, an additional subblock for correcting the forecast code in stationary mode from one adder is introduced into the forecast block, the output buses of the smoothing unit multiplexer shifted to the left by one bit , the second input of the adder is connected to the inverter output of the second subtractor, and the output of the adder of the subunit is connected to the first information input of the multiplexer of the correction circuit a prediction code on the dynamics in which: the first input of the first adder is connected to the output of the averaging adder, the second input is the output of the inverter of the second subtracter, the output buses of the first adder are mountingly shifted left by two bits and left by one bit, respectively wound to both inputs of the second the adder, the output of which is connected to the first input of the third adder, the second input of which is connected to the output of the multiplexer of the second subtractor, the output of the third adder is connected to the second information input of the multiplexer, addressed to the stroke of which is connected to the “1” output of the trigger of the sub-block mode of counting increments of the process speed, and the multiplexer output is the output of the device.

The invention is illustrated by drawings, which depict: in FIG. 1 is a block diagram of the proposed device; in FIG. 2 is a block diagram of one channel of a smoothing unit; in FIG. 3 is a block diagram of a timing unit of a forecast block; in FIG. 4 - diagram of the formation of the absolute value of the velocity of the joint venture; in FIG. 5 is a graphical interpretation of the derivation of the formulas for the correction of the forecast code in stationary mode and in dynamics; in FIG. 6 - metrological characteristic of the smoothing unit on m = 64 channels; application (on 5 sheets) - the results of modeling the operation of a device on a computer during processing of a non-stationary random process.

The known prediction operator formulas obtained analytically using approximating polynomials in three points (ordinates) of the buffer history of the input random discrete process using the least squares method (Milne V.E. Numerical analysis. M.: IL, 1951, p. 212), by the approximating polynomial of the second degree (quadratic):

y _{n + 1} = (3y _n - 3y _n-1 + y _n-2 ), (1) [KB3]

first degree (linear):

y _{n + 1} = _^1/3 (4y _n + y _n-1 - 2y _n-3)

or

y _{n + 1} = _^1/2 (3y _n - y _n-2), (2) [LN3]

In addition, there are known formulas for numerical differentiation for equally spaced points expressed in terms of the function values at these points (Demidovich B.P. and Maron I.A. Fundamentals of Computational Mathematics. M: FM, 1960, Ch. XV, §4, p. 573), in particular for three points we have:

where _n is the first (current) calculated point (ordinate);

_n-1 , _n-2 , respectively, the second and third calculated points (ordinates) of the two-level buffer for storing the history of the input smoothed discrete sequence. In numerical analysis, this is a system of equally spaced points with a step h, in real time H = h is the forecast time (depth), and the period of storage of current information in the history memory buffers is two forecast intervals B _t = 2h.

By analogy with the methods of calculating finite differences for numerical differentiation and extrapolation, we denote:

Δy ₁ = (2y _n -y _n-1 ) - as the biodiversity of the first level of the history of the input discrete sequence, i.e. the difference between the doubled current and previous ordinates of the process;

Δy ₂ = (2y _n-1 -y _n-2 ) - biodiversity of the second level of history.

After transforming equations (1) and (2) in order to simplify and taking into account biodiversity, we obtain the following empirical expressions for the quadratic and linear prediction operators:

The proposed device implements prediction and differentiation operators according to formulas (3), (4) and (5), the main elements of the circuit being an adder and an inverter unit, and the multiplication of the coefficients by the terms is performed by the corresponding mounting shifts of the latter buses when entering the adder. Such operations in the flowchart (see Fig. 1) are indicated by a circle.

The device contains (see Fig. 1) a smoothing unit 1, consisting of a multi-channel digital smoothing device 2 on m = 32 series-connected channels (see ed. St. USSR No. 686034, class G06F 15/32, 1979 and No. 748417, 1980), register 3 sets the degree of smoothing (k) and multiplexer 4; a prediction block containing two series-connected subtractors 5 and 6, each of which includes a register memory buffer 7 from (A) series-connected registers 8, a multiplexer 9, an inverter block 10 (assuming that the multiplexer does not have inverse outputs) and an adder eleven; a quadratic prediction calculation subunit 12 comprising a block of inverters 13, a first 14 and a second 15 adders, the output of the latter being the output of a subunit; a subunit 16 for calculating a linear forecast from the inverter 17 and the adder 18, the output bus of which is the output of the subunit; an adder 19 averaging the output codes of both prediction subunits 12 and 16; a subunit 20 for calculating the first derivative (y ' _n-1 ) from the adder 21, at the output of which the evaluation code for the first derivative of the input process is set at the (n-1) th calculation point of the history buffer; a subunit 22 for counting process speed increments, comprising a circuit 23 for generating an absolute speed value (y ' _n-1 ) including (see FIG. 4) a multiplexer 24 and an inverter 25, registers 26 and 27 connected in series (forming a buffer of the history of speed increments process), two comparators 28 and 29, two I 30 and 31 elements, two 4-bit counts 32 and 33 of the process speed increments (increase and decrease), two I 34 and 35 elements, OR 36 element and 37 mode trigger (TG) ; prediction dynamics control unit 38 comprising a forecast time storage register 39, the input 40 of which is the first control input of the device through which the virtual forecast time h = AT is introduced, where T is the device operation cycle, A is the number (max, address) of registers 8 in a buffer 7 of the history of the process (the real forecast time for the inventive device is calculated by the formula: H = 2h), inverter 41, counter 42 of the duration (2h) of the operation of the forecast block on the dynamics and multiplexer 43; the second control input 44 to enter the degree of smoothing (k) SP, information (x _n ) 45 and clock (f _T ) 46 inputs of the device; channel 47 (see Fig. 2) of the smoothing device 2 consists of an adder 48 and a register 49; the timing unit 50 of the forecast block (see FIG. 3) contains a delay element 51, a trigger 52, a pulse generator 53 (f _g ), an And 54 element, and a shift register 55; the dynamics prediction code correction circuit 56 includes three adders 57, 58, 59 and a multiplexer 60, an additional stationary prediction code correction subunit 61 from the adder 62, the output of the multiplexer 60 of the circuit 56 is the output 63 of the device.

If in the prototype and analogues to determine the moment of transition of the stationary mode to the dynamics, the algorithm of fixing a series of 8 deviations from the median of the process of one sign in a row is used, then in the proposed device (due to the lack of a smoothing unit working with deviations), a subunit 22 of increment counting is introduced for the same purpose process speed, in which a series of 8 consecutive increments of growth (or decrease) in the process speed is also recorded.

The increment is the result of comparing, at each step, the current and previous values of the first derivative of the process at the (n-1) -th calculated point of the history buffer. With the transition to dynamics (TG = 1), the device does not begin to work with the full (h), but with an 8-fold truncated history buffer, i.e. Only current (“fresh”) discrete samples of the input process are involved in the calculation of the forecast code, respectively, the resulting forecast code gives an accurate picture of the change (increase or decrease) in the input process on the dynamics, but only for the forecast time (depth) reduced by 8 times h _k = h / 8 (conditionally it can be called technological).

To bring the forecast code in stationary mode in accordance with twice the forecast time (H = 2h) an additional subunit 61 of the forecast code correction has been introduced into the device. A graphical interpretation of the operation algorithm of this subunit, based on the postulate of a linear approximation of the median of the input process, is presented in FIG. 5, where Δ0 = (Y _n -Y _n-2 ) and Δ2 = (Y _{n + 2} -Y _n-2 ) are the correction prediction differences in the stationary mode, then according to the known relations in similar triangles we have:

Equation (6) is implemented in the proposed device in an additional subunit 61 of the correction of the forecast code in the stationary mode for twice the time (depth) of the forecast H = 2h.

The prediction code for the dynamics is brought into correspondence with twice the forecast time (H = 2h) in the correction prediction code correction scheme 56. A graphical interpretation of the operation algorithm of this circuit, based on the postulate of a linear approximation of the median of the input process, is presented in FIG. 5.

, тогда в соответствии с известными соотношениями сторон в подобных треугольниках имеем:Let ΔK = (Y ^k _{n + 1} -Y ^k _n-2 ) be the correction difference of the forecast for the dynamics, h _k = h / 8, h = 8h _k ,

, then, in accordance with the known aspect ratios in such triangles, we have:

Equation (7) is implemented in the proposed device in the scheme 56 of the correction of the forecast code on the dynamics for twice the time (depth) of the forecast H = 2h.

. Эффективность сглаживания (см. фиг. 6) выбирается заданием со входа 44 степени k=0,1, 2, 3, 4 или 5, которая в свою очередь определяет число задействованных каналов сглаживания m=2^k (1, 2, 4, 8, 16 или 32).The cycle of the device consists of two clock cycles. In the first, the smoothing unit 1 ends, each channel of which implements the exponential smoothing operator

. The smoothing efficiency (see Fig. 6) is selected by setting the input 44 of degree k = 0.1, 2, 3, 4, or 5, which in turn determines the number of smoothing channels involved m = 2 ^k (1, 2, 4, 8 , 16 or 32).

In the second clock cycle 50, the first series of mini-strokes ("a", "b") initiates the work of two subtractors 5 and 6, subunits 20, 12 and 16 of the calculation according to formulas (3), (4) and (5) of the first derivative, quadratic and linear components of the forecast block. The sum of the codes of the latter is averaged Y _{n + 1} = Y _{n + 1} [SR] = (Y _{n + 1} [KB3] + Y _{n + 1} [LN3]) / 2 in the adder 20 and enters the dynamic prediction code correction circuit 56.

The second series of mini-tacts ("c", "d", "e") forms the operation of the subunit 22 for counting the increments of the process speed. The subunit is designed to switch the stationary (TG = 0) mode to the dynamics (TG = 1).

The clock signal ("c") in register 27 from register 26 overwrites the previous one at ' _n-1 [(w-1) T], and the last - the current one at' _n-1 [wT] of the absolute value of the process speed. The subunit can be divided into two parallel channels for counting the number of increments in the process speed: decreasing and increasing. Consider the work of the latter: with a positive ratio A> B (y ' _n-1 [wT]>y' _n-1 [(w-1) T]) in comparator 28, the clock signal ("d") is fed to the counting input of the increment counter 32 and at the same time resets to “0” the counter 33 of another channel. The receipt of N _d = 8 or more pulses on the counter 32 in a row means that the process has switched from stationary to dynamics (transient). The high level ("1") of the output of the 4th digit of the counter 32 allows the signal ("e") to set the mode trigger 37 to "1" (TG = 1) and transfer from register 39 to the counter 42 of the dynamic control unit 38 in the inverse code number measures (2h), i.e. device runtime in dynamic mode. The direct output (“1”) of trigger 37 enables the generation of a forecast code Y ^d _{n + 2} on the speaker (corresponding to twice the forecast time H = 2h) from the adder 59 of the correction circuit 56 of the forecast code through the multiplexer 60 to the output of the device 63 and switches the multiplexer 43 node 38 control the dynamics of the operation of the forecast block with only 1/8 of the buffer of the process history, respectively, with h _k = h / 8 (technological) interval (time) of the forecast.

The device switches from the dynamics to the stationary mode by resetting the mode trigger (TG = 0) to “O” by the direct transfer pulse of the counter 42 of the control unit 38, i.e. only after filling (2h) the process history buffer with new information in the new mode. Accordingly, the multiplexer 43 switches to outputting to the history buffer the specified (virtual) interval (time) of the forecast h, and the multiplexer 60 to the output 63 of the forecast code device Y _{n + 2} = Y ^s _{n + 2} (corresponding to the doubled forecast time H = 2h) .

The appendix contains the results of modeling the operation of the device.

Column No. 5:

ΔP _k = (Y _n [w + 2h] -Y _{n + 1} ) - forecast error with correction on the dynamics (TG = 1).

Column number 8:

ΔР = (Y _n [w + 2h] -Y _{n + 1} [SR]) - forecast error without correction on the dynamics.

Columns No. 6 and No. 9:

% - forecast accuracy in%.

The refinement (modernization and simplification) of the analytical prediction operators and derivatives for the application of arithmetic operations (multiplication and division), multiples of degree 2, and the replacement of the latter, in turn, with the mounting shifts of the tires of the terms of the polynomials during input (or output) into the adder allows to simplify the device (abandon microprocessor), increase the speed by an order of magnitude and reduce hardware costs for the manufacture of electronic components of control systems and guidance of missiles, bombs and ATGMs, especially in mass production.

Claims (1)

An adaptive digital predictive device, which includes: a smoothing unit containing m = 32 channels connected in series, a smoothing unit, a register and a multiplexer, the outputs of each m = 1, 2, 4, 8, 16 and 32 channels being connected to information the inputs of the multiplexer, the address input of which is connected to the register output, the input of the latter is connected to the second control input of the device to set the degree (efficiency) of smoothing k = 0, 1, 2, 3, 4 or 5 (m = 2 ^k ), and the input of the first channel is the information input (x _n ) of the device, and a prediction block comprising first and second subtractors, each of which includes a register memory buffer, a multiplexer, an inverter unit and an adder, the input of the first subtractor being connected to the output of the multiplexer of the smoothing unit; a quadratic prediction calculation subunit comprising two adders and an inverter, the output of the second adder being the output of the subunit; a subunit for calculating a linear forecast from one adder, the output buses of which are the output of the subunit; the averaging adder discrete outputs of the sub-blocks of the quadratic and linear forecasts, the output buses of which are mountingly shifted to the right (towards the lower bits) by one bit; a prediction dynamics control unit comprising a prediction time setting input register, the input of which is the first control input of the device defining a forecast interval, an inverter, a counter and a multiplexer, the output buses of the prediction time setting input register being connected directly to the first input of the multiplexer, mountingly shifted to the right by three discharge - to the second input of the multiplexer and mountingly shifted to the left by one bit through the inverter - to the counter input, the output of the multiplexer is connected to the address inputs of the multiplex lexors of both subtractors; a subunit of calculating the first derivative from one adder, the output of which is the output of the subunit with the code of the first derivative (y ' _n-1 ) at the second (n-1) -th calculation point of the input process history buffer; a timing unit of a forecast block comprising a delay element, a trigger, a pulse generator, an AND element, and a shift register; a dynamic prediction code correction scheme comprising three adders and a multiplexer; a subunit for counting process speed increments containing a scheme for generating the absolute value of the first derivative (y ' _n-1 ), two sequentially connected storage registers of the current y' _n-1 [(wT)] and the previous y ' _n-1 [(w-1) T)] process speed samples, two parallel channels (for increasing and decreasing) for calculating the process speed increment, each of which includes a comparator, two AND elements and a four-digit increment counter, an OR element, and a mode trigger, with the output of the first And element in each the channel is connected to the counter input of the counter and to the reset bus at “0” of the counter of another channel, the output of the OR element is connected to the installation input at “1” of the mode trigger and to the write bus of the counter of the forecast dynamics control unit, and the direct transfer output of this counter is connected to the reset bus at “0” of the trigger , the direct (“1”) output of which is connected to the address inputs of the multiplexers of the dynamics control unit and the correction scheme of the forecast code for the dynamics, the output of the first derivative calculation subunit is connected to the input of the first register of the counting subunit expansion, and the outputs of both registers are connected respectively to the inputs of the comparators of both channels, characterized in that an additional subblock for correcting the forecast code in stationary mode from one adder is introduced into the forecast block, the output buses of the smoothing unit multiplexer shifted to the left by one bit , the second input of the adder is connected to the inverter output of the second subtractor, and the output of the adder of the subunit is connected to the first information input of the multiplexer of the prediction code correction circuit and on the dynamics in which: the first input of the first adder is connected to the output of the averaging adder, the second input is with the output of the inverter of the second subtracter, the output buses of the first adder, mountingly shifted left by two digits and left by one digit, are respectively connected to both inputs of the second adder the output of which is connected to the first input of the third adder, the second input of which is connected to the output of the multiplexer of the second subtracter, the output of the third adder is connected to the second information input of the multiplexer, the address input of which connected to the “1” output of the trigger of the sub-block mode of counting the increments of the process speed, and the multiplexer output is the output of the device.

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